From b052b12885e07bcece491b267685c5b76d87c230 Mon Sep 17 00:00:00 2001 From: FallenSigh Date: Fri, 10 Jul 2026 04:47:36 +0800 Subject: [PATCH] update vivado reports --- .../clock_interaction.rpt | 25 +- fpga/vivado_reports_nodsp/clocks.rpt | 26 +- .../design_analysis_complexity.rpt | 31 +- .../design_analysis_timing.rpt | 66 +- fpga/vivado_reports_nodsp/drc.rpt | 253 +- fpga/vivado_reports_nodsp/high_fanout.rpt | 254 +- fpga/vivado_reports_nodsp/methodology.rpt | 56 +- .../vivado_reports_nodsp/mlkem_clk_timing.rpt | 12418 ++-- fpga/vivado_reports_nodsp/power.rpt | 109 +- fpga/vivado_reports_nodsp/route_status.rpt | 12 +- .../timing_hold_paths.rpt | 26604 +++----- .../timing_setup_paths.rpt | 55220 +++++++--------- .../timing_summary_full.rpt | 49481 +++++--------- .../timing_summary_hold_full.rpt | 40917 ++++-------- fpga/vivado_reports_nodsp/utilization.rpt | 108 +- .../vivado_reports_nodsp/utilization_hier.rpt | 385 +- .../clock_interaction.rpt | 28 - .../vivado_reports_nodsp/clocks.rpt | 76 - .../design_analysis_complexity.rpt | 37 - .../design_analysis_timing.rpt | 52 - .../vivado_reports_nodsp/drc.rpt | 491 - .../vivado_reports_nodsp/high_fanout.rpt | 221 - .../vivado_reports_nodsp/methodology.rpt | 542 - .../vivado_reports_nodsp/mlkem_clk_timing.rpt | 5216 -- .../vivado_reports_nodsp/power.rpt | 180 - .../vivado_reports_nodsp/route_status.rpt | 12 - .../timing_hold_paths.rpt | 17094 ----- .../timing_setup_paths.rpt | 31976 --------- .../timing_summary_full.rpt | 38485 ----------- .../timing_summary_hold_full.rpt | 32214 --------- .../vivado_reports_nodsp/utilization.rpt | 237 - .../vivado_reports_nodsp/utilization_hier.rpt | 276 - 32 files changed, 76444 insertions(+), 236658 deletions(-) delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/mlkem_clk_timing.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_hold_paths.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_setup_paths.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_full.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_hold_full.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt delete mode 100644 fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt diff --git a/fpga/vivado_reports_nodsp/clock_interaction.rpt b/fpga/vivado_reports_nodsp/clock_interaction.rpt index a8a58a3..dbe9926 100644 --- a/fpga/vivado_reports_nodsp/clock_interaction.rpt +++ b/fpga/vivado_reports_nodsp/clock_interaction.rpt @@ -1,28 +1,25 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +| Date : Fri Jul 10 04:14:55 2026 | Host : fedora running 64-bit unknown -| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt +| Command : report_clock_interaction -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clock_interaction.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------- Clock Interaction Report Clock Interaction Table ----------------------- - WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock -From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints ------------------ ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ------------------- -cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed -cpu_clk sys_clk 0 162 Ignored Asynchronous Groups -mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed -mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed -sys_clk cpu_clk 0 59 Ignored Asynchronous Groups -sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed -sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed + WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock +From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints +---------------- ---------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ------------------- +cpu_clk cpu_clk rise - rise 1.51 0.00 0 17264 30.32 Clean Timed +cpu_clk sys_clk 0 154 Ignored Asynchronous Groups +sys_clk cpu_clk 0 59 Ignored Asynchronous Groups +sys_clk sys_clk rise - rise 0.15 0.00 0 96069 20.00 Clean Timed diff --git a/fpga/vivado_reports_nodsp/clocks.rpt b/fpga/vivado_reports_nodsp/clocks.rpt index 7ce6dda..d08872d 100644 --- a/fpga/vivado_reports_nodsp/clocks.rpt +++ b/fpga/vivado_reports_nodsp/clocks.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +| Date : Fri Jul 10 04:14:54 2026 | Host : fedora running 64-bit unknown -| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt +| Command : report_clocks -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/clocks.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------- Clock Report @@ -21,12 +21,11 @@ Attributes I: Inverted S: Pin phase-shifted with Latency mode -Clock Period(ns) Waveform(ns) Attributes Sources -clk 20.000 {0.000 10.000} P {clk} -clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} -cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} -mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} -sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} +Clock Period(ns) Waveform(ns) Attributes Sources +clk 20.000 {0.000 10.000} P {clk} +clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} +cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} +sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} ==================================================== @@ -46,13 +45,6 @@ Edges : {1 2 3} Edge Shifts(ns) : {0.000 5.161 10.323} Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} -Generated Clock : mlkem_clk_clk_pll -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Edges : {1 2 3} -Edge Shifts(ns) : {0.000 10.000 20.000} -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} - Generated Clock : sys_clk Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 Master Clock : clk diff --git a/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt b/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt index 441963e..fab96c3 100644 --- a/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt +++ b/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:35:00 2026 +| Date : Fri Jul 10 04:15:40 2026 | Host : fedora running 64-bit unknown -| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt +| Command : report_design_analysis -complexity -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_complexity.rpt | Design : soc_top | Device : xc7a200t | Design State : Routed -------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------- Report Design Analysis @@ -18,18 +18,17 @@ Table of Contents 1. Complexity Characteristics (Cells) ------------------------------------- -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| (top) | soc_top | 0.34 | 3.77 | 118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) | 1175 | 16 | 39 | 6020 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 | -| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.46 | 2.22 | 1002 | 1(0.3%) | 65(17.1%) | 39(10.3%) | 174(45.8%) | 13(3.4%) | 88(23.2%) | 0 | 0 | 0 | 0 | 0 | -| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.56 | 3.75 | 74954 | 362(0.9%) | 3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) | 1169 | 16 | 18 | 5286 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 0.63 | 3.76 | 15159 | 18(0.2%) | 1646(15.2%) | 357(3.3%) | 830(7.6%) | 974(9.0%) | 7026(64.7%) | 6 | 0 | 0 | 413 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.36 | 3.45 | 3680 | 136(6.5%) | 181(8.6%) | 405(19.3%) | 255(12.2%) | 342(16.3%) | 776(37.0%) | 0 | 0 | 1 | 4 | 0 | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+ +| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM | ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+ +| (top) | soc_top | 0.31 | 3.78 | 131904 | 802(1.0%) | 9228(11.4%) | 10135(12.5%) | 10316(12.7%) | 12781(15.7%) | 37981(46.7%) | 1175 | 0 | 41 | 6069 | 0 | +| u_axi_axil_adapter | axi_axil_adapter | 0.37 | 4.65 | 1624 | 0(0.0%) | 25(1.8%) | 36(2.6%) | 860(61.8%) | 202(14.5%) | 269(19.3%) | 0 | 0 | 0 | 62 | 0 | +| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 | +| u_cpu | core_top | 0.59 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 | +| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.41 | 3.78 | 87846 | 374(0.7%) | 6103(11.5%) | 7425(14.0%) | 6353(12.0%) | 8174(15.5%) | 24445(46.2%) | 1169 | 0 | 20 | 5269 | 0 | +| u_matmul_axi_slave | matmul_axi_slave | 0.60 | 3.76 | 15711 | 18(0.2%) | 1632(14.3%) | 345(3.0%) | 805(7.1%) | 1733(15.2%) | 6875(60.3%) | 6 | 0 | 0 | 417 | 0 | +| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.46 | 3.31 | 3435 | 136(7.4%) | 239(12.9%) | 432(23.4%) | 301(16.3%) | 234(12.6%) | 508(27.5%) | 0 | 0 | 1 | 4 | 0 | ++---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+--------------+--------------+--------------+--------------+------------+-----+------+------+------+ * Complexity Ranges ** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high *** -* -> Not computable as cell size is very small diff --git a/fpga/vivado_reports_nodsp/design_analysis_timing.rpt b/fpga/vivado_reports_nodsp/design_analysis_timing.rpt index 6e7bf34..09725ce 100644 --- a/fpga/vivado_reports_nodsp/design_analysis_timing.rpt +++ b/fpga/vivado_reports_nodsp/design_analysis_timing.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:29 2026 +| Date : Fri Jul 10 04:15:09 2026 | Host : fedora running 64-bit unknown -| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt +| Command : report_design_analysis -timing -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/design_analysis_timing.rpt | Design : soc_top | Device : xc7a200t | Design State : Routed ------------------------------------------------------------------------------------------------------------------------ +------------------------------------------------------------------------------------------------------------------------------------------------------------- Report Design Analysis @@ -18,35 +18,35 @@ Table of Contents 1. Setup Path Characteristics 1-1 --------------------------------- -+---------------------------+------------------------------------------------------+ -| Characteristics | Path #1 | -+---------------------------+------------------------------------------------------+ -| Requirement | 20.000 | -| Path Delay | 15.605 | -| Logic Delay | 5.343(35%) | -| Net Delay | 10.263(65%) | -| Clock Skew | -3.858 | -| Slack | 0.167 | -| Clock Relationship | Safely Timed | -| Logic Levels | 9 | -| Routes | 9 | -| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT | -| Start Point Clock | sys_clk | -| End Point Clock | sys_clk | -| DSP Block | None | -| BRAM | None | -| IO Crossings | 3 | -| Config Crossings | 0 | -| SLR Crossings | 0 | -| PBlocks | 0 | -| High Fanout | 130 | -| Dont Touch | 0 | -| Mark Debug | 0 | -| Start Point Pin Primitive | FDRE/C | -| End Point Pin Primitive | ext_ram_data[18] | -| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C | -| End Point Pin | ext_ram_data[18] | -+---------------------------+------------------------------------------------------+ ++---------------------------+----------------------------------------------------------------------------------------+ +| Characteristics | Path #1 | ++---------------------------+----------------------------------------------------------------------------------------+ +| Requirement | 20.000 | +| Path Delay | 15.529 | +| Logic Delay | 6.868(45%) | +| Net Delay | 8.661(55%) | +| Clock Skew | -3.955 | +| Slack | 0.146 | +| Clock Relationship | Safely Timed | +| Logic Levels | 14 | +| Routes | 12 | +| Logical Path | FDCE LUT4 LUT5 LUT6 CARRY4 CARRY4 CARRY4 CARRY4 LUT4 CARRY4 CARRY4 LUT6 LUT6 LUT6 OBUF | +| Start Point Clock | sys_clk | +| End Point Clock | sys_clk | +| DSP Block | None | +| BRAM | None | +| IO Crossings | 3 | +| Config Crossings | 0 | +| SLR Crossings | 0 | +| PBlocks | 0 | +| High Fanout | 80 | +| Dont Touch | 0 | +| Mark Debug | 0 | +| Start Point Pin Primitive | FDCE/C | +| End Point Pin Primitive | base_ram_be_n[3] | +| Start Point Pin | ax_req_q_len_reg[3]/C | +| End Point Pin | base_ram_be_n[3] | ++---------------------------+----------------------------------------------------------------------------------------+ * Bounding box calculated as % of dimensions for the target device (436, 500) diff --git a/fpga/vivado_reports_nodsp/drc.rpt b/fpga/vivado_reports_nodsp/drc.rpt index 213e823..3f0d407 100644 --- a/fpga/vivado_reports_nodsp/drc.rpt +++ b/fpga/vivado_reports_nodsp/drc.rpt @@ -1,14 +1,14 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:33:58 2026 +| Date : Fri Jul 10 04:14:40 2026 | Host : fedora running 64-bit unknown -| Command : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt +| Command : report_drc -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/drc.rpt | Design : soc_top | Device : xc7a200tfbg676-1 | Speed File : -1 | Design State : Fully Routed ------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------- Report DRC @@ -24,14 +24,11 @@ Table of Contents Design limits: Ruledeck: default Max violations: - Violations found: 90 + Violations found: 42 +-----------+----------+----------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+----------------------------+------------+ | CHECK-3 | Warning | Report rule limit reached | 2 | -| DPIP-1 | Warning | Input pipelining | 16 | -| DPOP-1 | Warning | PREG Output pipelining | 16 | -| DPOP-2 | Warning | MREG Output pipelining | 16 | | REQP-1839 | Warning | RAMB36 async control check | 20 | | REQP-1840 | Warning | RAMB18 async control check | 20 | +-----------+----------+----------------------------+------------+ @@ -48,246 +45,6 @@ Report rule limit reached REQP-1840 rule limit reached: 20 violations have been found. Related violations: -DPIP-1#1 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#2 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#3 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#4 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#5 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#6 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#7 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#8 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#9 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#10 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#11 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#12 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#13 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#14 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#15 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#16 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPOP-1#1 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#2 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#3 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#4 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#5 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#6 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#7 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#8 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#9 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#10 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#11 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#12 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#13 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#14 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#15 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#16 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-2#1 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#2 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#3 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#4 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#5 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#6 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#7 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#8 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#9 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#10 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#11 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#12 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#13 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#14 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#15 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#16 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - REQP-1839#1 Warning RAMB36 async control check The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. diff --git a/fpga/vivado_reports_nodsp/high_fanout.rpt b/fpga/vivado_reports_nodsp/high_fanout.rpt index 5af6bfc..6a0e9b4 100644 --- a/fpga/vivado_reports_nodsp/high_fanout.rpt +++ b/fpga/vivado_reports_nodsp/high_fanout.rpt @@ -1,12 +1,12 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +| Date : Fri Jul 10 04:14:55 2026 | Host : fedora running 64-bit unknown -| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt +| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/high_fanout.rpt | Design : soc_top | Device : xc7a200t --------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- High Fan-out Nets Information @@ -16,9 +16,11 @@ High Fan-out Nets Information +---------------------------------------------------------------------------------------+--------+-------------+ | Net Name | Fanout | Driver Type | +---------------------------------------------------------------------------------------+--------+-------------+ -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24598 | LUT5 | -| pll_clk.u_clk_pll/inst/sys_clk | 10004 | BUFG | -| pll_clk.u_rst_sys/p_0_in | 4130 | LUT1 | +| pll_clk.u_clk_pll/inst/sys_clk | 35652 | BUFG | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24670 | LUT5 | +| pll_clk.u_rst_sys/p_0_in | 5108 | LUT1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[0] | 3758 | FDCE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[1]_0 | 2151 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 | @@ -32,25 +34,22 @@ High Fan-out Nets Information | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active | 1130 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE | -| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1069 | LUT1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 936 | LUT5 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 938 | LUT5 | +| u_matmul_axi_slave/w_addr[2] | 873 | FDRE | | u_cpu/reset | 799 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 | -| u_matmul_axi_slave/w_addr[2] | 724 | FDRE | | u_cpu/u_mul/E[0] | 716 | LUT1 | -| u_matmul_axi_slave/w_addr[3] | 628 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 528 | LUT6 | -| u_matmul_axi_slave/current_r_offset[2] | 522 | LUT5 | -| u_matmul_axi_slave/current_r_offset[3] | 520 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 516 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 516 | FDCE | +| u_matmul_axi_slave/w_addr[4] | 655 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 525 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 518 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 515 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0] | 512 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2] | 390 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[3]_0[0] | 512 | LUT5 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE | | u_cpu/wb_stage/w_index[0] | 358 | LUT6 | @@ -63,85 +62,49 @@ High Fan-out Nets Information | u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE | | u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE | | u_cpu/wb_stage/we_0 | 324 | LUT4 | -| u_matmul_axi_slave/w_addr[4] | 317 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 284 | FDCE | -| u_matmul_axi_slave/cur_bank_reg_n_0 | 277 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 293 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[4] | 288 | CARRY4 | +| u_matmul_axi_slave/cur_bank_reg_n_0 | 274 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4] | 260 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 | -| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 259 | FDRE | -| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 257 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0] | 256 | LUT5 | +| u_matmul_axi_slave/sel0[1] | 259 | FDRE | +| u_matmul_axi_slave/b1_b_reg[0][31]_i_8_n_7 | 258 | CARRY4 | +| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 258 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 256 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_phase_reg[1]_0[0] | 256 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 | +| u_matmul_axi_slave/m_in_a[3][31]_i_1_n_0 | 256 | LUT6 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 | -| u_matmul_axi_slave/w_addr[5] | 246 | FDRE | -| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 | +| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT2 | +| u_matmul_axi_slave/b0_a[6][25]_i_2_n_0 | 242 | LUT2 | +| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 239 | LUT3 | +| u_matmul_axi_slave/m_in_a[3][30]_i_6_n_0 | 238 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 237 | FDCE | | u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 | | u_cpu/mem_stage/E[0] | 234 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 234 | FDCE | -| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 229 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0 | 228 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 227 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 231 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 | @@ -150,72 +113,109 @@ High Fan-out Nets Information | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 219 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[5] | 219 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 216 | RAMB18E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 216 | RAMB18E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 215 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[2] | 215 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 214 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 214 | RAMB18E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 214 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 212 | RAMB36E1 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 212 | RAMB36E1 | | u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 | | u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 | | u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3] | 197 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 207 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 206 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE | -| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 196 | LUT6 | | u_cpu/wb_stage/Q[33] | 194 | FDRE | | u_cpu/wb_stage/Q[34] | 194 | FDRE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0 | 191 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 187 | FDCE | -| u_matmul_axi_slave/current_r_offset[4] | 187 | LUT5 | -| u_matmul_axi_slave/s_axi_wready_reg_1 | 181 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg_n_0_[3] | 187 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[2] | 186 | FDCE | | u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 180 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 177 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 176 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 180 | FDCE | +| u_matmul_axi_slave/b0_b_reg[1][30]_i_4_n_7 | 178 | CARRY4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 176 | FDCE | | u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 | | u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt114_out | 175 | LUT2 | | u_cpu/wb_stage/Q[37] | 173 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 173 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7 | 171 | CARRY4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[5]_rep__0_n_0 | 172 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[131][11]_i_4_n_0 | 171 | LUT3 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 169 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 166 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/hek_r2[3] | 169 | CARRY4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[74][11]_i_4_n_0 | 168 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/w_addr_reg[6]_0[0] | 168 | CARRY4 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_0 | 167 | LUT2 | +| u_axi_axil_adapter/axi_axil_adapter_wr_inst/m_axil_awaddr_reg_reg[6]_1 | 167 | LUT2 | +| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 167 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[129][11]_i_3_n_0 | 166 | LUT3 | +| u_matmul_axi_slave/FSM_onehot_w_state_reg[2]_rep__0_n_0 | 165 | FDRE | | u_cpu/wb_stage/Q[32] | 164 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 164 | FDCE | | u_cpu/wb_stage/Q[35] | 163 | FDRE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg[0]_rep__0_n_0 | 163 | FDCE | | u_cpu/wb_stage/Q[36] | 162 | FDRE | -| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__12_n_0 | 158 | FDCE | +| u_matmul_axi_slave/w_addr_reg[3]_rep__2_0 | 158 | LUT6 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[181][5]_i_3_n_0 | 157 | LUT2 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[6] | 156 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 153 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 153 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[7] | 155 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 154 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[4] | 154 | FDCE | +| u_matmul_axi_slave/w_addr[3] | 153 | FDRE | | u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE | | u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 | | u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 | | u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 | -| u_matmul_axi_slave/s_axi_wready_reg_0 | 148 | LUT5 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 148 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[202][11]_i_3_n_0 | 148 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 147 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__1_n_0 | 146 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep_n_0 | 146 | FDCE | +| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 146 | LUT3 | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0 | 144 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 143 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 143 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 143 | LUT3 | -| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0 | 143 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0 | 142 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__10_n_0 | 145 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[2] | 144 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[247]_i_3_n_0 | 144 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/hek_r[255]_i_3_n_0 | 144 | LUT4 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__17_n_0 | 143 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[106][11]_i_3_n_0 | 143 | LUT3 | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 142 | FDCE | +| u_matmul_axi_slave/FSM_onehot_w_state_reg_n_0_[0] | 142 | FDSE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[5] | 141 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 141 | FDCE | | u_cpu/dcache/write_buffer_state | 140 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0 | 140 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 140 | FDCE | | u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE | -| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0 | 139 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0 | 139 | FDCE | +| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[7] | 140 | FDCE | +---------------------------------------------------------------------------------------+--------+-------------+ diff --git a/fpga/vivado_reports_nodsp/methodology.rpt b/fpga/vivado_reports_nodsp/methodology.rpt index 82b3488..a15278b 100644 --- a/fpga/vivado_reports_nodsp/methodology.rpt +++ b/fpga/vivado_reports_nodsp/methodology.rpt @@ -1,14 +1,14 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 +| Date : Fri Jul 10 04:14:46 2026 | Host : fedora running 64-bit unknown -| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt +| Command : report_methodology -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/methodology.rpt | Design : soc_top | Device : xc7a200tfbg676-1 | Speed File : -1 | Design State : Fully Routed ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- Report Methodology @@ -23,13 +23,13 @@ Table of Contents Floorplan: impl_1 Design limits: Max violations: - Violations found: 99 + Violations found: 107 +-----------+----------+-------------------------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+-------------------------------------------------------------------+------------+ | LUTAR-1 | Warning | LUT drives async reset alert | 1 | | SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 | -| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 | +| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 9 | | SYNTH-16 | Warning | Address collision | 8 | | TIMING-10 | Warning | Missing property on synchronizer | 1 | | TIMING-18 | Warning | Missing input or output delay | 76 | @@ -42,7 +42,7 @@ Table of Contents ----------------- LUTAR-1#1 Warning LUT drives async reset alert -LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. +LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24656 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: SYNTH-5#1 Warning @@ -87,7 +87,47 @@ Related violations: SYNTH-6#1 Warning Timing of a block RAM might be sub-optimal -The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#2 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#3 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#4 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#5 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#6 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#7 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#8 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0, implemented as a block RAM, might be sub-optimal as no output register was merged into the block +Related violations: + +SYNTH-6#9 Warning +Timing of a block RAM might be sub-optimal +The timing for the instance u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block Related violations: SYNTH-16#1 Warning diff --git a/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt b/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt index 2fdd8cd..7142711 100644 --- a/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt +++ b/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt @@ -1,5215 +1,8691 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +| Date : Fri Jul 10 04:14:54 2026 | Host : fedora running 64-bit unknown -| Command : report_timing -from [get_clocks mlkem_clk_clk_pll] -to [get_clocks mlkem_clk_clk_pll] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/mlkem_clk_timing.rpt +| Command : report_timing -from [get_clocks sys_clk] -to [get_clocks sys_clk] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/mlkem_clk_timing.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.208 + ------------------------------------------------------------------- + slack 0.146 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] + L25 r base_ram_data[1] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.074 + ------------------------------------------------------------------- + slack 0.280 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.073 + ------------------------------------------------------------------- + slack 0.281 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[30] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T + M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T + M24 OBUFT (TriStatE_obuft_T_O) + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] + M24 r base_ram_data[30] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.067 + ------------------------------------------------------------------- + slack 0.287 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns + Discrete Jitter (DJ): 0.122ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 diff --git a/fpga/vivado_reports_nodsp/power.rpt b/fpga/vivado_reports_nodsp/power.rpt index 851e855..db1e590 100644 --- a/fpga/vivado_reports_nodsp/power.rpt +++ b/fpga/vivado_reports_nodsp/power.rpt @@ -1,16 +1,16 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:25 2026 +| Date : Fri Jul 10 04:15:05 2026 | Host : fedora running 64-bit unknown -| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt +| Command : report_power -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/power.rpt | Design : soc_top | Device : xc7a200tfbg676-1 | Design State : routed | Grade : commercial | Process : typical | Characterization : Production ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- Power Report @@ -30,14 +30,14 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 0.549 | +| Total On-Chip Power (W) | 0.686 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 0.409 | +| Dynamic (W) | 0.545 | | Device Static (W) | 0.141 | | Effective TJA (C/W) | 1.9 | -| Max Ambient (C) | 84.0 | -| Junction Temperature (C) | 26.0 | +| Max Ambient (C) | 83.7 | +| Junction Temperature (C) | 26.3 | | Confidence Level | Low | | Setting File | --- | | Simulation Activity File | --- | @@ -52,22 +52,21 @@ Table of Contents +--------------------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +--------------------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.042 | 7 | --- | --- | -| Slice Logic | 0.069 | 120086 | --- | --- | -| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 | -| CARRY4 | 0.002 | 2859 | 33450 | 8.55 | -| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 | -| Register | <0.001 | 39931 | 267600 | 14.92 | +| Clocks | 0.056 | 6 | --- | --- | +| Slice Logic | 0.109 | 133224 | --- | --- | +| LUT as Logic | 0.102 | 75460 | 133800 | 56.40 | +| CARRY4 | 0.003 | 3546 | 33450 | 10.60 | +| LUT as Distributed RAM | 0.002 | 628 | 46200 | 1.36 | +| Register | 0.001 | 39690 | 267600 | 14.83 | | LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 | -| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 | -| Others | 0.000 | 318 | --- | --- | -| Signals | 0.115 | 85084 | --- | --- | -| Block RAM | 0.019 | 23.5 | 365 | 6.44 | -| PLL | 0.132 | 1 | 10 | 10.00 | -| DSPs | 0.009 | 16 | 740 | 2.16 | -| I/O | 0.023 | 202 | 400 | 50.50 | +| F7/F8 Muxes | <0.001 | 6085 | 133800 | 4.55 | +| Others | 0.000 | 289 | --- | --- | +| Signals | 0.194 | 93202 | --- | --- | +| Block RAM | 0.019 | 25.5 | 365 | 6.99 | +| PLL | 0.137 | 1 | 10 | 10.00 | +| I/O | 0.029 | 202 | 400 | 50.50 | | Static Power | 0.141 | | | | -| Total | 0.549 | | | | +| Total | 0.686 | | | | +--------------------------+-----------+----------+-----------+-----------------+ @@ -77,9 +76,9 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | +-----------+-------------+-----------+-------------+------------+ -| Vccint | 1.000 | 0.294 | 0.262 | 0.032 | -| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 | -| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 | +| Vccint | 1.000 | 0.423 | 0.391 | 0.032 | +| Vccaux | 1.800 | 0.101 | 0.070 | 0.031 | +| Vcco33 | 3.300 | 0.013 | 0.008 | 0.005 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | | Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | @@ -130,15 +129,14 @@ Table of Contents 2.2 Clock Constraints --------------------- -+-------------------+------------------------------------------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------------------+------------------------------------------+-----------------+ -| clk | clk | 20.0 | -| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | -| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 | -| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 | -| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | -+-------------------+------------------------------------------+-----------------+ ++------------------+-----------------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++------------------+-----------------------------------------+-----------------+ +| clk | clk | 20.0 | +| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | +| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 | +| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | ++------------------+-----------------------------------------+-----------------+ 3. Detailed Reports @@ -150,29 +148,32 @@ Table of Contents +----------------------------+-----------+ | Name | Power (W) | +----------------------------+-----------+ -| soc_top | 0.409 | -| pll_clk.u_clk_pll | 0.133 | -| inst | 0.133 | -| u_Axi_CDC | 0.002 | -| u_axi_uart_controller | 0.001 | -| uart0 | 0.001 | -| regs | 0.001 | -| u_cdma_matmul_bridge | 0.001 | -| u_cpu | 0.018 | +| soc_top | 0.545 | +| pll_clk.u_clk_pll | 0.138 | +| inst | 0.138 | +| u_Axi_CDC | 0.003 | +| u_axi_uart_controller | 0.002 | +| u_cpu | 0.025 | | addr_trans | 0.002 | | tlb_entry | 0.002 | -| btb | 0.002 | -| dcache | 0.004 | +| btb | 0.003 | +| dcache | 0.006 | | icache | 0.005 | -| u_csr | 0.002 | -| u_fft_mlkem_axi_slave | 0.148 | -| u_fft_controller | 0.032 | -| u_FFT | 0.029 | -| u_mlkem_axi_cdc | 0.002 | -| u_mlkem_axi_slave | 0.115 | -| u_mlkem | 0.113 | -| u_matmul_axi_slave | 0.065 | -| u_snix_axil_cdma_mux_8ch | 0.009 | +| u_csr | 0.001 | +| u_mul | 0.004 | +| u_fft_mlkem_axi_slave | 0.251 | +| u_fft_controller | 0.030 | +| u_FFT | 0.027 | +| u_out0 | 0.001 | +| u_out1 | 0.001 | +| u_mlkem_axi_slave | 0.221 | +| u_mlkem | 0.218 | +| u_matmul_axi_slave | 0.081 | +| mult_inst[0].u_mult | 0.003 | +| mult_inst[1].u_mult | 0.002 | +| mult_inst[2].u_mult | 0.002 | +| mult_inst[3].u_mult | 0.002 | +| u_snix_axil_cdma_mux_8ch | 0.008 | | u_core_engine | 0.004 | | axis_fifo_u0 | 0.003 | +----------------------------+-----------+ diff --git a/fpga/vivado_reports_nodsp/route_status.rpt b/fpga/vivado_reports_nodsp/route_status.rpt index a98697c..8907005 100644 --- a/fpga/vivado_reports_nodsp/route_status.rpt +++ b/fpga/vivado_reports_nodsp/route_status.rpt @@ -1,12 +1,12 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 128919 : - # of nets not needing routing.......... : 43824 : - # of internally routed nets........ : 43359 : - # of nets with no loads............ : 465 : - # of routable nets..................... : 85095 : - # of fully routed nets............. : 85095 : + # of logical nets.......................... : 144034 : + # of nets not needing routing.......... : 50823 : + # of internally routed nets........ : 50442 : + # of nets with no loads............ : 381 : + # of routable nets..................... : 93211 : + # of fully routed nets............. : 93211 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/fpga/vivado_reports_nodsp/timing_hold_paths.rpt b/fpga/vivado_reports_nodsp/timing_hold_paths.rpt index fefd31f..09403fa 100644 --- a/fpga/vivado_reports_nodsp/timing_hold_paths.rpt +++ b/fpga/vivado_reports_nodsp/timing_hold_paths.rpt @@ -1,197 +1,175 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 +| Date : Fri Jul 10 04:14:54 2026 | Host : fedora running 64-bit unknown -| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_hold_paths.rpt +| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_hold_paths.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D + 1.174 -0.674 + SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C + SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_matmul_axi_slave/m_in_b_reg[1][23]/Q + net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] + SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 + required time 0.271 + arrival time -0.231 ------------------------------------------------------------------- - slack 0.032 + slack 0.040 -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D + 1.174 -0.674 + SLICE_X47Y102 FDRE 0.000 -0.674 r u_matmul_axi_slave/m_in_b_reg[1][23]/C + SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 f u_matmul_axi_slave/m_in_b_reg[1][23]/Q + net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] + SLICE_X59Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] + 1.566 -0.381 + clock pessimism 0.040 -0.341 + SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 + required time 0.271 + arrival time -0.231 ------------------------------------------------------------------- - slack 0.032 + slack 0.040 Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.413ns + Source Clock Delay (SCD): -0.639ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + 1.209 -0.639 + SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q + net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] + SLICE_X85Y77 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2 + SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O + net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 + SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] + 1.534 -0.413 + clock pessimism 0.037 -0.376 + SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 + required time 0.269 + arrival time -0.228 ------------------------------------------------------------------- slack 0.042 Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.413ns + Source Clock Delay (SCD): -0.639ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D + 1.209 -0.639 + SLICE_X82Y77 FDCE 0.000 -0.639 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q + net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] + SLICE_X85Y77 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/I2 + SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O + net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 + SLICE_X85Y77 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] + 1.534 -0.413 + clock pessimism 0.037 -0.376 + SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 + required time 0.269 + arrival time -0.228 ------------------------------------------------------------------- slack 0.042 @@ -203,35 +181,35 @@ Slack (MET) : 0.049ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + 1.236 -0.612 + SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C + SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q + net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 + SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + 1.564 -0.383 + clock pessimism -0.216 -0.599 + SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 + required time 0.452 + arrival time -0.403 ------------------------------------------------------------------- slack 0.049 @@ -243,11 +221,2377 @@ Slack (MET) : 0.049ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) + Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.236 -0.612 + SLICE_X97Y50 FDRE 0.000 -0.612 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C + SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q + net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 + SLICE_X96Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.216 -0.599 + SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + ------------------------------------------------------------------- + required time 0.452 + arrival time -0.403 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) + Logic Levels: 0 + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.487ns + Source Clock Delay (SCD): -0.710ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.139 -0.710 + SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q + net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] + SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.460 -0.487 + clock pessimism 0.040 -0.447 + SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.328 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) + Logic Levels: 0 + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.487ns + Source Clock Delay (SCD): -0.710ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.139 -0.710 + SLICE_X85Y170 FDCE 0.000 -0.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q + net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] + SLICE_X81Y171 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.460 -0.487 + clock pessimism 0.040 -0.447 + SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] + ------------------------------------------------------------------- + required time 0.377 + arrival time -0.328 + ------------------------------------------------------------------- + slack 0.049 + +Slack (MET) : 0.051ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.216 -0.602 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.455 + arrival time -0.404 + ------------------------------------------------------------------- + slack 0.051 + +Slack (MET) : 0.051ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X67Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.216 -0.602 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.455 + arrival time -0.404 + ------------------------------------------------------------------- + slack 0.051 + +Slack (MET) : 0.056ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q + net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] + SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O + net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.056 + +Slack (MET) : 0.056ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X112Y55 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C + SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q + net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] + SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O + net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] + SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.094 + ------------------------------------------------------------------- + slack 0.056 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_confreg/confreg_int_set_reg[11]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): -0.494ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.355 -0.494 + SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C + SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 r u_confreg/confreg_int_set_reg[11]/Q + net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] + SLICE_X8Y51 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2 + SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O + net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 + SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.612 -0.335 + clock pessimism 0.037 -0.298 + SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] + ------------------------------------------------------------------- + required time 0.178 + arrival time -0.117 + ------------------------------------------------------------------- + slack 0.061 + +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_confreg/confreg_int_set_reg[11]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): -0.494ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.355 -0.494 + SLICE_X8Y49 FDRE 0.000 -0.494 r u_confreg/confreg_int_set_reg[11]/C + SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 f u_confreg/confreg_int_set_reg[11]/Q + net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] + SLICE_X8Y51 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/I2 + SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 f u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O + net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 + SLICE_X8Y51 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.612 -0.335 + clock pessimism 0.037 -0.298 + SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] + ------------------------------------------------------------------- + required time 0.178 + arrival time -0.117 + ------------------------------------------------------------------- + slack 0.061 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q + net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] + SLICE_X114Y49 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O + net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.076 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.246 -0.602 + SLICE_X112Y53 FDRE 0.000 -0.602 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q + net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] + SLICE_X114Y49 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/I2 + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O + net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] + SLICE_X114Y49 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.653 -0.294 + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] + ------------------------------------------------------------------- + required time 0.150 + arrival time -0.076 + ------------------------------------------------------------------- + slack 0.074 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) + Logic Levels: 0 + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.120 + ------------------------------------------------------------------- + slack 0.076 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) + Logic Levels: 0 + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.120 + ------------------------------------------------------------------- + slack 0.076 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) + Logic Levels: 0 + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.120 + ------------------------------------------------------------------- + slack 0.076 + +Slack (MET) : 0.076ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) + Logic Levels: 0 + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.302 -0.546 + SLICE_X4Y67 FDCE 0.000 -0.546 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.634 -0.313 + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.120 + ------------------------------------------------------------------- + slack 0.076 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.600 -0.347 + clock pessimism 0.037 -0.310 + SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] + ------------------------------------------------------------------- + required time 0.240 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X39Y52 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.600 -0.347 + clock pessimism 0.037 -0.310 + SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] + ------------------------------------------------------------------- + required time 0.240 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C + SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[5]/Q + net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) + 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.280 + arrival time -0.196 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y47 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[5]/C + SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[5]/Q + net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 + SLICE_X44Y51 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) + 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.280 + arrival time -0.196 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/wstrb_reg[2]/C + (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.496ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.353 -0.496 + SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C + SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 r u_cpu/axi_bridge/wstrb_reg[2]/Q + net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.221 -0.483 + SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) + 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC + ------------------------------------------------------------------- + required time 0.393 + arrival time -0.309 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/wstrb_reg[2]/C + (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.496ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.353 -0.496 + SLICE_X15Y41 FDSE 0.000 -0.496 r u_cpu/axi_bridge/wstrb_reg[2]/C + SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 f u_cpu/axi_bridge/wstrb_reg[2]/Q + net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 + SLICE_X14Y41 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.221 -0.483 + SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) + 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC + ------------------------------------------------------------------- + required time 0.393 + arrival time -0.309 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.504ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.345 -0.504 + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[27]/Q + net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] + SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] + ------------------------------------------------------------------- + required time 0.243 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.504ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.345 -0.504 + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[27]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[27]/Q + net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] + SLICE_X37Y50 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] + ------------------------------------------------------------------- + required time 0.243 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.086 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.608 -0.339 + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.221 + arrival time -0.135 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.608 -0.339 + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + ------------------------------------------------------------------- + required time 0.221 + arrival time -0.135 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.608 -0.339 + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.221 + arrival time -0.135 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) + Logic Levels: 0 + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.279 -0.569 + SLICE_X15Y61 FDCE 0.000 -0.569 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 f axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.608 -0.339 + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + ------------------------------------------------------------------- + required time 0.221 + arrival time -0.135 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 f u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 f u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.383 -0.466 + SLICE_X1Y45 FDRE 0.000 -0.466 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.717 -0.230 + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -255,199 +2599,1105 @@ Slack (MET) : 0.049ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 + required time 0.196 + arrival time -0.109 ------------------------------------------------------------------- - slack 0.049 + slack 0.087 -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 + required time 0.196 + arrival time -0.109 ------------------------------------------------------------------- - slack 0.052 + slack 0.087 -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 + required time 0.196 + arrival time -0.109 ------------------------------------------------------------------- - slack 0.052 + slack 0.087 -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_confreg/int_out_or_q1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/int_out_or_q2_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) + Logic Levels: 0 + Clock Path Skew: 0.316ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D + 1.309 -0.539 + SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C + SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/int_out_or_q1_reg/Q + net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] + 1.687 -0.260 + clock pessimism 0.037 -0.223 + SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 + required time 0.148 + arrival time -0.059 ------------------------------------------------------------------- - slack 0.054 + slack 0.089 -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_confreg/int_out_or_q1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/int_out_or_q2_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.316ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D + 1.309 -0.539 + SLICE_X4Y50 FDRE 0.000 -0.539 r u_confreg/int_out_or_q1_reg/C + SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_confreg/int_out_or_q1_reg/Q + net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 + SLICE_X9Y47 FDRE f u_confreg/int_out_or_q2_reg/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] + 1.687 -0.260 + clock pessimism 0.037 -0.223 + SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 + required time 0.148 + arrival time -0.059 ------------------------------------------------------------------- - slack 0.054 + slack 0.089 -Slack (MET) : 0.057ns (arrival time - required time) +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C + SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q + net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.213 -0.599 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.453 + arrival time -0.363 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X69Y50 FDRE 0.000 -0.615 r u_cpu/u_csr/csr_tlbelo1_reg[22]/C + SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_cpu/u_csr/csr_tlbelo1_reg[22]/Q + net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 + SLICE_X66Y50 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.561 -0.386 + clock pessimism -0.213 -0.599 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.453 + arrival time -0.363 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[11]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[11]/Q + net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.281 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[11]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[11]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[11]/Q + net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 + SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 + ------------------------------------------------------------------- + required time 0.281 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[9]/Q + net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.177 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[9]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 f u_cpu/axi_bridge/araddr_reg[9]/Q + net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 + SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.177 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] + RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X103Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] + RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.094ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I @@ -455,12 +3705,12 @@ Slack (MET) : 0.057ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) + Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Pessimism Removal (CPR): 0.222ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -470,24 +3720,24 @@ Slack (MET) : 0.057ns (arrival time - required time) 1.353 -0.496 SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I + net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC + 1.686 -0.261 + clock pessimism -0.222 -0.483 + SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 + required time 0.339 + arrival time -0.245 ------------------------------------------------------------------- - slack 0.057 + slack 0.094 -Slack (MET) : 0.057ns (arrival time - required time) +Slack (MET) : 0.094ns (arrival time - required time) Source: u_cpu/axi_bridge/awaddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I @@ -495,12 +3745,12 @@ Slack (MET) : 0.057ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) + Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Pessimism Removal (CPR): 0.222ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -510,2012 +3760,116 @@ Slack (MET) : 0.057ns (arrival time - required time) 1.353 -0.496 SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I + net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X16Y49 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC + 1.686 -0.261 + clock pessimism -0.222 -0.483 + SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 + required time 0.339 + arrival time -0.245 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 + required time 0.214 + arrival time -0.118 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 + required time 0.214 + arrival time -0.118 ------------------------------------------------------------------- slack 0.095 -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2523,39 +3877,39 @@ Slack (MET) : 0.099ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 + required time 0.214 + arrival time -0.118 ------------------------------------------------------------------- - slack 0.099 + slack 0.095 -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2563,6195 +3917,843 @@ Slack (MET) : 0.099ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 + required time 0.214 + arrival time -0.118 ------------------------------------------------------------------- - slack 0.099 + slack 0.095 -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 + required time 0.214 + arrival time -0.118 ------------------------------------------------------------------- - slack 0.106 + slack 0.095 -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) Logic Levels: 0 Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 + required time 0.214 + arrival time -0.118 ------------------------------------------------------------------- - slack 0.106 + slack 0.095 -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 f u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[1]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 f u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.641 -0.306 + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.097ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) + Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D + 1.230 -0.619 + SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q + net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] + SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] + 1.559 -0.388 + clock pessimism 0.045 -0.343 + SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 + required time 0.273 + arrival time -0.176 ------------------------------------------------------------------- - slack 0.107 + slack 0.097 -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.097ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) + Logic Levels: 0 + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D + 1.230 -0.619 + SLICE_X157Y150 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q + net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] + SLICE_X159Y138 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] + 1.559 -0.388 + clock pessimism 0.045 -0.343 + SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 + required time 0.273 + arrival time -0.176 ------------------------------------------------------------------- - slack 0.108 + slack 0.097 -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 + required time 0.343 + arrival time -0.245 ------------------------------------------------------------------- - slack 0.110 + slack 0.098 -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 + SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 + required time 0.343 + arrival time -0.245 ------------------------------------------------------------------- - slack 0.110 + slack 0.098 -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.099ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 + required time 0.344 + arrival time -0.245 ------------------------------------------------------------------- - slack 0.110 + slack 0.099 -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll +Slack (MET) : 0.099ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns Source Clock Delay (SCD): -0.701ns Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + SLICE_X83Y151 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/I3 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 + SLICE_X87Y152 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + 1.472 -0.475 + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 + required time 0.344 + arrival time -0.245 ------------------------------------------------------------------- - slack 0.117 + slack 0.099 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] + ------------------------------------------------------------------- + required time 0.239 + arrival time -0.140 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.343 -0.506 + SLICE_X40Y49 FDRE 0.000 -0.506 r u_cpu/u_csr/csr_tlbidx_reg[26]/C + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 f u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X37Y51 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.346 + clock pessimism 0.037 -0.309 + SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] + ------------------------------------------------------------------- + required time 0.239 + arrival time -0.140 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -8759,39 +4761,39 @@ Slack (MET) : 0.121ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 + required time 0.305 + arrival time -0.205 ------------------------------------------------------------------- - slack 0.121 + slack 0.100 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -8799,1853 +4801,677 @@ Slack (MET) : 0.121ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 + required time 0.305 + arrival time -0.205 ------------------------------------------------------------------- - slack 0.121 + slack 0.100 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 f u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.332 -0.517 + SLICE_X37Y26 FDRE 0.000 -0.517 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 f u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.660 -0.287 + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.101ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.675ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D + 1.173 -0.675 + SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C + SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 r u_matmul_axi_slave/m_in_a_reg[1][28]/Q + net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] + SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 + required time 0.280 + arrival time -0.179 ------------------------------------------------------------------- - slack 0.121 + slack 0.101 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D +Slack (MET) : 0.101ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.675ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + 1.173 -0.675 + SLICE_X44Y105 FDRE 0.000 -0.675 r u_matmul_axi_slave/m_in_a_reg[1][28]/C + SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 f u_matmul_axi_slave/m_in_a_reg[1][28]/Q + net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] + SLICE_X56Y98 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] + 1.568 -0.379 + clock pessimism 0.040 -0.339 + SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 + required time 0.280 + arrival time -0.179 ------------------------------------------------------------------- - slack 0.121 + slack 0.101 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) + Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.537ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10653,39 +5479,39 @@ Slack (MET) : 0.124ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I + 1.312 -0.537 + SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C + SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_cpu/u_csr/csr_tlbelo0_reg[4]/Q + net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D + SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC + 1.643 -0.304 + clock pessimism -0.196 -0.500 + SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 + required time 0.354 + arrival time -0.250 ------------------------------------------------------------------- - slack 0.124 + slack 0.103 -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) + Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.537ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -10693,987 +5519,39 @@ Slack (MET) : 0.124ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I + 1.312 -0.537 + SLICE_X50Y43 FDRE 0.000 -0.537 r u_cpu/u_csr/csr_tlbelo0_reg[4]/C + SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 f u_cpu/u_csr/csr_tlbelo0_reg[4]/Q + net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D + SLICE_X48Y43 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC + 1.643 -0.304 + clock pessimism -0.196 -0.500 + SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 + required time 0.354 + arrival time -0.250 ------------------------------------------------------------------- - slack 0.124 + slack 0.103 -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) + Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 f u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 f u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -11681,39 +5559,39 @@ Slack (MET) : 0.135ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_cpu/axi_bridge/araddr_reg[10]/Q + net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 + required time 0.197 + arrival time -0.093 ------------------------------------------------------------------- - slack 0.135 + slack 0.104 -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) + Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -11721,676 +5599,602 @@ Slack (MET) : 0.135ns (arrival time - required time) (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I + 1.313 -0.536 + SLICE_X47Y49 FDRE 0.000 -0.536 r u_cpu/axi_bridge/araddr_reg[10]/C + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 f u_cpu/axi_bridge/araddr_reg[10]/Q + net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X44Y52 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB + 1.569 -0.378 + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 + required time 0.197 + arrival time -0.093 ------------------------------------------------------------------- - slack 0.135 + slack 0.104 -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q + net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] ------------------------------------------------------------------- - required time 0.305 + required time 0.272 + arrival time -0.168 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q + net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] + SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] + ------------------------------------------------------------------- + required time 0.272 + arrival time -0.168 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] + RAMB18_X6Y27 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.233 -0.615 + SLICE_X102Y68 FDRE 0.000 -0.615 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 f u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] + RAMB18_X6Y26 RAMB18E1 f u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.601 -0.347 + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q + net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] + ------------------------------------------------------------------- + required time 0.276 arrival time -0.170 ------------------------------------------------------------------- - slack 0.135 + slack 0.106 -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q + net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] + SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] ------------------------------------------------------------------- - required time 0.305 + required time 0.276 arrival time -0.170 ------------------------------------------------------------------- - slack 0.135 + slack 0.106 -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/buf_addr_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I + 1.354 -0.495 + SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q + net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] + SLICE_X16Y51 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1 + SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/O + net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] + SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA + 1.611 -0.336 + clock pessimism 0.037 -0.299 + SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 + required time 0.178 + arrival time -0.070 ------------------------------------------------------------------- - slack 0.136 + slack 0.108 -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/buf_addr_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I + 1.354 -0.495 + SLICE_X13Y45 FDRE 0.000 -0.495 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 f u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q + net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] + SLICE_X16Y51 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/I1 + SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 f u_Axi_CDC/arFifo/buf_addr[2]_i_1/O + net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] + SLICE_X16Y51 FDRE f u_confreg/buf_addr_reg[2]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA + 1.611 -0.336 + clock pessimism 0.037 -0.299 + SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 + required time 0.178 + arrival time -0.070 ------------------------------------------------------------------- - slack 0.136 + slack 0.108 -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_confreg/digital_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I + SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C + SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 r u_confreg/digital_data_reg[1]/Q + net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] + SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC + 1.641 -0.306 + clock pessimism 0.037 -0.269 + SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 + required time 0.222 + arrival time -0.112 ------------------------------------------------------------------- - slack 0.138 + slack 0.111 -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_confreg/digital_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 f u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I + SLICE_X0Y49 FDRE 0.000 -0.465 r u_confreg/digital_data_reg[1]/C + SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 f u_confreg/digital_data_reg[1]/Q + net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] + SLICE_X0Y54 FDRE f u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC + 1.641 -0.306 + clock pessimism 0.037 -0.269 + SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 + required time 0.222 + arrival time -0.112 ------------------------------------------------------------------- - slack 0.138 + slack 0.111 -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.192ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.527ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D + 1.322 -0.527 + SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q + net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] + SLICE_X118Y50 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2 + SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O + net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] + SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] + 1.576 -0.371 + clock pessimism 0.037 -0.334 + SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 + required time 0.227 + arrival time -0.117 ------------------------------------------------------------------- - slack 0.139 + slack 0.111 -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.192ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.527ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE f u_cpu/icache/lfsr/r_lfsr_reg[7]/D + 1.322 -0.527 + SLICE_X116Y49 FDRE 0.000 -0.527 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q + net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] + SLICE_X118Y50 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/I2 + SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O + net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] + SLICE_X118Y50 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] + 1.576 -0.371 + clock pessimism 0.037 -0.334 + SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 + required time 0.227 + arrival time -0.117 ------------------------------------------------------------------- - slack 0.139 + slack 0.111 -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) + Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE f u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.345ns Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -12398,38 +6202,38 @@ Slack (MET) : 0.143ns (arrival time - required time) clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[24]/Q + net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] + SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] + 1.602 -0.345 + clock pessimism 0.037 -0.308 + SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 + required time 0.238 + arrival time -0.127 ------------------------------------------------------------------- - slack 0.143 + slack 0.111 -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) + Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.345ns Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -12437,3037 +6241,1003 @@ Slack (MET) : 0.143ns (arrival time - required time) clock source latency -1.848 -1.848 propagated clock network latency 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE f u_cpu/u_csr/lladdr_reg[9]/D + SLICE_X37Y49 FDRE 0.000 -0.504 r u_cpu/u_csr/csr_tlbidx_reg[24]/C + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/u_csr/csr_tlbidx_reg[24]/Q + net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] + SLICE_X32Y53 FDRE f u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] + 1.602 -0.345 + clock pessimism 0.037 -0.308 + SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 + required time 0.238 + arrival time -0.127 ------------------------------------------------------------------- - slack 0.143 + slack 0.111 -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.490ns + Source Clock Delay (SCD): -0.711ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.138 -0.711 + SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q + net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] + SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.457 -0.490 + clock pessimism 0.040 -0.450 + SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] + ------------------------------------------------------------------- + required time 0.395 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.112 + +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.490ns + Source Clock Delay (SCD): -0.711ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.138 -0.711 + SLICE_X85Y171 FDCE 0.000 -0.711 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q + net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] + SLICE_X81Y173 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.457 -0.490 + clock pessimism 0.040 -0.450 + SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] + ------------------------------------------------------------------- + required time 0.395 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.112 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 + required time 0.212 + arrival time -0.099 ------------------------------------------------------------------- - slack 0.148 + slack 0.113 -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 f u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.524ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.192 -0.534 - SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.626 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.524 - -Slack (MET) : 0.548ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.214 -0.556 - SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.648 - arrival time -0.101 - ------------------------------------------------------------------- - slack 0.548 - -Slack (MET) : 0.558ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) + Logic Levels: 0 + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.310 -0.539 + SLICE_X47Y10 FDRE 0.000 -0.539 r u_cpu/btb/ras_ptr_reg[0]/C + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 f u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 f u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.212 + arrival time -0.099 + ------------------------------------------------------------------- + slack 0.113 + +Slack (MET) : 0.114ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.399ns + Source Clock Delay (SCD): -0.629ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR + 1.219 -0.629 + SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q + net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 + SLICE_X85Y98 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0 + SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O + net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 + SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg + 1.548 -0.399 + clock pessimism 0.037 -0.362 + SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] ------------------------------------------------------------------- - required time 0.620 + required time 0.255 + arrival time -0.141 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.114ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.399ns + Source Clock Delay (SCD): -0.629ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.219 -0.629 + SLICE_X83Y93 FDCE 0.000 -0.629 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q + net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 + SLICE_X85Y98 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/I0 + SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O + net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 + SLICE_X85Y98 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.548 -0.399 + clock pessimism 0.037 -0.362 + SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] + ------------------------------------------------------------------- + required time 0.255 + arrival time -0.141 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] + ------------------------------------------------------------------- + required time 0.177 arrival time -0.063 ------------------------------------------------------------------- - slack 0.558 + slack 0.115 -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- - required time 0.645 + required time 0.177 arrival time -0.063 ------------------------------------------------------------------- - slack 0.583 + slack 0.115 -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- - required time 0.645 + required time 0.177 arrival time -0.063 ------------------------------------------------------------------- - slack 0.583 + slack 0.115 -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + 1.384 -0.465 + SLICE_X2Y49 FDRE 0.000 -0.465 r u_confreg/confreg_int_edge_reg[3]/C + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 f u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/I0 + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 f u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE f u_confreg/u_int_ctrl/edge_int_state_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] ------------------------------------------------------------------- - required time 0.645 + required time 0.177 arrival time -0.063 ------------------------------------------------------------------- - slack 0.583 + slack 0.115 -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.650ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns + Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR + 1.384 -0.465 + SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q + net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] + SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.608 -0.339 - clock pessimism -0.192 -0.531 - SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] ------------------------------------------------------------------- - required time 0.598 - arrival time 0.052 + required time 0.193 + arrival time -0.078 ------------------------------------------------------------------- - slack 0.650 + slack 0.115 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.384 -0.465 + SLICE_X1Y49 FDCE 0.000 -0.465 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q + net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] + SLICE_X3Y51 FDCE f u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.642 -0.305 + clock pessimism 0.037 -0.268 + SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] + ------------------------------------------------------------------- + required time 0.193 + arrival time -0.078 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.116ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q + net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.154 + ------------------------------------------------------------------- + slack 0.116 + +Slack (MET) : 0.116ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.230 -0.619 + SLICE_X157Y151 FDCE 0.000 -0.619 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q + net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] + SLICE_X159Y140 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.560 -0.387 + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.154 + ------------------------------------------------------------------- + slack 0.116 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.651 + slack 0.117 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.651 + slack 0.117 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.651 + slack 0.117 -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.651 + slack 0.117 -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15475,41 +7245,39 @@ Slack (MET) : 0.800ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.800 + slack 0.117 -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15517,41 +7285,39 @@ Slack (MET) : 0.800ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.800 + slack 0.117 -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15559,41 +7325,39 @@ Slack (MET) : 0.800ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.800 + slack 0.117 -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15601,41 +7365,39 @@ Slack (MET) : 0.800ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.800 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15643,41 +7405,39 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15685,41 +7445,39 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15727,41 +7485,39 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15769,41 +7525,39 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15811,41 +7565,39 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15853,41 +7605,39 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15895,41 +7645,39 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -15937,475 +7685,123 @@ Slack (MET) : 0.805ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + 1.354 -0.495 + SLICE_X12Y44 FDCE 0.000 -0.495 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 f u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 f u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + 1.610 -0.337 + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- - slack 0.805 + slack 0.117 -Slack (MET) : 0.824ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.824 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.118ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O + net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 + required time 0.283 + arrival time -0.165 ------------------------------------------------------------------- - slack 0.859 + slack 0.118 -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.118ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O + net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 + SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.165 + ------------------------------------------------------------------- + slack 0.118 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.403ns + Source Clock Delay (SCD): -0.630ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -16413,423 +7809,233 @@ Slack (MET) : 0.859ns (arrival time - required time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR + 1.218 -0.630 + SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q + net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] + SLICE_X82Y61 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3 + SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O + net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] + SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] + 1.544 -0.403 + clock pessimism 0.037 -0.366 + SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 + required time 0.274 + arrival time -0.156 ------------------------------------------------------------------- - slack 0.859 + slack 0.119 -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.403ns + Source Clock Delay (SCD): -0.630ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR + 1.218 -0.630 + SLICE_X84Y61 FDRE 0.000 -0.630 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q + net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] + SLICE_X82Y61 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/I3 + SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O + net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] + SLICE_X82Y61 FDRE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0] + 1.544 -0.403 + clock pessimism 0.037 -0.366 + SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 + required time 0.274 + arrival time -0.156 ------------------------------------------------------------------- - slack 0.860 + slack 0.119 -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.418ns + Source Clock Delay (SCD): -0.645ns + Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR + 1.203 -0.645 + SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q + net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg + 1.529 -0.418 + clock pessimism -0.227 -0.645 + SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 + required time 0.567 + arrival time -0.448 ------------------------------------------------------------------- - slack 0.860 + slack 0.119 -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Logic Levels: 0 + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.418ns + Source Clock Delay (SCD): -0.645ns + Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR + 1.203 -0.645 + SLICE_X39Y105 FDRE 0.000 -0.645 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 f u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q + net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] + SLICE_X39Y105 FDRE f u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0] + 1.529 -0.418 + clock pessimism -0.227 -0.645 + SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 + required time 0.567 + arrival time -0.448 ------------------------------------------------------------------- - slack 0.868 + slack 0.119 -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O + net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1] + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 + required time 0.284 + arrival time -0.164 ------------------------------------------------------------------- - slack 0.868 + slack 0.120 -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR + 1.208 -0.640 + SLICE_X144Y148 FDCE 0.000 -0.640 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/I1 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O + net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 + SLICE_X151Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2] + 1.527 -0.420 + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 + required time 0.284 + arrival time -0.164 ------------------------------------------------------------------- - slack 0.868 + slack 0.120 -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) +Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR @@ -16837,41 +8043,251 @@ Slack (MET) : 0.885ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] + 1.684 -0.263 + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 + required time 0.573 + arrival time 0.154 ------------------------------------------------------------------- - slack 0.885 + slack 0.727 -Slack (MET) : 0.885ns (arrival time - required time) +Slack (MET) : 0.727ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.684 -0.263 + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.573 + arrival time 0.154 + ------------------------------------------------------------------- + slack 0.727 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.761ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.236 + ------------------------------------------------------------------- + slack 0.761 + +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR @@ -16879,215 +8295,3945 @@ Slack (MET) : 0.885ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 0.885 + slack 0.765 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.736ns (logic 0.227ns (30.836%) route 0.509ns (69.164%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.228 0.239 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y39 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.684 -0.263 + clock pessimism -0.196 -0.459 + SLICE_X13Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.551 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.551 + arrival time 0.239 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.790 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.853ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.329 + ------------------------------------------------------------------- + slack 0.853 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.860ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.310 + ------------------------------------------------------------------- + slack 0.860 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.299 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.299 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.872ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.301 + ------------------------------------------------------------------- + slack 0.872 + +Slack (MET) : 0.890ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.864ns (logic 0.186ns (21.517%) route 0.678ns (78.483%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.372 0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13] + 1.567 -0.380 + clock pessimism -0.192 -0.572 + SLICE_X112Y66 FDCE (Remov_fdce_C_CLR) -0.067 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.639 + arrival time 0.251 ------------------------------------------------------------------- - slack 0.906 + slack 0.890 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.914ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.786ns (logic 0.249ns (31.687%) route 0.537ns (68.313%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.377ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.371 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21] + 1.570 -0.377 + clock pessimism -0.192 -0.569 + SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.734 + arrival time 0.179 ------------------------------------------------------------------- - slack 0.906 + slack 0.914 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.381 -0.468 + SLICE_X5Y45 FDCE 0.000 -0.468 r pll_clk.u_rst_cpu/delay_reg[1]/C + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 r pll_clk.u_rst_cpu/reset_i_1/I0 + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.918ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.021ns (logic 0.246ns (24.092%) route 0.775ns (75.908%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.489 0.526 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X11Y53 FDCE f u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.611 -0.336 + clock pessimism 0.037 -0.299 + SLICE_X11Y53 FDCE (Remov_fdce_C_CLR) -0.092 -0.391 u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.391 + arrival time 0.526 + ------------------------------------------------------------------- + slack 0.918 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.932ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29] + 1.558 -0.389 + clock pessimism -0.192 -0.581 + SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.721 + arrival time 0.210 ------------------------------------------------------------------- - slack 0.906 + slack 0.932 -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.848 -1.848 propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3] + ------------------------------------------------------------------- + required time 0.638 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.935 + +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.208 + ------------------------------------------------------------------- + slack 0.944 + +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.208 + ------------------------------------------------------------------- + slack 0.944 + +Slack (MET) : 0.947ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.211ns (25.751%) route 0.608ns (74.249%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.377ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.371 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.570 -0.377 + clock pessimism -0.192 -0.569 + SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] + ------------------------------------------------------------------- + required time 0.734 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.947 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.569 -0.378 + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.249ns (30.308%) route 0.573ns (69.692%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.035ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.407 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y67 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X125Y67 FDCE (Remov_fdce_C_CLR) -0.165 -0.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37] + ------------------------------------------------------------------- + required time 0.736 + arrival time 0.215 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.354 -0.495 + SLICE_X8Y43 FDCE 0.000 -0.495 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.685 -0.262 + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X113Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + clock pessimism -0.192 -0.581 + SLICE_X113Y75 FDCE (Remov_fdce_C_CLR) -0.165 -0.746 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5] + ------------------------------------------------------------------- + required time 0.746 + arrival time 0.210 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.960ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.235 -0.613 + SLICE_X106Y69 FDCE 0.000 -0.613 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 r pll_clk.u_rst_sys/rdb_addr[11]_i_3/I0 + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X113Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.568 -0.379 + clock pessimism -0.192 -0.571 + SLICE_X113Y65 FDCE (Remov_fdce_C_CLR) -0.092 -0.663 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] + ------------------------------------------------------------------- + required time 0.663 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.960 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r clock source latency -1.947 -1.947 propagated clock network latency 1.564 -0.383 clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5] + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1] ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 + required time 0.740 + arrival time 0.221 ------------------------------------------------------------------- - slack 0.906 + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[7] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[8] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.564 -0.383 + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[9] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.962ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[251] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.228 + ------------------------------------------------------------------- + slack 0.962 + +Slack (MET) : 0.962ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.835ns (logic 0.249ns (29.836%) route 0.586ns (70.164%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.420 0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X130Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X130Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[254] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.228 + ------------------------------------------------------------------- + slack 0.962 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[104] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[105] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[106] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[107] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[108] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[109] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[110] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.863ns (logic 0.249ns (28.862%) route 0.614ns (71.138%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.448 0.256 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X132Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.571 -0.376 + clock pessimism -0.192 -0.568 + SLICE_X132Y65 FDCE (Remov_fdce_C_CLR) -0.140 -0.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[111] + ------------------------------------------------------------------- + required time 0.708 + arrival time 0.256 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.965ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.850ns (logic 0.211ns (24.816%) route 0.639ns (75.184%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.242 -0.606 + SLICE_X112Y65 FDCE 0.000 -0.606 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.164 -0.442 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.237 -0.205 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.047 -0.158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.558 -0.389 + clock pessimism -0.192 -0.581 + SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] + ------------------------------------------------------------------- + required time 0.721 + arrival time 0.244 + ------------------------------------------------------------------- + slack 0.965 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.848 -1.848 + propagated clock network latency + 1.352 -0.497 + SLICE_X11Y38 FDCE 0.000 -0.497 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -1.947 -1.947 + propagated clock network latency + 1.686 -0.261 + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 diff --git a/fpga/vivado_reports_nodsp/timing_setup_paths.rpt b/fpga/vivado_reports_nodsp/timing_setup_paths.rpt index 090a5ca..61cee24 100644 --- a/fpga/vivado_reports_nodsp/timing_setup_paths.rpt +++ b/fpga/vivado_reports_nodsp/timing_setup_paths.rpt @@ -1,1490 +1,30 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:12 2026 +| Date : Fri Jul 10 04:14:53 2026 | Host : fedora running 64-bit unknown -| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_setup_paths.rpt +| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_setup_paths.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Report -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1496,61 +36,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -1562,24 +100,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1591,61 +129,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -1657,24 +193,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1686,61 +222,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -1752,24 +286,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1781,61 +315,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -1847,24 +379,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1876,61 +408,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -1942,24 +472,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -1971,61 +501,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -2037,24 +565,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -2066,61 +594,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -2132,24 +658,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -2161,61 +687,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -2227,24 +751,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -2256,61 +780,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -2322,24 +844,24 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -2351,61 +873,59 @@ Slack (MET) : 0.377ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 r base_ram_be_n_OBUF[3]_inst/I + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -2417,974 +937,1364 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/I2 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/I0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.382 17.707 + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 f ext_ram_data_IOBUF[23]_inst/OBUFT/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3396,38 +2306,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3440,24 +2371,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3469,38 +2400,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3513,24 +2465,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3542,38 +2494,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3586,24 +2559,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3615,38 +2588,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3659,24 +2653,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3688,38 +2682,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3732,24 +2747,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3761,38 +2776,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3805,24 +2841,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3834,38 +2870,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3878,24 +2935,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3907,38 +2964,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -3951,24 +3029,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3980,38 +3058,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -4024,24 +3123,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4053,38 +3152,59 @@ Slack (MET) : 0.424ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 f base_ram_data_IOBUF[1]_inst/OBUFT/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -4097,754 +3217,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4856,61 +3246,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -4922,24 +3311,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -4951,61 +3340,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5017,24 +3405,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5046,61 +3434,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5112,24 +3499,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5141,61 +3528,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5207,24 +3593,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5236,61 +3622,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5302,24 +3687,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5331,61 +3716,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5397,24 +3781,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5426,61 +3810,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5492,24 +3875,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5521,61 +3904,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5587,24 +3969,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5616,61 +3998,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5682,24 +4063,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -5711,61 +4092,60 @@ Slack (MET) : 0.455ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -5777,1704 +4157,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -7486,60 +4186,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -7552,24 +4251,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -7581,60 +4280,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -7647,24 +4345,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -7676,60 +4374,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -7742,24 +4439,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -7771,60 +4468,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -7837,24 +4533,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -7866,60 +4562,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -7932,24 +4627,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -7961,60 +4656,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -8027,24 +4721,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -8056,60 +4750,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -8122,24 +4815,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -8151,60 +4844,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -8217,24 +4909,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -8246,60 +4938,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -8312,24 +5003,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -8341,60 +5032,59 @@ Slack (MET) : 0.555ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -8407,14107 +5097,20775 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 4.581ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[24] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T + AD17 f ext_ram_data_IOBUF[24]_inst/OBUFT/T + AD17 OBUFT (TriStatE_obuft_T_O) + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] + AD17 r ext_ram_data[24] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.043 + ------------------------------------------------------------------- + slack 0.311 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[1] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/I5 + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 r base_ram_be_n_OBUF[1]_inst/I + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/I2 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/I0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.381 17.706 + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.789 -2.487 + SLICE_X123Y83 FDRE 0.000 -2.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/I2 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/I0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.373 17.699 + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.955 -2.321 + SLICE_X7Y62 FDCE 0.000 -2.321 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I3 + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/I5 + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/S[3] + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/I2 + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/S[1] + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CI + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I0 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 f base_ram_data_IOBUF[0]_inst/OBUFT/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 0.000 14.326 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.882 28.530 + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.883 28.531 + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.473 + arrival time -25.962 + ------------------------------------------------------------------- + slack 1.512 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.781 28.429 + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.371 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.855 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.782 28.430 + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.372 + arrival time -25.516 + ------------------------------------------------------------------- + slack 1.856 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.777 28.425 + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.367 + arrival time -25.451 + ------------------------------------------------------------------- + slack 1.916 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 f u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 r u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 r u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 4.051 -2.225 + SLICE_X35Y35 FDRE 0.000 -2.225 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/I5 + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/S[0] + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CI + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/I1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I2 + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/S + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/I1 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/I3 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way[1]_i_18/I3 + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 f u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 f u_cpu/u_csr/write_buffer_way_reg[1]_i_11/S[0] + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CI + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 r u_cpu/wb_stage/write_buffer_way[1]_i_5/I1 + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I1 + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/I0 + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/I0 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/I4 + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 f u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/I1 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 f u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 f u_cpu/if_stage/fetch_pc_r[6]_i_4/I2 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 r u_cpu/if_stage/fetch_pc_r[6]_i_2/I2 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 r u_cpu/if_stage/fetch_pc_r[6]_i_1/I2 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/I4 + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + clock source latency -5.674 24.648 + propagated clock network latency + 3.779 28.427 + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.369 + arrival time -25.450 + ------------------------------------------------------------------- + slack 1.920 + +Slack (MET) : 8.003ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%)) - Logic Levels: 1 (LUT1=1) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0] + ------------------------------------------------------------------- + required time 16.482 + arrival time -8.480 + ------------------------------------------------------------------- + slack 8.003 + +Slack (MET) : 8.062ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0] + ------------------------------------------------------------------- + required time 16.482 + arrival time -8.420 + ------------------------------------------------------------------- + slack 8.062 + +Slack (MET) : 8.086ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.323ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0] + ------------------------------------------------------------------- + required time 16.482 + arrival time -8.396 + ------------------------------------------------------------------- + slack 8.086 + +Slack (MET) : 8.089ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.480 + ------------------------------------------------------------------- + slack 8.089 + +Slack (MET) : 8.089ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.480 + ------------------------------------------------------------------- + slack 8.089 + +Slack (MET) : 8.089ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.480 + ------------------------------------------------------------------- + slack 8.089 + +Slack (MET) : 8.148ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.420 + ------------------------------------------------------------------- + slack 8.148 + +Slack (MET) : 8.148ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.420 + ------------------------------------------------------------------- + slack 8.148 + +Slack (MET) : 8.148ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.907ns (logic 0.670ns (6.143%) route 10.237ns (93.857%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.420 + ------------------------------------------------------------------- + slack 8.148 + +Slack (MET) : 8.172ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.323ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.396 + ------------------------------------------------------------------- + slack 8.172 + +Slack (MET) : 8.172ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.323ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.396 + ------------------------------------------------------------------- + slack 8.172 + +Slack (MET) : 8.172ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.891ns (logic 0.608ns (5.582%) route 10.283ns (94.418%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.323ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.396 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.396 + ------------------------------------------------------------------- + slack 8.172 + +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.372 + +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.372 + +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.372 + +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.372 + +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.372 + +Slack (MET) : 8.421ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0] + ------------------------------------------------------------------- + required time 16.482 + arrival time -8.061 + ------------------------------------------------------------------- + slack 8.421 + +Slack (MET) : 8.432ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.432 + +Slack (MET) : 8.432ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.432 + +Slack (MET) : 8.432ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.432 + +Slack (MET) : 8.432ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.432 + +Slack (MET) : 8.432ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.432 + +Slack (MET) : 8.456ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.456 + +Slack (MET) : 8.456ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.456 + +Slack (MET) : 8.456ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.456 + +Slack (MET) : 8.456ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.456 + +Slack (MET) : 8.456ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.456 + +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.458 + +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.458 + +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.458 + +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.114 + ------------------------------------------------------------------- + slack 8.458 + +Slack (MET) : 8.467ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0] + ------------------------------------------------------------------- + required time 16.482 + arrival time -8.015 + ------------------------------------------------------------------- + slack 8.467 + +Slack (MET) : 8.507ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.061 + ------------------------------------------------------------------- + slack 8.507 + +Slack (MET) : 8.507ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.061 + ------------------------------------------------------------------- + slack 8.507 + +Slack (MET) : 8.507ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.548ns (logic 0.668ns (6.333%) route 9.880ns (93.667%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.061 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.061 + ------------------------------------------------------------------- + slack 8.507 + +Slack (MET) : 8.518ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.518 + +Slack (MET) : 8.518ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.518 + +Slack (MET) : 8.518ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.518 + +Slack (MET) : 8.518ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.541ns (logic 0.670ns (6.356%) route 9.871ns (93.644%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.054 + ------------------------------------------------------------------- + slack 8.518 + +Slack (MET) : 8.542ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.542 + +Slack (MET) : 8.542ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.542 + +Slack (MET) : 8.542ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.542 + +Slack (MET) : 8.542ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.526ns (logic 0.608ns (5.776%) route 9.918ns (94.224%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.030 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -8.030 + ------------------------------------------------------------------- + slack 8.542 + +Slack (MET) : 8.553ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.015 + ------------------------------------------------------------------- + slack 8.553 + +Slack (MET) : 8.553ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.015 + ------------------------------------------------------------------- + slack 8.553 + +Slack (MET) : 8.553ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.503ns (logic 0.766ns (7.293%) route 9.737ns (92.707%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.015 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.370 17.695 + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11] + ------------------------------------------------------------------- + required time 16.568 + arrival time -8.015 + ------------------------------------------------------------------- + slack 8.553 + +Slack (MET) : 8.665ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.821 + ------------------------------------------------------------------- + slack 8.665 + +Slack (MET) : 8.725ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.249ns (logic 0.670ns (6.537%) route 9.579ns (93.463%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.761 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.761 + ------------------------------------------------------------------- + slack 8.725 + +Slack (MET) : 8.749ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.233ns (logic 0.608ns (5.942%) route 9.625ns (94.058%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.737 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.737 + ------------------------------------------------------------------- + slack 8.749 + +Slack (MET) : 8.751ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.821 + ------------------------------------------------------------------- + slack 8.751 + +Slack (MET) : 8.791ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.791 + +Slack (MET) : 8.791ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.791 + +Slack (MET) : 8.791ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.791 + +Slack (MET) : 8.791ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.791 + +Slack (MET) : 8.791ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.791 + +Slack (MET) : 8.811ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.249ns (logic 0.670ns (6.537%) route 9.579ns (93.463%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.761 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.761 + ------------------------------------------------------------------- + slack 8.811 + +Slack (MET) : 8.835ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.233ns (logic 0.608ns (5.942%) route 9.625ns (94.058%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.319ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.737 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.737 + ------------------------------------------------------------------- + slack 8.835 + +Slack (MET) : 8.837ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.837 + +Slack (MET) : 8.837ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.837 + +Slack (MET) : 8.837ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.837 + +Slack (MET) : 8.837ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.837 + +Slack (MET) : 8.837ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4] + ------------------------------------------------------------------- + required time 16.486 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.837 + +Slack (MET) : 8.856ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.628 + ------------------------------------------------------------------- + slack 8.856 + +Slack (MET) : 8.856ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.628 + ------------------------------------------------------------------- + slack 8.856 + +Slack (MET) : 8.856ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.628 + ------------------------------------------------------------------- + slack 8.856 + +Slack (MET) : 8.877ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.877 + +Slack (MET) : 8.877ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.877 + +Slack (MET) : 8.877ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.877 + +Slack (MET) : 8.877ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.182ns (logic 0.668ns (6.560%) route 9.514ns (93.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/Q + net (fo=8, routed) 0.633 -1.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[0] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I2 + SLICE_X112Y66 LUT5 (Prop_lut5_I2_O) 0.150 -1.186 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.695 + ------------------------------------------------------------------- + slack 8.877 + +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.758 + ------------------------------------------------------------------- + slack 8.896 + +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.758 + ------------------------------------------------------------------- + slack 8.896 + +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.758 + ------------------------------------------------------------------- + slack 8.896 + +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.758 + ------------------------------------------------------------------- + slack 8.896 + +Slack (MET) : 8.916ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.056ns (logic 0.670ns (6.663%) route 9.386ns (93.337%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.568 + ------------------------------------------------------------------- + slack 8.916 + +Slack (MET) : 8.916ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.056ns (logic 0.670ns (6.663%) route 9.386ns (93.337%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.568 + ------------------------------------------------------------------- + slack 8.916 + +Slack (MET) : 8.916ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.056ns (logic 0.670ns (6.663%) route 9.386ns (93.337%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.568 + ------------------------------------------------------------------- + slack 8.916 + +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.660 17.986 + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0] + ------------------------------------------------------------------- + required time 16.773 + arrival time -7.850 + ------------------------------------------------------------------- + slack 8.923 + +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.660 17.986 + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2] + ------------------------------------------------------------------- + required time 16.773 + arrival time -7.850 + ------------------------------------------------------------------- + slack 8.923 + +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.660 17.986 + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5] + ------------------------------------------------------------------- + required time 16.773 + arrival time -7.850 + ------------------------------------------------------------------- + slack 8.923 + +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.923 + +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.923 + +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.923 + +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.137ns (logic 0.766ns (7.557%) route 9.371ns (92.443%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.478 -2.010 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.490 -1.520 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I3 + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.288 -1.232 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 7.649 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.374 17.699 + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9] + ------------------------------------------------------------------- + required time 16.572 + arrival time -7.649 + ------------------------------------------------------------------- + slack 8.923 + +Slack (MET) : 8.940ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.040ns (logic 0.608ns (6.056%) route 9.432ns (93.944%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.544 + ------------------------------------------------------------------- + slack 8.940 + +Slack (MET) : 8.940ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.040ns (logic 0.608ns (6.056%) route 9.432ns (93.944%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.544 + ------------------------------------------------------------------- + slack 8.940 + +Slack (MET) : 8.940ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.040ns (logic 0.608ns (6.056%) route 9.432ns (93.944%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.544 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8] + ------------------------------------------------------------------- + required time 16.484 + arrival time -7.544 + ------------------------------------------------------------------- + slack 8.940 + +Slack (MET) : 8.942ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X52Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.372 17.697 + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X52Y169 FDCE (Recov_fdce_C_CLR) -0.543 16.570 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8] + ------------------------------------------------------------------- + required time 16.570 + arrival time -7.628 + ------------------------------------------------------------------- + slack 8.942 + +Slack (MET) : 8.944ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.736 18.062 + clock pessimism -0.514 17.548 + clock uncertainty -0.071 17.478 + SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1 + ------------------------------------------------------------------- + required time 16.849 + arrival time -7.904 + ------------------------------------------------------------------- + slack 8.944 + +Slack (MET) : 8.944ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.736 18.062 + clock pessimism -0.514 17.548 + clock uncertainty -0.071 17.478 + SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1 + ------------------------------------------------------------------- + required time 16.849 + arrival time -7.904 + ------------------------------------------------------------------- + slack 8.944 + +Slack (MET) : 8.944ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.736 18.062 + clock pessimism -0.514 17.548 + clock uncertainty -0.071 17.478 + SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2 + ------------------------------------------------------------------- + required time 16.849 + arrival time -7.904 + ------------------------------------------------------------------- + slack 8.944 + +Slack (MET) : 8.956ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.698 + ------------------------------------------------------------------- + slack 8.956 + +Slack (MET) : 8.956ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.698 + ------------------------------------------------------------------- + slack 8.956 + +Slack (MET) : 8.956ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.698 + ------------------------------------------------------------------- + slack 8.956 + +Slack (MET) : 8.956ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.185ns (logic 0.670ns (6.578%) route 9.515ns (93.422%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.488ns + Clock Pessimism Removal (CPR): -0.514ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + clock source latency -6.275 -6.275 + propagated clock network latency + 3.788 -2.488 + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/Q + net (fo=7, routed) 0.990 -0.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[1] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I1 + SLICE_X112Y66 LUT5 (Prop_lut5_I1_O) 0.152 -0.827 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.698 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + clock source latency -5.674 14.326 + propagated clock network latency + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5] + ------------------------------------------------------------------- + required time 16.654 + arrival time -7.698 + ------------------------------------------------------------------- + slack 8.956 + +Slack (MET) : 8.980ns (required time - arrival time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%)) + Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.151ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.542 17.868 - clock pessimism -0.507 17.361 - clock uncertainty -0.071 17.290 - SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2] - ------------------------------------------------------------------- - required time 16.681 - arrival time -12.101 - ------------------------------------------------------------------- - slack 4.581 - -Slack (MET) : 5.171ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.547 17.873 - clock pessimism -0.507 17.366 - clock uncertainty -0.071 17.295 - SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0] - ------------------------------------------------------------------- - required time 16.686 - arrival time -11.515 - ------------------------------------------------------------------- - slack 5.171 - -Slack (MET) : 5.624ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2] - ------------------------------------------------------------------- - required time 16.782 - arrival time -11.158 - ------------------------------------------------------------------- - slack 5.624 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 - ------------------------------------------------------------------- - slack 6.650 - -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 - ------------------------------------------------------------------- - slack 6.650 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -22518,43 +25876,43 @@ Slack (MET) : 6.654ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13] + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.654 + arrival time -7.674 ------------------------------------------------------------------- - slack 6.654 + slack 8.980 -Slack (MET) : 6.654ns (required time - arrival time) +Slack (MET) : 8.980ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.151ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -22565,43 +25923,43 @@ Slack (MET) : 6.654ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14] + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.654 + arrival time -7.674 ------------------------------------------------------------------- - slack 6.654 + slack 8.980 -Slack (MET) : 6.654ns (required time - arrival time) +Slack (MET) : 8.980ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.151ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -22612,43 +25970,43 @@ Slack (MET) : 6.654ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15] + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.654 + arrival time -7.674 ------------------------------------------------------------------- - slack 6.654 + slack 8.980 -Slack (MET) : 6.814ns (required time - arrival time) +Slack (MET) : 8.980ns (required time - arrival time) Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Data Path Delay: 10.170ns (logic 0.608ns (5.979%) route 9.562ns (94.021%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.151ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) + Source Clock Delay (SCD): -2.496ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -22659,43 +26017,43 @@ Slack (MET) : 6.814ns (required time - arrival time) (clock sys_clk rise edge) 0.000 0.000 r clock source latency -6.275 -6.275 propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR + 3.780 -2.496 + SLICE_X106Y69 FDCE 0.000 -2.496 r pll_clk.u_rst_sys/delay_reg[1]/C + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 1.036 -1.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] + SLICE_X112Y66 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I0 + SLICE_X112Y66 LUT5 (Prop_lut5_I0_O) 0.152 -0.851 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11] + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.654 + arrival time -7.674 ------------------------------------------------------------------- - slack 6.814 + slack 8.980 -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.982ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -22707,9269 +26065,27 @@ Slack (MET) : 6.814ns (required time - arrival time) clock source latency -6.275 -6.275 propagated clock network latency 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR + SLICE_X112Y65 FDCE 0.000 -2.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/I4 + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X158Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r clock source latency -5.674 14.326 propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5] - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.143ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.926 - ------------------------------------------------------------------- - slack 7.143 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.288ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.027 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3] - ------------------------------------------------------------------- - required time 17.027 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.288 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.345ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X3Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.924 18.249 - clock pessimism -0.507 17.743 - clock uncertainty -0.071 17.672 - SLICE_X3Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.063 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1] - ------------------------------------------------------------------- - required time 17.063 - arrival time -9.718 - ------------------------------------------------------------------- - slack 7.345 - -Slack (MET) : 7.388ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.160ns (logic 0.606ns (4.983%) route 11.554ns (95.017%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.227ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.754ns = ( 18.246 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.047 9.673 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X5Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.921 18.246 - clock pessimism -0.507 17.740 - clock uncertainty -0.071 17.669 - SLICE_X5Y8 FDCE (Recov_fdce_C_CLR) -0.609 17.060 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0] - ------------------------------------------------------------------- - required time 17.060 - arrival time -9.673 - ------------------------------------------------------------------- - slack 7.388 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.431ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X2Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.924 18.249 - clock pessimism -0.507 17.743 - clock uncertainty -0.071 17.672 - SLICE_X2Y3 FDCE (Recov_fdce_C_CLR) -0.523 17.149 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4] - ------------------------------------------------------------------- - required time 17.149 - arrival time -9.718 - ------------------------------------------------------------------- - slack 7.431 - -Slack (MET) : 7.510ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.038ns (logic 0.606ns (5.034%) route 11.432ns (94.966%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.925 9.551 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X5Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.551 - ------------------------------------------------------------------- - slack 7.510 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.638ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg - ------------------------------------------------------------------- - required time 17.108 - arrival time -9.470 - ------------------------------------------------------------------- - slack 7.638 - -Slack (MET) : 7.638ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3] - ------------------------------------------------------------------- - required time 17.108 - arrival time -9.470 - ------------------------------------------------------------------- - slack 7.638 - -Slack (MET) : 7.641ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.911ns (logic 0.606ns (5.088%) route 11.305ns (94.912%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.798 9.423 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X1Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.423 - ------------------------------------------------------------------- - slack 7.641 - -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0] - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 - ------------------------------------------------------------------- - slack 7.668 - -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1] - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 - ------------------------------------------------------------------- - slack 7.668 - -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2] - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 - ------------------------------------------------------------------- - slack 7.668 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] + 3.542 17.867 + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X158Y190 FDCE (Recov_fdce_C_CLR) -0.543 16.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4] ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 + required time 16.740 + arrival time -7.758 ------------------------------------------------------------------- - slack 11.519 + slack 8.982 diff --git a/fpga/vivado_reports_nodsp/timing_summary_full.rpt b/fpga/vivado_reports_nodsp/timing_summary_full.rpt index ef11c9c..88f0414 100644 --- a/fpga/vivado_reports_nodsp/timing_summary_full.rpt +++ b/fpga/vivado_reports_nodsp/timing_summary_full.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:10 2026 +| Date : Fri Jul 10 04:14:51 2026 | Host : fedora running 64-bit unknown -| Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_full.rpt +| Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_summary_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report @@ -208,7 +208,7 @@ video_vsync WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 0.167 0.000 0 115177 7.000 0.000 0 42610 + 0.146 0.000 0 113333 7.000 0.000 0 42143 All user specified timing constraints are met. @@ -219,13 +219,12 @@ All user specified timing constraints are met. | ------------- ------------------------------------------------------------------------------------------------ -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk {0.000 10.000} 20.000 50.000 - clkfbout_clk_pll {0.000 10.000} 20.000 50.000 - cpu_clk {0.000 15.161} 30.323 32.979 - mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 - sys_clk {0.000 10.000} 20.000 50.000 +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 10.000} 20.000 50.000 + clkfbout_clk_pll {0.000 10.000} 20.000 50.000 + cpu_clk {0.000 15.161} 30.323 32.979 + sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ @@ -233,13 +232,12 @@ clk {0.000 10.000} 20.000 50.000 | ----------------- ------------------------------------------------------------------------------------------------ -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk 7.000 0.000 0 1 - clkfbout_clk_pll 17.845 0.000 0 3 - cpu_clk 2.716 0.000 0 17197 13.911 0.000 0 6486 - mlkem_clk_clk_pll 10.807 0.000 0 48474 18.750 0.000 0 26131 - sys_clk 0.167 0.000 0 22818 8.750 0.000 0 9989 +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 7.000 0.000 0 1 + clkfbout_clk_pll 17.845 0.000 0 3 + cpu_clk 1.509 0.000 0 17197 13.911 0.000 0 6486 + sys_clk 0.146 0.000 0 69558 8.750 0.000 0 35653 ------------------------------------------------------------------------------------------------ @@ -247,10 +245,8 @@ clk | ----------------- ------------------------------------------------------------------------------------------------ -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- -sys_clk mlkem_clk_clk_pll 14.363 0.000 0 108 -mlkem_clk_clk_pll sys_clk 16.175 0.000 0 59 +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ @@ -260,11 +256,8 @@ mlkem_clk_clk_pll sys_clk 16.175 0.000 Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- -**async_default** cpu_clk cpu_clk 25.793 0.000 0 67 -**async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 23.497 0.000 0 25694 -**async_default** sys_clk mlkem_clk_clk_pll 9.156 0.000 0 4 -**async_default** mlkem_clk_clk_pll sys_clk 11.249 0.000 0 2 -**async_default** sys_clk sys_clk 4.581 0.000 0 886 +**async_default** cpu_clk cpu_clk 26.490 0.000 0 67 +**async_default** sys_clk sys_clk 8.003 0.000 0 26511 ------------------------------------------------------------------------------------------------ @@ -341,7 +334,7 @@ Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN @@ -353,7 +346,7 @@ Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 From Clock: cpu_clk To Clock: cpu_clk -Setup : 0 Failing Endpoints, Worst Slack 2.716ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 1.509ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- @@ -361,20 +354,20 @@ PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Vio Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE +Slack (MET) : 1.509ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 28.188ns (logic 5.333ns (18.919%) route 22.855ns (81.081%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.014ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.792ns = ( 28.530 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -390,72 +383,69 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.924 25.963 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -466,32 +456,148 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.036 28.530 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/cpu_clk + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 28.112 + clock uncertainty -0.074 28.038 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.472 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.472 + arrival time -25.963 + ------------------------------------------------------------------- + slack 1.509 + +Slack (MET) : 1.512ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 28.186ns (logic 5.333ns (18.920%) route 22.853ns (81.079%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: 0.015ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.791ns = ( 28.531 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.922 25.962 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.037 28.531 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/cpu_clk + RAMB18_X1Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.113 + clock uncertainty -0.074 28.039 + RAMB18_X1Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.473 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg ------------------------------------------------------------------- required time 27.473 - arrival time -24.757 + arrival time -25.962 ------------------------------------------------------------------- - slack 2.716 + slack 1.512 -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -507,72 +613,69 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -583,32 +686,33 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.935 28.429 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/cpu_clk + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 + required time 27.371 + arrival time -25.516 ------------------------------------------------------------------- - slack 2.716 + slack 1.855 -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE +Slack (MET) : 1.855ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.087ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.893ns = ( 28.429 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -624,72 +728,69 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -700,32 +801,33 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.935 28.429 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/cpu_clk + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 28.011 + clock uncertainty -0.074 27.937 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.371 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 + required time 27.371 + arrival time -25.516 ------------------------------------------------------------------- - slack 2.716 + slack 1.855 -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -741,72 +843,69 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -817,32 +916,33 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.936 28.430 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/cpu_clk + RAMB18_X2Y2 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y2 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 + required time 27.372 + arrival time -25.516 ------------------------------------------------------------------- - slack 2.716 + slack 1.856 -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE +Slack (MET) : 1.856ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.741ns (logic 5.333ns (19.224%) route 22.408ns (80.776%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.086ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.892ns = ( 28.430 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -858,72 +958,69 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.477 25.516 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -934,32 +1031,33 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.936 28.430 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/cpu_clk + RAMB18_X2Y3 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.012 + clock uncertainty -0.074 27.938 + RAMB18_X2Y3 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.372 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 + required time 27.372 + arrival time -25.516 ------------------------------------------------------------------- - slack 2.716 + slack 1.856 -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -975,72 +1073,69 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -1051,32 +1146,33 @@ Slack (MET) : 2.716ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.931 28.425 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/cpu_clk + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 + required time 27.367 + arrival time -25.451 ------------------------------------------------------------------- - slack 2.716 + slack 1.916 -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D +Slack (MET) : 1.916ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.676ns (logic 5.333ns (19.269%) route 22.343ns (80.731%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.091ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.897ns = ( 28.425 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -1092,82 +1188,69 @@ Slack (MET) : 2.751ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.412 25.451 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -1178,32 +1261,33 @@ Slack (MET) : 2.751ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.931 28.425 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/cpu_clk + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 28.007 + clock uncertainty -0.074 27.933 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.367 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 + required time 27.367 + arrival time -25.451 ------------------------------------------------------------------- - slack 2.751 + slack 1.916 -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -1219,82 +1303,69 @@ Slack (MET) : 2.754ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -1305,32 +1376,33 @@ Slack (MET) : 2.754ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.933 28.427 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/cpu_clk + RAMB18_X2Y4 RAMB18E1 r u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y4 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 + required time 27.369 + arrival time -25.450 ------------------------------------------------------------------- - slack 2.754 + slack 1.920 -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D +Slack (MET) : 1.920ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.674ns (logic 5.333ns (19.271%) route 22.341ns (80.729%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.089ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.895ns = ( 28.427 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -1346,82 +1418,69 @@ Slack (MET) : 2.789ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.410 25.450 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/ADDRBWRADDR[2] + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -1432,666 +1491,32 @@ Slack (MET) : 2.789ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.933 28.427 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/cpu_clk + RAMB18_X2Y5 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.009 + clock uncertainty -0.074 27.935 + RAMB18_X2Y5 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.369 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 + required time 27.369 + arrival time -25.450 ------------------------------------------------------------------- - slack 2.789 + slack 1.920 -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.959ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.468ns (logic 7.073ns (25.750%) route 20.395ns (74.250%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O - net (fo=27, routed) 1.068 23.412 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 - SLICE_X45Y35 LUT4 (Prop_lut4_I2_O) 0.150 23.562 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O - net (fo=1, routed) 1.078 24.640 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 - SLICE_X39Y34 LUT6 (Prop_lut6_I1_O) 0.326 24.966 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O - net (fo=1, routed) 0.000 24.966 u_cpu/exe_stage/ds_to_es_bus[118] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.029 27.926 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] - ------------------------------------------------------------------- - required time 27.926 - arrival time -24.966 - ------------------------------------------------------------------- - slack 2.959 - -Slack (MET) : 3.081ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.303ns (logic 7.073ns (25.905%) route 20.230ns (74.095%)) - Logic Levels: 32 (CARRY4=5 LUT3=2 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.059ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.945ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 1.096 21.904 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y31 LUT6 (Prop_lut6_I5_O) 0.124 22.028 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_19/O - net (fo=4, routed) 0.942 22.969 u_cpu/id_stage/ds_to_es_bus_r[188]_i_19_n_0 - SLICE_X43Y28 LUT3 (Prop_lut3_I2_O) 0.150 23.119 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_11/O - net (fo=1, routed) 0.652 23.771 u_cpu/id_stage/ds_to_es_bus_r[181]_i_11_n_0 - SLICE_X43Y28 LUT6 (Prop_lut6_I5_O) 0.326 24.097 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O - net (fo=1, routed) 0.581 24.678 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 - SLICE_X46Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.802 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O - net (fo=1, routed) 0.000 24.802 u_cpu/exe_stage/ds_to_es_bus[131] - SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_cpu/exe_stage/cpu_clk - SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C - clock pessimism -0.498 27.880 - clock uncertainty -0.074 27.806 - SLICE_X46Y28 FDRE (Setup_fdre_C_D) 0.077 27.883 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] - ------------------------------------------------------------------- - required time 27.883 - arrival time -24.802 - ------------------------------------------------------------------- - slack 3.081 - -Slack (MET) : 3.101ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.282ns (logic 6.845ns (25.090%) route 20.437ns (74.910%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O - net (fo=15, routed) 1.068 23.250 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 - SLICE_X43Y32 LUT4 (Prop_lut4_I2_O) 0.124 23.374 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_2/O - net (fo=1, routed) 1.282 24.656 u_cpu/id_stage/ds_to_es_bus_r[176]_i_2_n_0 - SLICE_X46Y24 LUT6 (Prop_lut6_I1_O) 0.124 24.780 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O - net (fo=1, routed) 0.000 24.780 u_cpu/exe_stage/ds_to_es_bus[126] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.081 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] - ------------------------------------------------------------------- - required time 27.882 - arrival time -24.780 - ------------------------------------------------------------------- - slack 3.101 - -Slack (MET) : 3.107ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.229ns (logic 6.845ns (25.138%) route 20.384ns (74.862%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.277 23.041 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X51Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.165 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_12/O - net (fo=1, routed) 0.649 23.814 u_cpu/id_stage/ds_to_es_bus_r[186]_i_12_n_0 - SLICE_X47Y27 LUT5 (Prop_lut5_I0_O) 0.124 23.938 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_5/O - net (fo=1, routed) 0.666 24.604 u_cpu/id_stage/ds_to_es_bus_r[186]_i_5_n_0 - SLICE_X45Y27 LUT6 (Prop_lut6_I4_O) 0.124 24.728 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O - net (fo=1, routed) 0.000 24.728 u_cpu/exe_stage/ds_to_es_bus[136] - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] - ------------------------------------------------------------------- - required time 27.835 - arrival time -24.728 - ------------------------------------------------------------------- - slack 3.107 - -Slack (MET) : 3.111ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 1.988ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.278ns (logic 6.845ns (25.094%) route 20.433ns (74.906%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) - Source Clock Delay (SCD): -2.502ns + Data Path Delay: 27.905ns (logic 7.157ns (25.647%) route 20.748ns (74.353%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.384ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.110ns = ( 28.212 - 30.323 ) + Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -2108,82 +1533,83 @@ Slack (MET) : 3.111ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.127 22.946 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_0 - SLICE_X48Y33 LUT4 (Prop_lut4_I0_O) 0.124 23.070 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O - net (fo=1, routed) 0.656 23.726 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 - SLICE_X46Y30 LUT6 (Prop_lut6_I1_O) 0.124 23.850 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O - net (fo=1, routed) 0.803 24.652 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 - SLICE_X44Y33 LUT6 (Prop_lut6_I4_O) 0.124 24.776 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O - net (fo=1, routed) 0.000 24.776 u_cpu/exe_stage/ds_to_es_bus[117] - SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O + net (fo=29, routed) 1.565 24.339 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 + SLICE_X50Y37 LUT6 (Prop_lut6_I4_O) 0.124 24.463 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O + net (fo=1, routed) 1.094 25.557 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 + SLICE_X58Y50 LUT6 (Prop_lut6_I4_O) 0.124 25.681 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O + net (fo=1, routed) 0.000 25.681 u_cpu/exe_stage/ds_to_es_bus[117] + SLICE_X58Y50 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -2194,32 +1620,32 @@ Slack (MET) : 3.111ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk - SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C - clock pessimism -0.498 27.885 - clock uncertainty -0.074 27.811 - SLICE_X44Y33 FDRE (Setup_fdre_C_D) 0.077 27.888 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.718 28.212 u_cpu/exe_stage/cpu_clk + SLICE_X58Y50 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C + clock pessimism -0.498 27.714 + clock uncertainty -0.074 27.640 + SLICE_X58Y50 FDRE (Setup_fdre_C_D) 0.029 27.669 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] ------------------------------------------------------------------- - required time 27.888 - arrival time -24.776 + required time 27.669 + arrival time -25.681 ------------------------------------------------------------------- - slack 3.111 + slack 1.988 -Slack (MET) : 3.117ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D +Slack (MET) : 1.995ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.301ns (logic 7.095ns (25.988%) route 20.206ns (74.012%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.595ns (logic 5.333ns (19.326%) route 22.262ns (80.674%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.093ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.899ns = ( 28.423 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -2235,82 +1661,69 @@ Slack (MET) : 3.117ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O - net (fo=27, routed) 0.883 23.227 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 - SLICE_X44Y32 LUT2 (Prop_lut2_I1_O) 0.150 23.377 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O - net (fo=1, routed) 1.075 24.452 u_cpu/id_stage/ds_to_es_bus_r_reg[171] - SLICE_X41Y26 LUT6 (Prop_lut6_I2_O) 0.348 24.800 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O - net (fo=1, routed) 0.000 24.800 u_cpu/exe_stage/ds_to_es_bus[121] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.331 25.370 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -2321,32 +1734,33 @@ Slack (MET) : 3.117ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.029 27.917 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.929 28.423 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/cpu_clk + RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.005 + clock uncertainty -0.074 27.931 + RAMB18_X2Y6 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.365 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.917 - arrival time -24.800 + required time 27.365 + arrival time -25.370 ------------------------------------------------------------------- - slack 3.117 + slack 1.995 -Slack (MET) : 3.132ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D +Slack (MET) : 1.995ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.293ns (logic 7.073ns (25.915%) route 20.220ns (74.085%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.595ns (logic 5.333ns (19.326%) route 22.262ns (80.674%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.093ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.899ns = ( 28.423 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -2362,82 +1776,69 @@ Slack (MET) : 3.132ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 0.818 22.446 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X40Y24 LUT5 (Prop_lut5_I0_O) 0.326 22.772 r u_cpu/u_csr/ds_to_es_bus_r[187]_i_11/O - net (fo=1, routed) 0.976 23.747 u_cpu/id_stage/ds_to_es_bus_r_reg[187]_0 - SLICE_X40Y30 LUT4 (Prop_lut4_I2_O) 0.124 23.871 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O - net (fo=1, routed) 0.796 24.668 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 - SLICE_X41Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.792 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O - net (fo=1, routed) 0.000 24.792 u_cpu/exe_stage/ds_to_es_bus[137] - SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.331 25.370 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -2448,32 +1849,33 @@ Slack (MET) : 3.132ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk - SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C - clock pessimism -0.498 27.967 - clock uncertainty -0.074 27.893 - SLICE_X41Y31 FDRE (Setup_fdre_C_D) 0.031 27.924 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.929 28.423 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/cpu_clk + RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.005 + clock uncertainty -0.074 27.931 + RAMB18_X2Y7 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.365 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.924 - arrival time -24.792 + required time 27.365 + arrival time -25.370 ------------------------------------------------------------------- - slack 3.132 + slack 1.995 -Slack (MET) : 3.146ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D +Slack (MET) : 2.008ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.188ns (logic 6.949ns (25.559%) route 20.239ns (74.441%)) - Logic Levels: 31 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.579ns (logic 5.333ns (19.337%) route 22.246ns (80.663%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.096ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.902ns = ( 28.420 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -2489,80 +1891,69 @@ Slack (MET) : 3.146ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.847 20.893 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y30 LUT5 (Prop_lut5_I2_O) 0.124 21.017 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_15/O - net (fo=8, routed) 1.169 22.186 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_1 - SLICE_X44Y30 LUT2 (Prop_lut2_I1_O) 0.148 22.334 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_12/O - net (fo=6, routed) 0.893 23.226 u_cpu/id_stage/ds_to_es_bus_r[183]_i_12_n_0 - SLICE_X41Y29 LUT6 (Prop_lut6_I3_O) 0.328 23.554 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_3/O - net (fo=1, routed) 1.008 24.562 u_cpu/id_stage/ds_to_es_bus_r[180]_i_3_n_0 - SLICE_X43Y26 LUT6 (Prop_lut6_I2_O) 0.124 24.686 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O - net (fo=1, routed) 0.000 24.686 u_cpu/exe_stage/ds_to_es_bus[130] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.315 25.354 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/ADDRBWRADDR[2] + RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -2573,32 +1964,33 @@ Slack (MET) : 3.146ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.032 27.833 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.926 28.420 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/cpu_clk + RAMB18_X2Y6 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 28.002 + clock uncertainty -0.074 27.928 + RAMB18_X2Y6 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.362 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.833 - arrival time -24.686 + required time 27.362 + arrival time -25.354 ------------------------------------------------------------------- - slack 3.146 + slack 2.008 -Slack (MET) : 3.154ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D +Slack (MET) : 2.008ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.182ns (logic 6.845ns (25.182%) route 20.337ns (74.818%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.579ns (logic 5.333ns (19.337%) route 22.246ns (80.663%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.096ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.902ns = ( 28.420 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -2614,82 +2006,69 @@ Slack (MET) : 3.154ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O - net (fo=32, routed) 1.325 23.002 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 - SLICE_X46Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.126 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_10/O - net (fo=1, routed) 0.502 23.627 u_cpu/id_stage/ds_to_es_bus_r[185]_i_10_n_0 - SLICE_X46Y27 LUT6 (Prop_lut6_I5_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_4/O - net (fo=1, routed) 0.805 24.556 u_cpu/id_stage/ds_to_es_bus_r[185]_i_4_n_0 - SLICE_X45Y27 LUT6 (Prop_lut6_I3_O) 0.124 24.680 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O - net (fo=1, routed) 0.000 24.680 u_cpu/exe_stage/ds_to_es_bus[135] - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.315 25.354 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/ADDRBWRADDR[2] + RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -2700,32 +2079,33 @@ Slack (MET) : 3.154ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.926 28.420 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/cpu_clk + RAMB18_X2Y7 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 28.002 + clock uncertainty -0.074 27.928 + RAMB18_X2Y7 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.362 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.835 - arrival time -24.680 + required time 27.362 + arrival time -25.354 ------------------------------------------------------------------- - slack 3.154 + slack 2.008 -Slack (MET) : 3.179ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D +Slack (MET) : 2.064ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.162ns (logic 6.845ns (25.201%) route 20.317ns (74.799%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.521ns (logic 5.333ns (19.378%) route 22.188ns (80.622%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.098ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.904ns = ( 28.418 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -2741,82 +2121,69 @@ Slack (MET) : 3.179ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O - net (fo=32, routed) 1.184 22.860 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 - SLICE_X46Y31 LUT4 (Prop_lut4_I0_O) 0.124 22.984 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_13/O - net (fo=1, routed) 0.785 23.769 u_cpu/id_stage/ds_to_es_bus_r[189]_i_13_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.893 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_4/O - net (fo=1, routed) 0.643 24.536 u_cpu/id_stage/ds_to_es_bus_r[189]_i_4_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I3_O) 0.124 24.660 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O - net (fo=1, routed) 0.000 24.660 u_cpu/exe_stage/ds_to_es_bus[139] - SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.257 25.297 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRBWRADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -2827,32 +2194,33 @@ Slack (MET) : 3.179ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk - SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C - clock pessimism -0.498 27.885 - clock uncertainty -0.074 27.811 - SLICE_X47Y33 FDRE (Setup_fdre_C_D) 0.029 27.840 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.924 28.418 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/cpu_clk + RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.418 28.000 + clock uncertainty -0.074 27.926 + RAMB18_X2Y8 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[7]) + -0.566 27.360 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.840 - arrival time -24.660 + required time 27.360 + arrival time -25.297 ------------------------------------------------------------------- - slack 3.179 + slack 2.064 -Slack (MET) : 3.179ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D +Slack (MET) : 2.198ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.160ns (logic 7.073ns (26.042%) route 20.087ns (73.958%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.384ns (logic 5.333ns (19.475%) route 22.051ns (80.525%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=2 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.101ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.907ns = ( 28.415 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -2868,82 +2236,69 @@ Slack (MET) : 3.179ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.194 22.822 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X50Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.148 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O - net (fo=1, routed) 0.700 23.848 u_cpu/id_stage/ds_to_es_bus_r_reg[190] - SLICE_X47Y30 LUT6 (Prop_lut6_I2_O) 0.124 23.972 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O - net (fo=1, routed) 0.562 24.534 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 - SLICE_X45Y29 LUT5 (Prop_lut5_I1_O) 0.124 24.658 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O - net (fo=1, routed) 0.000 24.658 u_cpu/exe_stage/ds_to_es_bus[140] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 3.249 23.915 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X49Y33 LUT5 (Prop_lut5_I4_O) 0.124 24.039 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_8/O + net (fo=16, routed) 1.120 25.159 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/ADDRBWRADDR[2] + RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/ADDRARDADDR[7] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -2954,413 +2309,33 @@ Slack (MET) : 3.179ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.031 27.838 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.921 28.415 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/cpu_clk + RAMB18_X2Y8 RAMB18E1 r u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.418 27.997 + clock uncertainty -0.074 27.923 + RAMB18_X2Y8 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[7]) + -0.566 27.357 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.838 - arrival time -24.658 + required time 27.357 + arrival time -25.159 ------------------------------------------------------------------- - slack 3.179 + slack 2.198 -Slack (MET) : 3.222ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.251ns (logic 6.845ns (25.118%) route 20.406ns (74.882%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 0.885 22.649 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X39Y35 LUT4 (Prop_lut4_I2_O) 0.124 22.773 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_9/O - net (fo=1, routed) 1.128 23.901 u_cpu/id_stage/ds_to_es_bus_r[162]_i_9_n_0 - SLICE_X39Y33 LUT6 (Prop_lut6_I2_O) 0.124 24.025 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_4/O - net (fo=1, routed) 0.600 24.625 u_cpu/id_stage/ds_to_es_bus_r[162]_i_4_n_0 - SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.749 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_1/O - net (fo=1, routed) 0.000 24.749 u_cpu/exe_stage/ds_to_es_bus[112] - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/C - clock pessimism -0.498 27.969 - clock uncertainty -0.074 27.895 - SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.077 27.972 u_cpu/exe_stage/ds_to_es_bus_r_reg[162] - ------------------------------------------------------------------- - required time 27.972 - arrival time -24.749 - ------------------------------------------------------------------- - slack 3.222 - -Slack (MET) : 3.225ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.158ns (logic 6.845ns (25.204%) route 20.313ns (74.796%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.058ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O - net (fo=12, routed) 1.248 22.679 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 - SLICE_X48Y34 LUT4 (Prop_lut4_I2_O) 0.124 22.803 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_8/O - net (fo=1, routed) 0.983 23.787 u_cpu/id_stage/ds_to_es_bus_r[163]_i_8_n_0 - SLICE_X42Y34 LUT6 (Prop_lut6_I0_O) 0.124 23.911 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_4/O - net (fo=1, routed) 0.622 24.533 u_cpu/id_stage/ds_to_es_bus_r[163]_i_4_n_0 - SLICE_X42Y29 LUT6 (Prop_lut6_I3_O) 0.124 24.657 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O - net (fo=1, routed) 0.000 24.657 u_cpu/exe_stage/ds_to_es_bus[113] - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C - clock pessimism -0.498 27.879 - clock uncertainty -0.074 27.805 - SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.077 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] - ------------------------------------------------------------------- - required time 27.882 - arrival time -24.657 - ------------------------------------------------------------------- - slack 3.225 - -Slack (MET) : 3.228ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.103ns (logic 7.041ns (25.978%) route 20.062ns (74.021%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O - net (fo=12, routed) 0.831 22.262 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 - SLICE_X45Y31 LUT2 (Prop_lut2_I1_O) 0.118 22.380 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O - net (fo=1, routed) 0.965 23.345 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 - SLICE_X42Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.671 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O - net (fo=1, routed) 0.806 24.478 u_cpu/id_stage/ds_to_es_bus_r_reg[165] - SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.602 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O - net (fo=1, routed) 0.000 24.602 u_cpu/exe_stage/ds_to_es_bus[115] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] - ------------------------------------------------------------------- - required time 27.830 - arrival time -24.602 - ------------------------------------------------------------------- - slack 3.228 - -Slack (MET) : 3.306ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.528ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.027ns (logic 6.845ns (25.326%) route 20.182ns (74.674%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.715ns (logic 7.360ns (26.556%) route 20.355ns (73.444%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.403ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -3376,82 +2351,83 @@ Slack (MET) : 3.306ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.269 23.016 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.140 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_11/O - net (fo=1, routed) 0.487 23.627 u_cpu/id_stage/ds_to_es_bus_r[174]_i_11_n_0 - SLICE_X45Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_4/O - net (fo=1, routed) 0.651 24.402 u_cpu/id_stage/ds_to_es_bus_r[174]_i_4_n_0 - SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.526 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O - net (fo=1, routed) 0.000 24.526 u_cpu/exe_stage/ds_to_es_bus[124] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y23 LUT5 (Prop_lut5_I2_O) 0.119 21.947 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 1.248 23.194 u_cpu/id_stage/fs_to_ds_bus_r_reg[45]_3 + SLICE_X48Y28 LUT6 (Prop_lut6_I5_O) 0.332 23.526 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_7/O + net (fo=1, routed) 0.598 24.125 u_cpu/id_stage/ds_to_es_bus_r[174]_i_7_n_0 + SLICE_X48Y26 LUT5 (Prop_lut5_I0_O) 0.124 24.249 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_3/O + net (fo=1, routed) 1.118 25.366 u_cpu/id_stage/ds_to_es_bus_r[174]_i_3_n_0 + SLICE_X35Y26 LUT6 (Prop_lut6_I2_O) 0.124 25.490 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O + net (fo=1, routed) 0.000 25.490 u_cpu/exe_stage/ds_to_es_bus[124] + SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -3462,32 +2438,32 @@ Slack (MET) : 3.306ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk + SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C + clock pessimism -0.403 28.063 + clock uncertainty -0.074 27.989 + SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.029 28.018 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] ------------------------------------------------------------------- - required time 27.832 - arrival time -24.526 + required time 28.018 + arrival time -25.490 ------------------------------------------------------------------- - slack 3.306 + slack 2.528 -Slack (MET) : 3.315ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.548ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.066ns (logic 6.845ns (25.290%) route 20.221ns (74.710%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.056ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.948ns = ( 28.375 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.673ns (logic 7.157ns (25.862%) route 20.516ns (74.138%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.058ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.865ns = ( 28.458 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -3503,82 +2479,83 @@ Slack (MET) : 3.315ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.101 22.527 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X46Y22 LUT5 (Prop_lut5_I2_O) 0.124 22.651 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_10/O - net (fo=1, routed) 0.985 23.636 u_cpu/id_stage/ds_to_es_bus_r[178]_i_10_n_0 - SLICE_X46Y26 LUT6 (Prop_lut6_I2_O) 0.124 23.760 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O - net (fo=1, routed) 0.680 24.440 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 - SLICE_X46Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.564 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O - net (fo=1, routed) 0.000 24.564 u_cpu/exe_stage/ds_to_es_bus[128] - SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O + net (fo=29, routed) 1.305 24.078 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 + SLICE_X28Y26 LUT5 (Prop_lut5_I2_O) 0.124 24.202 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_5/O + net (fo=1, routed) 1.122 25.325 u_cpu/id_stage/ds_to_es_bus_r[183]_i_5_n_0 + SLICE_X38Y25 LUT6 (Prop_lut6_I4_O) 0.124 25.449 r u_cpu/id_stage/ds_to_es_bus_r[183]_i_1/O + net (fo=1, routed) 0.000 25.449 u_cpu/exe_stage/ds_to_es_bus[133] + SLICE_X38Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -3589,31 +2566,159 @@ Slack (MET) : 3.315ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.881 28.375 u_cpu/exe_stage/cpu_clk - SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C - clock pessimism -0.498 27.877 - clock uncertainty -0.074 27.803 - SLICE_X46Y26 FDRE (Setup_fdre_C_D) 0.077 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.964 28.458 u_cpu/exe_stage/cpu_clk + SLICE_X38Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[183]/C + clock pessimism -0.418 28.040 + clock uncertainty -0.074 27.966 + SLICE_X38Y25 FDRE (Setup_fdre_C_D) 0.031 27.997 u_cpu/exe_stage/ds_to_es_bus_r_reg[183] ------------------------------------------------------------------- - required time 27.880 - arrival time -24.564 + required time 27.997 + arrival time -25.449 ------------------------------------------------------------------- - slack 3.315 + slack 2.548 -Slack (MET) : 3.348ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.597ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.129ns (logic 6.845ns (25.231%) route 20.284ns (74.769%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) - Source Clock Delay (SCD): -2.502ns + Data Path Delay: 27.541ns (logic 7.157ns (25.987%) route 20.384ns (74.013%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.142ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.949ns = ( 28.374 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y23 LUT5 (Prop_lut5_I4_O) 0.124 21.952 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O + net (fo=20, routed) 1.394 23.346 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10 + SLICE_X48Y27 LUT6 (Prop_lut6_I3_O) 0.124 23.470 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_8/O + net (fo=1, routed) 0.660 24.129 u_cpu/id_stage/ds_to_es_bus_r[181]_i_8_n_0 + SLICE_X48Y24 LUT6 (Prop_lut6_I0_O) 0.124 24.253 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O + net (fo=1, routed) 0.939 25.192 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 + SLICE_X43Y27 LUT6 (Prop_lut6_I3_O) 0.124 25.316 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O + net (fo=1, routed) 0.000 25.316 u_cpu/exe_stage/ds_to_es_bus[131] + SLICE_X43Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.880 28.374 u_cpu/exe_stage/cpu_clk + SLICE_X43Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C + clock pessimism -0.418 27.956 + clock uncertainty -0.074 27.882 + SLICE_X43Y27 FDRE (Setup_fdre_C_D) 0.031 27.913 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] + ------------------------------------------------------------------- + required time 27.913 + arrival time -25.316 + ------------------------------------------------------------------- + slack 2.597 + +Slack (MET) : 2.616ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRBWRADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.721ns (logic 5.333ns (19.958%) route 21.388ns (80.042%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.346ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.072ns = ( 28.251 - 30.323 ) + Source Clock Delay (SCD): -2.225ns Clock Pessimism Removal (CPR): -0.498ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -3630,82 +2735,69 @@ Slack (MET) : 3.348ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X44Y31 LUT4 (Prop_lut4_I0_O) 0.124 23.189 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_7/O - net (fo=1, routed) 0.553 23.742 u_cpu/id_stage/ds_to_es_bus_r[166]_i_7_n_0 - SLICE_X40Y31 LUT5 (Prop_lut5_I0_O) 0.124 23.866 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_3/O - net (fo=1, routed) 0.638 24.504 u_cpu/id_stage/ds_to_es_bus_r[166]_i_3_n_0 - SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.628 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O - net (fo=1, routed) 0.000 24.628 u_cpu/exe_stage/ds_to_es_bus[116] - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O + net (fo=4, routed) 0.838 24.496 u_cpu/icache/tagv_ram_way[0].u/ADDRARDADDR[2] + RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRBWRADDR[6] ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -3716,32 +2808,626 @@ Slack (MET) : 3.348ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C - clock pessimism -0.498 27.969 - clock uncertainty -0.074 27.895 - SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.081 27.976 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.756 28.251 u_cpu/icache/tagv_ram_way[0].u/cpu_clk + RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.498 27.752 + clock uncertainty -0.074 27.678 + RAMB18_X3Y20 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[6]) + -0.566 27.112 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg ------------------------------------------------------------------- - required time 27.976 - arrival time -24.628 + required time 27.112 + arrival time -24.496 ------------------------------------------------------------------- - slack 3.348 + slack 2.616 -Slack (MET) : 3.380ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.616ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRBWRADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.721ns (logic 5.333ns (19.958%) route 21.388ns (80.042%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.346ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.072ns = ( 28.251 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O + net (fo=4, routed) 0.838 24.496 u_cpu/icache/tagv_ram_way[1].u/ADDRARDADDR[2] + RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRBWRADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.756 28.251 u_cpu/icache/tagv_ram_way[1].u/cpu_clk + RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK + clock pessimism -0.498 27.752 + clock uncertainty -0.074 27.678 + RAMB18_X3Y21 RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[6]) + -0.566 27.112 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.112 + arrival time -24.496 + ------------------------------------------------------------------- + slack 2.616 + +Slack (MET) : 2.621ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[18]/CE + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.237ns (logic 5.705ns (20.946%) route 21.532ns (79.054%)) + Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.186ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.921ns = ( 28.402 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok + SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O + net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 + SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O + net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin + SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O + net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin + SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O + net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go + SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O + net (fo=32, routed) 3.808 25.012 u_cpu/if_stage/flush_inst_req_buffer + SLICE_X115Y16 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[18]/CE + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.908 28.402 u_cpu/if_stage/cpu_clk + SLICE_X115Y16 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[18]/C + clock pessimism -0.490 27.912 + clock uncertainty -0.074 27.838 + SLICE_X115Y16 FDRE (Setup_fdre_C_CE) -0.205 27.633 u_cpu/if_stage/flush_inst_req_buffer_reg[18] + ------------------------------------------------------------------- + required time 27.633 + arrival time -25.012 + ------------------------------------------------------------------- + slack 2.621 + +Slack (MET) : 2.748ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.588ns (logic 5.333ns (20.058%) route 21.255ns (79.942%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.347ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.073ns = ( 28.250 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O + net (fo=4, routed) 0.705 24.363 u_cpu/icache/tagv_ram_way[0].u/ADDRARDADDR[2] + RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.755 28.250 u_cpu/icache/tagv_ram_way[0].u/cpu_clk + RAMB18_X3Y20 RAMB18E1 r u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.498 27.751 + clock uncertainty -0.074 27.677 + RAMB18_X3Y20 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + -0.566 27.111 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.111 + arrival time -24.363 + ------------------------------------------------------------------- + slack 2.748 + +Slack (MET) : 2.748ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.588ns (logic 5.333ns (20.058%) route 21.255ns (79.942%)) + Logic Levels: 26 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.347ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.073ns = ( 28.250 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.498ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 0.531 16.794 u_cpu/if_stage/nextpc5 + SLICE_X51Y27 LUT6 (Prop_lut6_I2_O) 0.124 16.918 r u_cpu/if_stage/fetch_pc_r[6]_i_4/O + net (fo=1, routed) 3.059 19.977 u_cpu/if_stage/fetch_pc_r[6]_i_4_n_0 + SLICE_X114Y28 LUT6 (Prop_lut6_I2_O) 0.124 20.101 r u_cpu/if_stage/fetch_pc_r[6]_i_2/O + net (fo=1, routed) 0.441 20.542 u_cpu/if_stage/fetch_pc_r[6]_i_2_n_0 + SLICE_X114Y25 LUT6 (Prop_lut6_I2_O) 0.124 20.666 r u_cpu/if_stage/fetch_pc_r[6]_i_1/O + net (fo=6, routed) 2.868 23.534 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_2[2] + SLICE_X60Y50 LUT6 (Prop_lut6_I5_O) 0.124 23.658 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg_i_7__0/O + net (fo=4, routed) 0.705 24.363 u_cpu/icache/tagv_ram_way[1].u/ADDRARDADDR[2] + RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.755 28.250 u_cpu/icache/tagv_ram_way[1].u/cpu_clk + RAMB18_X3Y21 RAMB18E1 r u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK + clock pessimism -0.498 27.751 + clock uncertainty -0.074 27.677 + RAMB18_X3Y21 RAMB18E1 (Setup_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + -0.566 27.111 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg + ------------------------------------------------------------------- + required time 27.111 + arrival time -24.363 + ------------------------------------------------------------------- + slack 2.748 + +Slack (MET) : 2.850ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.001ns (logic 6.845ns (25.351%) route 20.156ns (74.649%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Data Path Delay: 27.342ns (logic 7.157ns (26.176%) route 20.185ns (73.824%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.138ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.945ns = ( 28.378 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.887 21.879 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X45Y20 LUT6 (Prop_lut6_I0_O) 0.124 22.003 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O + net (fo=26, routed) 1.241 23.244 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 + SLICE_X50Y27 LUT6 (Prop_lut6_I3_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_9/O + net (fo=1, routed) 1.040 24.408 u_cpu/id_stage/ds_to_es_bus_r[179]_i_9_n_0 + SLICE_X48Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.532 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_3/O + net (fo=1, routed) 0.462 24.993 u_cpu/id_stage/ds_to_es_bus_r[179]_i_3_n_0 + SLICE_X44Y28 LUT5 (Prop_lut5_I2_O) 0.124 25.117 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O + net (fo=1, routed) 0.000 25.117 u_cpu/exe_stage/ds_to_es_bus[129] + SLICE_X44Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.884 28.378 u_cpu/exe_stage/cpu_clk + SLICE_X44Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C + clock pessimism -0.418 27.960 + clock uncertainty -0.074 27.886 + SLICE_X44Y28 FDRE (Setup_fdre_C_D) 0.081 27.967 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] + ------------------------------------------------------------------- + required time 27.967 + arrival time -25.117 + ------------------------------------------------------------------- + slack 2.850 + +Slack (MET) : 2.850ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.335ns (logic 7.157ns (26.183%) route 20.178ns (73.817%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=4 LUT5=7 LUT6=12 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -3757,82 +3443,83 @@ Slack (MET) : 3.380ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O - net (fo=15, routed) 1.094 23.277 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.401 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_2/O - net (fo=1, routed) 0.974 24.375 u_cpu/id_stage/ds_to_es_bus_r[179]_i_2_n_0 - SLICE_X46Y24 LUT5 (Prop_lut5_I1_O) 0.124 24.499 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O - net (fo=1, routed) 0.000 24.499 u_cpu/exe_stage/ds_to_es_bus[129] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y23 LUT5 (Prop_lut5_I4_O) 0.124 21.952 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_24/O + net (fo=20, routed) 1.178 23.130 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_10 + SLICE_X49Y28 LUT4 (Prop_lut4_I0_O) 0.124 23.254 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_8/O + net (fo=1, routed) 0.659 23.913 u_cpu/id_stage/ds_to_es_bus_r[177]_i_8_n_0 + SLICE_X48Y29 LUT4 (Prop_lut4_I3_O) 0.124 24.037 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_3/O + net (fo=1, routed) 0.949 24.986 u_cpu/id_stage/ds_to_es_bus_r[177]_i_3_n_0 + SLICE_X44Y25 LUT6 (Prop_lut6_I2_O) 0.124 25.110 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O + net (fo=1, routed) 0.000 25.110 u_cpu/exe_stage/ds_to_es_bus[127] + SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -3843,32 +3530,32 @@ Slack (MET) : 3.380ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.079 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] + SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C + clock pessimism -0.418 27.955 + clock uncertainty -0.074 27.881 + SLICE_X44Y25 FDRE (Setup_fdre_C_D) 0.079 27.960 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] ------------------------------------------------------------------- - required time 27.880 - arrival time -24.499 + required time 27.960 + arrival time -25.110 ------------------------------------------------------------------- - slack 3.380 + slack 2.850 -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.883ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][10]/CE + Destination: u_cpu/addr_trans/inst_vaddr_buffer_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.236ns (logic 5.209ns (19.126%) route 22.027ns (80.874%)) + Logic Levels: 25 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.049ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -3884,72 +3571,67 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 3.828 20.091 u_cpu/if_stage/nextpc5 + SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.215 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_4/O + net (fo=1, routed) 0.280 20.495 u_cpu/if_stage/flush_inst_req_buffer[20]_i_4_n_0 + SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.619 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_2/O + net (fo=1, routed) 0.159 20.777 u_cpu/if_stage/flush_inst_req_buffer[20]_i_2_n_0 + SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.901 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_1/O + net (fo=3, routed) 4.110 25.011 u_cpu/addr_trans/D[8] + SLICE_X38Y32 FDRE r u_cpu/addr_trans/inst_vaddr_buffer_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -3960,32 +3642,32 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][10] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.973 28.467 u_cpu/addr_trans/cpu_clk + SLICE_X38Y32 FDRE r u_cpu/addr_trans/inst_vaddr_buffer_reg[20]/C + clock pessimism -0.418 28.049 + clock uncertainty -0.074 27.975 + SLICE_X38Y32 FDRE (Setup_fdre_C_D) -0.081 27.894 u_cpu/addr_trans/inst_vaddr_buffer_reg[20] ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 + required time 27.894 + arrival time -25.011 ------------------------------------------------------------------- - slack 3.393 + slack 2.883 -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.901ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][18]/CE + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.282ns (logic 7.157ns (26.234%) route 20.125ns (73.766%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -4001,72 +3683,83 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O + net (fo=29, routed) 1.330 24.103 u_cpu/u_csr/ds_to_es_bus_r_reg[184]_0 + SLICE_X43Y25 LUT6 (Prop_lut6_I5_O) 0.124 24.227 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O + net (fo=1, routed) 0.706 24.933 u_cpu/id_stage/ds_to_es_bus_r_reg[184] + SLICE_X42Y25 LUT6 (Prop_lut6_I3_O) 0.124 25.057 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O + net (fo=1, routed) 0.000 25.057 u_cpu/exe_stage/ds_to_es_bus[134] + SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -4077,32 +3770,32 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][18] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.877 28.371 u_cpu/exe_stage/cpu_clk + SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C + clock pessimism -0.418 27.953 + clock uncertainty -0.074 27.879 + SLICE_X42Y25 FDRE (Setup_fdre_C_D) 0.079 27.958 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 + required time 27.958 + arrival time -25.057 ------------------------------------------------------------------- - slack 3.393 + slack 2.901 -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.901ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][23]/CE + Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[20]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 26.953ns (logic 5.705ns (21.167%) route 21.248ns (78.833%)) + Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.190ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.925ns = ( 28.398 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -4118,72 +3811,75 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok + SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O + net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 + SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O + net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin + SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O + net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin + SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O + net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go + SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O + net (fo=32, routed) 3.524 24.728 u_cpu/if_stage/flush_inst_req_buffer + SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[20]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -4194,32 +3890,32 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][23] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.904 28.398 u_cpu/if_stage/cpu_clk + SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[20]/C + clock pessimism -0.490 27.908 + clock uncertainty -0.074 27.834 + SLICE_X114Y19 FDRE (Setup_fdre_C_CE) -0.205 27.629 u_cpu/if_stage/flush_inst_req_buffer_reg[20] ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 + required time 27.629 + arrival time -24.728 ------------------------------------------------------------------- - slack 3.393 + slack 2.901 -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.901ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][27]/CE + Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[22]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 26.953ns (logic 5.705ns (21.167%) route 21.248ns (78.833%)) + Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.190ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.925ns = ( 28.398 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -4235,72 +3931,75 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok + SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O + net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 + SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O + net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin + SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O + net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin + SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O + net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go + SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O + net (fo=32, routed) 3.524 24.728 u_cpu/if_stage/flush_inst_req_buffer + SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[22]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -4311,32 +4010,32 @@ Slack (MET) : 3.393ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][27] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.904 28.398 u_cpu/if_stage/cpu_clk + SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[22]/C + clock pessimism -0.490 27.908 + clock uncertainty -0.074 27.834 + SLICE_X114Y19 FDRE (Setup_fdre_C_CE) -0.205 27.629 u_cpu/if_stage/flush_inst_req_buffer_reg[22] ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 + required time 27.629 + arrival time -24.728 ------------------------------------------------------------------- - slack 3.393 + slack 2.901 -Slack (MET) : 3.408ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.901ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D + Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[28]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.974ns (logic 7.073ns (26.222%) route 19.901ns (73.778%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 26.953ns (logic 5.705ns (21.167%) route 21.248ns (78.833%)) + Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.190ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.925ns = ( 28.398 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -4352,82 +4051,75 @@ Slack (MET) : 3.408ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.025 22.652 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X45Y28 LUT5 (Prop_lut5_I0_O) 0.326 22.978 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O - net (fo=1, routed) 0.653 23.631 u_cpu/id_stage/ds_to_es_bus_r_reg[182] - SLICE_X44Y28 LUT6 (Prop_lut6_I1_O) 0.124 23.755 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O - net (fo=1, routed) 0.593 24.348 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 - SLICE_X44Y27 LUT6 (Prop_lut6_I1_O) 0.124 24.472 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O - net (fo=1, routed) 0.000 24.472 u_cpu/exe_stage/ds_to_es_bus[132] - SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok + SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O + net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 + SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O + net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin + SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O + net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin + SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O + net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go + SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O + net (fo=32, routed) 3.524 24.728 u_cpu/if_stage/flush_inst_req_buffer + SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[28]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -4438,32 +4130,32 @@ Slack (MET) : 3.408ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X44Y27 FDRE (Setup_fdre_C_D) 0.077 27.881 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.904 28.398 u_cpu/if_stage/cpu_clk + SLICE_X114Y19 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[28]/C + clock pessimism -0.490 27.908 + clock uncertainty -0.074 27.834 + SLICE_X114Y19 FDRE (Setup_fdre_C_CE) -0.205 27.629 u_cpu/if_stage/flush_inst_req_buffer_reg[28] ------------------------------------------------------------------- - required time 27.881 - arrival time -24.472 + required time 27.629 + arrival time -24.728 ------------------------------------------------------------------- - slack 3.408 + slack 2.901 -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.912ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][29]/CE + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.310ns (logic 7.157ns (26.206%) route 20.153ns (73.794%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -4479,72 +4171,83 @@ Slack (MET) : 3.421ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O + net (fo=29, routed) 1.082 23.855 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 + SLICE_X31Y27 LUT5 (Prop_lut5_I2_O) 0.124 23.979 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_5/O + net (fo=1, routed) 0.982 24.962 u_cpu/id_stage/ds_to_es_bus_r[186]_i_5_n_0 + SLICE_X38Y27 LUT6 (Prop_lut6_I4_O) 0.124 25.086 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O + net (fo=1, routed) 0.000 25.086 u_cpu/exe_stage/ds_to_es_bus[136] + SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -4555,383 +4258,32 @@ Slack (MET) : 3.421ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][29] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk + SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C + clock pessimism -0.418 28.043 + clock uncertainty -0.074 27.969 + SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.029 27.998 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 + required time 27.998 + arrival time -25.086 ------------------------------------------------------------------- - slack 3.421 + slack 2.912 -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][2]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][2] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][4]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][4] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][7]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][7] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.432ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.943ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.954ns (logic 7.073ns (26.241%) route 19.881ns (73.759%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.943ns = ( 28.380 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.301ns (logic 7.360ns (26.959%) route 19.941ns (73.041%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.035ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.857ns = ( 28.466 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.403ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -4947,82 +4299,83 @@ Slack (MET) : 3.432ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.175 22.803 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X47Y31 LUT4 (Prop_lut4_I3_O) 0.326 23.129 r u_cpu/u_csr/ds_to_es_bus_r[188]_i_12/O - net (fo=1, routed) 0.667 23.796 u_cpu/id_stage/ds_to_es_bus_r_reg[188] - SLICE_X47Y31 LUT6 (Prop_lut6_I1_O) 0.124 23.920 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_5/O - net (fo=1, routed) 0.409 24.329 u_cpu/id_stage/ds_to_es_bus_r[188]_i_5_n_0 - SLICE_X48Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.453 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O - net (fo=1, routed) 0.000 24.453 u_cpu/exe_stage/ds_to_es_bus[138] - SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y23 LUT5 (Prop_lut5_I2_O) 0.119 21.947 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 1.128 23.074 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X46Y26 LUT4 (Prop_lut4_I3_O) 0.332 23.406 r u_cpu/u_csr/ds_to_es_bus_r[188]_i_12/O + net (fo=1, routed) 0.670 24.076 u_cpu/id_stage/ds_to_es_bus_r_reg[188] + SLICE_X46Y26 LUT6 (Prop_lut6_I1_O) 0.124 24.200 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_5/O + net (fo=1, routed) 0.752 24.953 u_cpu/id_stage/ds_to_es_bus_r[188]_i_5_n_0 + SLICE_X35Y26 LUT6 (Prop_lut6_I4_O) 0.124 25.077 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O + net (fo=1, routed) 0.000 25.077 u_cpu/exe_stage/ds_to_es_bus[138] + SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -5033,32 +4386,32 @@ Slack (MET) : 3.432ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.886 28.380 u_cpu/exe_stage/cpu_clk - SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C - clock pessimism -0.498 27.882 - clock uncertainty -0.074 27.808 - SLICE_X48Y31 FDRE (Setup_fdre_C_D) 0.077 27.885 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.972 28.466 u_cpu/exe_stage/cpu_clk + SLICE_X35Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C + clock pessimism -0.403 28.063 + clock uncertainty -0.074 27.989 + SLICE_X35Y26 FDRE (Setup_fdre_C_D) 0.031 28.020 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] ------------------------------------------------------------------- - required time 27.885 - arrival time -24.453 + required time 28.020 + arrival time -25.077 ------------------------------------------------------------------- - slack 3.432 + slack 2.943 -Slack (MET) : 3.450ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.979ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.937ns (logic 7.073ns (26.257%) route 19.864ns (73.743%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.058ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.248ns (logic 7.360ns (27.011%) route 19.888ns (72.989%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.052ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.859ns = ( 28.464 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -5074,82 +4427,83 @@ Slack (MET) : 3.450ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 0.952 22.579 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X42Y24 LUT5 (Prop_lut5_I1_O) 0.326 22.905 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O - net (fo=1, routed) 0.483 23.388 u_cpu/id_stage/ds_to_es_bus_r_reg[192] - SLICE_X42Y27 LUT4 (Prop_lut4_I3_O) 0.124 23.512 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O - net (fo=1, routed) 0.800 24.312 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 - SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 24.436 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O - net (fo=1, routed) 0.000 24.436 u_cpu/exe_stage/ds_to_es_bus[142] - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.836 21.828 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y23 LUT5 (Prop_lut5_I2_O) 0.119 21.947 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O + net (fo=20, routed) 1.140 23.086 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 + SLICE_X46Y28 LUT6 (Prop_lut6_I0_O) 0.332 23.418 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O + net (fo=1, routed) 0.699 24.117 u_cpu/id_stage/ds_to_es_bus_r_reg[190] + SLICE_X41Y27 LUT6 (Prop_lut6_I2_O) 0.124 24.241 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O + net (fo=1, routed) 0.659 24.900 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 + SLICE_X35Y24 LUT5 (Prop_lut5_I1_O) 0.124 25.024 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O + net (fo=1, routed) 0.000 25.024 u_cpu/exe_stage/ds_to_es_bus[140] + SLICE_X35Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -5160,32 +4514,32 @@ Slack (MET) : 3.450ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C - clock pessimism -0.498 27.879 - clock uncertainty -0.074 27.805 - SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.081 27.886 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.970 28.464 u_cpu/exe_stage/cpu_clk + SLICE_X35Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C + clock pessimism -0.418 28.046 + clock uncertainty -0.074 27.972 + SLICE_X35Y24 FDRE (Setup_fdre_C_D) 0.031 28.003 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] ------------------------------------------------------------------- - required time 27.886 - arrival time -24.436 + required time 28.003 + arrival time -25.024 ------------------------------------------------------------------- - slack 3.450 + slack 2.979 -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.983ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][13]/CE + Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[27]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 26.868ns (logic 5.705ns (21.233%) route 21.163ns (78.767%)) + Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.193ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns = ( 28.395 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -5201,72 +4555,75 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok + SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O + net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 + SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O + net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin + SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O + net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin + SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O + net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go + SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O + net (fo=32, routed) 3.439 24.643 u_cpu/if_stage/flush_inst_req_buffer + SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[27]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -5277,32 +4634,32 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][13] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.901 28.395 u_cpu/if_stage/cpu_clk + SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[27]/C + clock pessimism -0.490 27.905 + clock uncertainty -0.074 27.831 + SLICE_X114Y27 FDRE (Setup_fdre_C_CE) -0.205 27.626 u_cpu/if_stage/flush_inst_req_buffer_reg[27] ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 + required time 27.626 + arrival time -24.643 ------------------------------------------------------------------- - slack 3.466 + slack 2.983 -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.983ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][15]/CE + Destination: u_cpu/if_stage/flush_inst_req_buffer_reg[6]/CE (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 26.868ns (logic 5.705ns (21.233%) route 21.163ns (78.767%)) + Logic Levels: 29 (CARRY4=4 LUT3=1 LUT4=1 LUT5=5 LUT6=16 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.193ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns = ( 28.395 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -5318,72 +4675,75 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 r u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 r u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 r u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 f u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 f u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 f u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.893 18.334 u_cpu/exe_stage/data_addr_ok + SLICE_X44Y26 LUT6 (Prop_lut6_I1_O) 0.124 18.458 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11/O + net (fo=1, routed) 0.460 18.919 u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_11_n_0 + SLICE_X44Y24 LUT6 (Prop_lut6_I2_O) 0.124 19.043 f u_cpu/exe_stage/request_buffer_cacop_op_mode[1]_i_9/O + net (fo=1, routed) 0.465 19.507 u_cpu/id_stage/es_allowin + SLICE_X46Y23 LUT5 (Prop_lut5_I2_O) 0.124 19.631 f u_cpu/id_stage/request_buffer_cacop_op_mode[1]_i_7/O + net (fo=2, routed) 0.495 20.126 u_cpu/if_stage/fs_allowin + SLICE_X47Y23 LUT6 (Prop_lut6_I4_O) 0.124 20.250 f u_cpu/if_stage/btb_lock_buffer[37]_i_4/O + net (fo=7, routed) 0.831 21.081 u_cpu/if_stage/pfs_ready_go + SLICE_X49Y26 LUT6 (Prop_lut6_I1_O) 0.124 21.205 r u_cpu/if_stage/flush_inst_req_buffer[31]_i_1/O + net (fo=32, routed) 3.439 24.643 u_cpu/if_stage/flush_inst_req_buffer + SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -5394,32 +4754,32 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][15] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.901 28.395 u_cpu/if_stage/cpu_clk + SLICE_X114Y27 FDRE r u_cpu/if_stage/flush_inst_req_buffer_reg[6]/C + clock pessimism -0.490 27.905 + clock uncertainty -0.074 27.831 + SLICE_X114Y27 FDRE (Setup_fdre_C_CE) -0.205 27.626 u_cpu/if_stage/flush_inst_req_buffer_reg[6] ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 + required time 27.626 + arrival time -24.643 ------------------------------------------------------------------- - slack 3.466 + slack 2.983 -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.984ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][17]/CE + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.241ns (logic 7.157ns (26.273%) route 20.084ns (73.727%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -5435,72 +4795,83 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.017 22.650 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X40Y23 LUT6 (Prop_lut6_I1_O) 0.124 22.774 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_11/O + net (fo=29, routed) 1.085 23.859 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_2 + SLICE_X31Y26 LUT5 (Prop_lut5_I3_O) 0.124 23.983 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_6/O + net (fo=1, routed) 0.910 24.892 u_cpu/id_stage/ds_to_es_bus_r[189]_i_6_n_0 + SLICE_X38Y27 LUT6 (Prop_lut6_I5_O) 0.124 25.016 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O + net (fo=1, routed) 0.000 25.016 u_cpu/exe_stage/ds_to_es_bus[139] + SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -5511,32 +4882,32 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][17] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk + SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C + clock pessimism -0.418 28.043 + clock uncertainty -0.074 27.969 + SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 + required time 28.000 + arrival time -25.016 ------------------------------------------------------------------- - slack 3.466 + slack 2.984 -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.985ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][21]/CE + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.196ns (logic 7.157ns (26.317%) route 20.039ns (73.683%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -5552,72 +4923,83 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.157 22.789 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X41Y25 LUT6 (Prop_lut6_I1_O) 0.124 22.913 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_7/O + net (fo=9, routed) 1.073 23.986 u_cpu/id_stage/ds_to_es_bus_r[193]_i_7_n_0 + SLICE_X43Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.110 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_2/O + net (fo=1, routed) 0.737 24.847 u_cpu/id_stage/ds_to_es_bus_r[165]_i_2_n_0 + SLICE_X42Y25 LUT6 (Prop_lut6_I1_O) 0.124 24.971 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O + net (fo=1, routed) 0.000 24.971 u_cpu/exe_stage/ds_to_es_bus[115] + SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -5628,500 +5010,32 @@ Slack (MET) : 3.466ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][21] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.877 28.371 u_cpu/exe_stage/cpu_clk + SLICE_X42Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C + clock pessimism -0.418 27.953 + clock uncertainty -0.074 27.879 + SLICE_X42Y25 FDRE (Setup_fdre_C_D) 0.077 27.956 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 + required time 27.956 + arrival time -24.971 ------------------------------------------------------------------- - slack 3.466 + slack 2.985 -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.992ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][3]/CE + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][3] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][4]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][4] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][6]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][6] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][7]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][7] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.472ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Data Path Delay: 27.194ns (logic 7.157ns (26.318%) route 20.037ns (73.682%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=3 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -6137,82 +5051,83 @@ Slack (MET) : 3.472ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.266 22.692 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X45Y19 LUT5 (Prop_lut5_I4_O) 0.124 22.816 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_7/O - net (fo=1, routed) 0.650 23.467 u_cpu/id_stage/ds_to_es_bus_r[169]_i_7_n_0 - SLICE_X45Y24 LUT5 (Prop_lut5_I2_O) 0.124 23.591 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_3/O - net (fo=1, routed) 0.643 24.234 u_cpu/id_stage/ds_to_es_bus_r[169]_i_3_n_0 - SLICE_X45Y24 LUT6 (Prop_lut6_I2_O) 0.124 24.358 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_1/O - net (fo=1, routed) 0.000 24.358 u_cpu/exe_stage/ds_to_es_bus[119] - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.000 22.633 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X40Y23 LUT6 (Prop_lut6_I0_O) 0.124 22.757 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O + net (fo=15, routed) 0.959 23.716 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 + SLICE_X44Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.840 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_2/O + net (fo=1, routed) 1.006 24.845 u_cpu/id_stage/ds_to_es_bus_r[176]_i_2_n_0 + SLICE_X44Y25 LUT6 (Prop_lut6_I1_O) 0.124 24.969 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O + net (fo=1, routed) 0.000 24.969 u_cpu/exe_stage/ds_to_es_bus[126] + SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -6223,32 +5138,288 @@ Slack (MET) : 3.472ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[169] + SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C + clock pessimism -0.418 27.955 + clock uncertainty -0.074 27.881 + SLICE_X44Y25 FDRE (Setup_fdre_C_D) 0.081 27.962 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] ------------------------------------------------------------------- - required time 27.830 - arrival time -24.358 + required time 27.962 + arrival time -24.969 ------------------------------------------------------------------- - slack 3.472 + slack 2.992 -Slack (MET) : 3.473ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 2.994ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) + Data Path Delay: 27.252ns (logic 7.157ns (26.263%) route 20.095ns (73.737%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.032ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.403ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.887 21.879 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X45Y20 LUT6 (Prop_lut6_I0_O) 0.124 22.003 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_13/O + net (fo=26, routed) 1.128 23.131 u_cpu/id_stage/ds_to_es_bus_r[193]_i_13_n_0 + SLICE_X46Y29 LUT6 (Prop_lut6_I0_O) 0.124 23.255 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_11/O + net (fo=1, routed) 0.459 23.713 u_cpu/id_stage/ds_to_es_bus_r[191]_i_11_n_0 + SLICE_X44Y28 LUT6 (Prop_lut6_I5_O) 0.124 23.837 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_3/O + net (fo=1, routed) 1.066 24.903 u_cpu/id_stage/ds_to_es_bus_r[191]_i_3_n_0 + SLICE_X34Y28 LUT6 (Prop_lut6_I2_O) 0.124 25.027 r u_cpu/id_stage/ds_to_es_bus_r[191]_i_1/O + net (fo=1, routed) 0.000 25.027 u_cpu/exe_stage/ds_to_es_bus[141] + SLICE_X34Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk + SLICE_X34Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[191]/C + clock pessimism -0.403 28.066 + clock uncertainty -0.074 27.992 + SLICE_X34Y28 FDRE (Setup_fdre_C_D) 0.029 28.021 u_cpu/exe_stage/ds_to_es_bus_r_reg[191] + ------------------------------------------------------------------- + required time 28.021 + arrival time -25.027 + ------------------------------------------------------------------- + slack 2.994 + +Slack (MET) : 2.999ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.222ns (logic 7.391ns (27.150%) route 19.831ns (72.850%)) + Logic Levels: 32 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.056ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.748 22.380 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X45Y24 LUT6 (Prop_lut6_I0_O) 0.124 22.504 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O + net (fo=27, routed) 0.913 23.418 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 + SLICE_X45Y26 LUT2 (Prop_lut2_I1_O) 0.150 23.568 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O + net (fo=1, routed) 1.098 24.666 u_cpu/id_stage/ds_to_es_bus_r_reg[171] + SLICE_X38Y23 LUT6 (Prop_lut6_I2_O) 0.332 24.998 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O + net (fo=1, routed) 0.000 24.998 u_cpu/exe_stage/ds_to_es_bus[121] + SLICE_X38Y23 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk + SLICE_X38Y23 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C + clock pessimism -0.418 28.042 + clock uncertainty -0.074 27.968 + SLICE_X38Y23 FDRE (Setup_fdre_C_D) 0.029 27.997 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] + ------------------------------------------------------------------- + required time 27.997 + arrival time -24.998 + ------------------------------------------------------------------- + slack 2.999 + +Slack (MET) : 3.036ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.147ns (logic 7.157ns (26.364%) route 19.990ns (73.636%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -6264,82 +5435,83 @@ Slack (MET) : 3.473ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.155 22.581 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X42Y20 LUT5 (Prop_lut5_I4_O) 0.124 22.705 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O - net (fo=1, routed) 0.760 23.465 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 - SLICE_X42Y24 LUT5 (Prop_lut5_I0_O) 0.124 23.589 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O - net (fo=1, routed) 0.646 24.235 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 - SLICE_X45Y24 LUT6 (Prop_lut6_I3_O) 0.124 24.359 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O - net (fo=1, routed) 0.000 24.359 u_cpu/exe_stage/ds_to_es_bus[125] - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.892 21.883 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X38Y24 LUT6 (Prop_lut6_I2_O) 0.124 22.007 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O + net (fo=32, routed) 0.978 22.985 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_1 + SLICE_X34Y23 LUT6 (Prop_lut6_I0_O) 0.124 23.109 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_11/O + net (fo=1, routed) 0.702 23.811 u_cpu/id_stage/ds_to_es_bus_r[173]_i_11_n_0 + SLICE_X41Y23 LUT6 (Prop_lut6_I0_O) 0.124 23.935 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_4/O + net (fo=1, routed) 0.863 24.798 u_cpu/id_stage/ds_to_es_bus_r[173]_i_4_n_0 + SLICE_X44Y25 LUT6 (Prop_lut6_I4_O) 0.124 24.922 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_1/O + net (fo=1, routed) 0.000 24.922 u_cpu/exe_stage/ds_to_es_bus[123] + SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -6350,32 +5522,32 @@ Slack (MET) : 3.473ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] + SLICE_X44Y25 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[173]/C + clock pessimism -0.418 27.955 + clock uncertainty -0.074 27.881 + SLICE_X44Y25 FDRE (Setup_fdre_C_D) 0.077 27.958 u_cpu/exe_stage/ds_to_es_bus_r_reg[173] ------------------------------------------------------------------- - required time 27.832 - arrival time -24.359 + required time 27.958 + arrival time -24.922 ------------------------------------------------------------------- - slack 3.473 + slack 3.036 -Slack (MET) : 3.482ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C +Slack (MET) : 3.048ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][26]/CE + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Setup (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.650ns (logic 5.748ns (21.569%) route 20.902ns (78.431%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.089ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.915ns = ( 28.408 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns + Data Path Delay: 27.135ns (logic 7.157ns (26.376%) route 19.978ns (73.624%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.143ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -6391,72 +5563,83 @@ Slack (MET) : 3.482ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.872 24.148 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/CE + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 1.157 22.789 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X41Y25 LUT6 (Prop_lut6_I1_O) 0.124 22.913 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_7/O + net (fo=9, routed) 1.129 24.042 u_cpu/id_stage/ds_to_es_bus_r[193]_i_7_n_0 + SLICE_X46Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.166 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_2/O + net (fo=1, routed) 0.620 24.786 u_cpu/id_stage/ds_to_es_bus_r[166]_i_2_n_0 + SLICE_X46Y24 LUT6 (Prop_lut6_I1_O) 0.124 24.910 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O + net (fo=1, routed) 0.000 24.910 u_cpu/exe_stage/ds_to_es_bus[116] + SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -6467,17 +5650,739 @@ Slack (MET) : 3.482ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.914 28.408 u_cpu/btb/cpu_clk - SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/C - clock pessimism -0.498 27.910 - clock uncertainty -0.074 27.836 - SLICE_X114Y41 FDRE (Setup_fdre_C_CE) -0.205 27.631 u_cpu/btb/btb_pc_reg[13][26] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk + SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C + clock pessimism -0.418 27.955 + clock uncertainty -0.074 27.881 + SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.958 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] ------------------------------------------------------------------- - required time 27.631 - arrival time -24.148 + required time 27.958 + arrival time -24.910 ------------------------------------------------------------------- - slack 3.482 + slack 3.048 + +Slack (MET) : 3.062ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.163ns (logic 7.157ns (26.349%) route 20.006ns (73.651%)) + Logic Levels: 32 (CARRY4=6 LUT3=1 LUT4=3 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.055ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.862ns = ( 28.461 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.892 21.883 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X38Y24 LUT6 (Prop_lut6_I2_O) 0.124 22.007 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_9/O + net (fo=32, routed) 1.164 23.172 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_1 + SLICE_X29Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.296 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_13/O + net (fo=1, routed) 0.424 23.720 u_cpu/id_stage/ds_to_es_bus_r[187]_i_13_n_0 + SLICE_X31Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.844 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_6/O + net (fo=1, routed) 0.970 24.814 u_cpu/id_stage/ds_to_es_bus_r[187]_i_6_n_0 + SLICE_X38Y27 LUT6 (Prop_lut6_I5_O) 0.124 24.938 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O + net (fo=1, routed) 0.000 24.938 u_cpu/exe_stage/ds_to_es_bus[137] + SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.967 28.461 u_cpu/exe_stage/cpu_clk + SLICE_X38Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C + clock pessimism -0.418 28.043 + clock uncertainty -0.074 27.969 + SLICE_X38Y27 FDRE (Setup_fdre_C_D) 0.031 28.000 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] + ------------------------------------------------------------------- + required time 28.000 + arrival time -24.938 + ------------------------------------------------------------------- + slack 3.062 + +Slack (MET) : 3.068ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 27.117ns (logic 7.374ns (27.193%) route 19.743ns (72.807%)) + Logic Levels: 32 (CARRY4=6 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.929 9.806 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[17] + SLICE_X43Y46 LUT6 (Prop_lut6_I4_O) 0.124 9.930 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13/O + net (fo=1, routed) 0.000 9.930 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[1]_i_13_n_0 + SLICE_X43Y46 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 10.480 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7/CO[3] + net (fo=1, routed) 0.000 10.480 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_7_n_0 + SLICE_X43Y47 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 10.708 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[1]_i_5/CO[2] + net (fo=5, routed) 1.662 12.370 u_cpu/dcache/tagv_ram_way[1].u/write_buffer_way_reg[1][0] + SLICE_X25Y30 LUT3 (Prop_lut3_I0_O) 0.339 12.709 r u_cpu/dcache/tagv_ram_way[1].u/ms_to_ws_bus_r[46]_i_11/O + net (fo=32, routed) 0.572 13.281 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[47]_i_4 + SLICE_X24Y30 LUT6 (Prop_lut6_I5_O) 0.326 13.607 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[43]_i_4/O + net (fo=3, routed) 0.781 14.388 u_cpu/mem_stage/ms_to_ws_bus_r[47]_i_2_0[10] + SLICE_X23Y23 LUT5 (Prop_lut5_I1_O) 0.124 14.512 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35/O + net (fo=1, routed) 0.873 15.386 u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_35_n_0 + SLICE_X24Y18 LUT6 (Prop_lut6_I0_O) 0.124 15.510 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_14/O + net (fo=1, routed) 0.430 15.940 u_cpu/u_div/ms_to_ws_bus_r_reg[35] + SLICE_X24Y17 LUT5 (Prop_lut5_I4_O) 0.124 16.064 r u_cpu/u_div/ms_to_ws_bus_r[35]_i_4/O + net (fo=1, routed) 0.412 16.476 u_cpu/mem_stage/ms_to_ws_bus_r_reg[35]_0 + SLICE_X26Y17 LUT6 (Prop_lut6_I5_O) 0.124 16.600 r u_cpu/mem_stage/ms_to_ws_bus_r[35]_i_1/O + net (fo=4, routed) 0.482 17.081 u_cpu/id_stage/ms_to_ds_forward_bus[3] + SLICE_X29Y17 LUT5 (Prop_lut5_I2_O) 0.124 17.205 r u_cpu/id_stage/ds_to_es_bus_r[173]_i_20/O + net (fo=1, routed) 0.000 17.205 u_cpu/id_stage/ds_to_es_bus_r[173]_i_20_n_0 + SLICE_X29Y17 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 17.737 r u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9/CO[3] + net (fo=1, routed) 0.000 17.737 u_cpu/id_stage/ds_to_es_bus_r_reg[173]_i_9_n_0 + SLICE_X29Y18 CARRY4 (Prop_carry4_CI_O[3]) + 0.313 18.050 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/O[3] + net (fo=1, routed) 0.563 18.613 u_cpu/id_stage/rd_csr_addr0[10] + SLICE_X30Y19 LUT5 (Prop_lut5_I0_O) 0.306 18.919 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_58/O + net (fo=1, routed) 0.925 19.844 u_cpu/id_stage/ds_to_es_bus_r[193]_i_58_n_0 + SLICE_X38Y21 LUT5 (Prop_lut5_I0_O) 0.124 19.968 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O + net (fo=3, routed) 0.308 20.276 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 + SLICE_X41Y22 LUT4 (Prop_lut4_I3_O) 0.124 20.400 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O + net (fo=7, routed) 0.468 20.868 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 + SLICE_X40Y20 LUT6 (Prop_lut6_I5_O) 0.124 20.992 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O + net (fo=19, routed) 0.517 21.508 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 + SLICE_X41Y21 LUT6 (Prop_lut6_I2_O) 0.124 21.632 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O + net (fo=20, routed) 0.893 22.525 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 + SLICE_X44Y24 LUT6 (Prop_lut6_I0_O) 0.124 22.649 f u_cpu/id_stage/ds_to_es_bus_r[173]_i_3/O + net (fo=22, routed) 0.750 23.399 u_cpu/u_csr/ds_to_es_bus_r_reg[172] + SLICE_X46Y25 LUT2 (Prop_lut2_I1_O) 0.117 23.516 r u_cpu/u_csr/ds_to_es_bus_r[172]_i_3/O + net (fo=1, routed) 1.028 24.544 u_cpu/id_stage/ds_to_es_bus_r_reg[172] + SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.348 24.892 r u_cpu/id_stage/ds_to_es_bus_r[172]_i_1/O + net (fo=1, routed) 0.000 24.892 u_cpu/exe_stage/ds_to_es_bus[122] + SLICE_X42Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.877 28.371 u_cpu/exe_stage/cpu_clk + SLICE_X42Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[172]/C + clock pessimism -0.418 27.953 + clock uncertainty -0.074 27.879 + SLICE_X42Y24 FDRE (Setup_fdre_C_D) 0.081 27.960 u_cpu/exe_stage/ds_to_es_bus_r_reg[172] + ------------------------------------------------------------------- + required time 27.960 + arrival time -24.892 + ------------------------------------------------------------------- + slack 3.068 + +Slack (MET) : 3.072ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/if_stage/fs_pc_reg[20]/D + (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.964ns (logic 5.209ns (19.318%) route 21.755ns (80.682%)) + Logic Levels: 25 (CARRY4=4 LUT3=2 LUT4=1 LUT5=1 LUT6=15 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.145ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.952ns = ( 28.371 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 f u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 r u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 r u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 r u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.415 13.799 u_cpu/mem_stage/data_data_ok + SLICE_X43Y30 LUT3 (Prop_lut3_I0_O) 0.124 13.923 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_15/O + net (fo=2, routed) 0.833 14.756 u_cpu/mem_stage/es_to_ms_bus_r_reg[70]_1 + SLICE_X48Y30 LUT6 (Prop_lut6_I0_O) 0.124 14.880 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_14/O + net (fo=1, routed) 0.651 15.532 u_cpu/mem_stage/ms_ready_go + SLICE_X48Y25 LUT6 (Prop_lut6_I4_O) 0.124 15.656 r u_cpu/mem_stage/flush_inst_req_buffer[1]_i_13/O + net (fo=3, routed) 0.483 16.139 u_cpu/id_stage/flush_inst_req_buffer[31]_i_6 + SLICE_X50Y25 LUT6 (Prop_lut6_I1_O) 0.124 16.263 r u_cpu/id_stage/flush_inst_req_buffer[1]_i_9/O + net (fo=32, routed) 3.828 20.091 u_cpu/if_stage/nextpc5 + SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.215 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_4/O + net (fo=1, routed) 0.280 20.495 u_cpu/if_stage/flush_inst_req_buffer[20]_i_4_n_0 + SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.619 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_2/O + net (fo=1, routed) 0.159 20.777 u_cpu/if_stage/flush_inst_req_buffer[20]_i_2_n_0 + SLICE_X114Y16 LUT6 (Prop_lut6_I2_O) 0.124 20.901 r u_cpu/if_stage/flush_inst_req_buffer[20]_i_1/O + net (fo=3, routed) 3.838 24.740 u_cpu/if_stage/D[20] + SLICE_X51Y24 FDSE r u_cpu/if_stage/fs_pc_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.877 28.371 u_cpu/if_stage/cpu_clk + SLICE_X51Y24 FDSE r u_cpu/if_stage/fs_pc_reg[20]/C + clock pessimism -0.418 27.953 + clock uncertainty -0.074 27.879 + SLICE_X51Y24 FDSE (Setup_fdse_C_D) -0.067 27.812 u_cpu/if_stage/fs_pc_reg[20] + ------------------------------------------------------------------- + required time 27.812 + arrival time -24.740 + ------------------------------------------------------------------- + slack 3.072 + +Slack (MET) : 3.074ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/btb_pc_reg[23][10]/CE + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.786ns (logic 5.581ns (20.835%) route 21.205ns (79.165%)) + Logic Levels: 28 (CARRY4=4 LUT3=1 LUT4=2 LUT5=5 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.183ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.918ns = ( 28.405 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 f u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.890 18.331 u_cpu/exe_stage/data_addr_ok + SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.124 18.455 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.503 18.958 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X44Y21 LUT6 (Prop_lut6_I2_O) 0.124 19.082 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 0.485 19.567 u_cpu/btb/btb_operate_en + SLICE_X45Y19 LUT5 (Prop_lut5_I3_O) 0.124 19.691 f u_cpu/btb/btb_counter[23][1]_i_4/O + net (fo=26, routed) 3.899 23.590 u_cpu/btb/btb_counter[23][1]_i_4_n_0 + SLICE_X114Y6 LUT4 (Prop_lut4_I0_O) 0.124 23.714 r u_cpu/btb/btb_pc[23][29]_i_1/O + net (fo=30, routed) 0.848 24.562 u_cpu/btb/btb_pc[23][29]_i_1_n_0 + SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][10]/CE + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.911 28.405 u_cpu/btb/cpu_clk + SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][10]/C + clock pessimism -0.490 27.915 + clock uncertainty -0.074 27.841 + SLICE_X114Y12 FDRE (Setup_fdre_C_CE) -0.205 27.636 u_cpu/btb/btb_pc_reg[23][10] + ------------------------------------------------------------------- + required time 27.636 + arrival time -24.562 + ------------------------------------------------------------------- + slack 3.074 + +Slack (MET) : 3.074ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/btb_pc_reg[23][13]/CE + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.786ns (logic 5.581ns (20.835%) route 21.205ns (79.165%)) + Logic Levels: 28 (CARRY4=4 LUT3=1 LUT4=2 LUT5=5 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.183ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.918ns = ( 28.405 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 f u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.890 18.331 u_cpu/exe_stage/data_addr_ok + SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.124 18.455 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.503 18.958 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X44Y21 LUT6 (Prop_lut6_I2_O) 0.124 19.082 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 0.485 19.567 u_cpu/btb/btb_operate_en + SLICE_X45Y19 LUT5 (Prop_lut5_I3_O) 0.124 19.691 f u_cpu/btb/btb_counter[23][1]_i_4/O + net (fo=26, routed) 3.899 23.590 u_cpu/btb/btb_counter[23][1]_i_4_n_0 + SLICE_X114Y6 LUT4 (Prop_lut4_I0_O) 0.124 23.714 r u_cpu/btb/btb_pc[23][29]_i_1/O + net (fo=30, routed) 0.848 24.562 u_cpu/btb/btb_pc[23][29]_i_1_n_0 + SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][13]/CE + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.911 28.405 u_cpu/btb/cpu_clk + SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][13]/C + clock pessimism -0.490 27.915 + clock uncertainty -0.074 27.841 + SLICE_X114Y12 FDRE (Setup_fdre_C_CE) -0.205 27.636 u_cpu/btb/btb_pc_reg[23][13] + ------------------------------------------------------------------- + required time 27.636 + arrival time -24.562 + ------------------------------------------------------------------- + slack 3.074 + +Slack (MET) : 3.074ns (required time - arrival time) + Source: u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/btb_pc_reg[23][1]/CE + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 26.786ns (logic 5.581ns (20.835%) route 21.205ns (79.165%)) + Logic Levels: 28 (CARRY4=4 LUT3=1 LUT4=2 LUT5=5 LUT6=14 MUXF7=1 MUXF8=1) + Clock Path Skew: -0.183ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.918ns = ( 28.405 - 30.323 ) + Source Clock Delay (SCD): -2.225ns + Clock Pessimism Removal (CPR): -0.490ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_cpu/addr_trans/cpu_clk + SLICE_X35Y35 FDRE r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/C + ------------------------------------------------------------------- ------------------- + SLICE_X35Y35 FDRE (Prop_fdre_C_Q) 0.456 -1.769 r u_cpu/addr_trans/data_vaddr_buffer_reg[14]/Q + net (fo=33, routed) 1.442 -0.326 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer[2] + SLICE_X42Y40 LUT6 (Prop_lut6_I5_O) 0.124 -0.202 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226/O + net (fo=1, routed) 0.000 -0.202 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_226_n_0 + SLICE_X42Y40 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.513 0.311 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111/CO[3] + net (fo=1, routed) 0.000 0.311 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_111_n_0 + SLICE_X42Y41 CARRY4 (Prop_carry4_CI_CO[2]) + 0.229 0.540 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32/CO[2] + net (fo=1, routed) 1.009 1.549 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_32_n_1 + SLICE_X40Y47 LUT6 (Prop_lut6_I1_O) 0.310 1.859 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_9/O + net (fo=2, routed) 0.635 2.494 u_cpu/addr_trans/tlb_entry/match1[28] + SLICE_X38Y47 LUT4 (Prop_lut4_I2_O) 0.124 2.618 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O + net (fo=2, routed) 0.667 3.285 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 + SLICE_X39Y47 LUT5 (Prop_lut5_I0_O) 0.124 3.409 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O + net (fo=2, routed) 1.103 4.512 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 + SLICE_X38Y50 LUT6 (Prop_lut6_I0_O) 0.124 4.636 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O + net (fo=89, routed) 1.162 5.797 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] + SLICE_X42Y51 MUXF7 (Prop_muxf7_S_O) 0.292 6.089 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0/O + net (fo=1, routed) 0.000 6.089 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_38__0_n_0 + SLICE_X42Y51 MUXF8 (Prop_muxf8_I1_O) 0.088 6.177 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0/O + net (fo=1, routed) 0.957 7.134 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_16__0_n_0 + SLICE_X42Y50 LUT6 (Prop_lut6_I0_O) 0.319 7.453 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O + net (fo=1, routed) 0.435 7.888 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I5_O) 0.124 8.012 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O + net (fo=10, routed) 0.740 8.753 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 + SLICE_X44Y50 LUT6 (Prop_lut6_I3_O) 0.124 8.877 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[5]_i_1__0/O + net (fo=6, routed) 0.845 9.722 u_cpu/u_csr/ms_to_ws_bus[13] + SLICE_X50Y46 LUT6 (Prop_lut6_I3_O) 0.124 9.846 r u_cpu/u_csr/write_buffer_way[1]_i_18/O + net (fo=1, routed) 0.000 9.846 u_cpu/u_csr/write_buffer_way[1]_i_18_n_0 + SLICE_X50Y46 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 10.378 r u_cpu/u_csr/write_buffer_way_reg[1]_i_11/CO[3] + net (fo=1, routed) 0.000 10.378 u_cpu/u_csr/write_buffer_way_reg[1]_i_11_n_0 + SLICE_X50Y47 CARRY4 (Prop_carry4_CI_CO[1]) + 0.157 10.535 r u_cpu/u_csr/write_buffer_way_reg[1]_i_9/CO[1] + net (fo=2, routed) 0.791 11.326 u_cpu/wb_stage/CO[0] + SLICE_X46Y39 LUT6 (Prop_lut6_I1_O) 0.329 11.655 f u_cpu/wb_stage/write_buffer_way[1]_i_5/O + net (fo=7, routed) 0.762 12.417 u_cpu/addr_trans/tlb_entry/sc_cancel_req + SLICE_X46Y35 LUT3 (Prop_lut3_I1_O) 0.124 12.541 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O + net (fo=3, routed) 0.719 13.260 u_cpu/dcache/main_state_reg[0]_2 + SLICE_X43Y31 LUT6 (Prop_lut6_I3_O) 0.124 13.384 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O + net (fo=3, routed) 0.444 13.829 u_cpu/mem_stage/data_data_ok + SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 13.953 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O + net (fo=9, routed) 0.603 14.556 u_cpu/mem_stage/ms_allowin + SLICE_X42Y27 LUT6 (Prop_lut6_I2_O) 0.124 14.680 f u_cpu/mem_stage/request_buffer_icacop_i_2/O + net (fo=6, routed) 0.564 15.243 u_cpu/exe_stage/p_13_in + SLICE_X38Y27 LUT5 (Prop_lut5_I0_O) 0.124 15.367 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O + net (fo=6, routed) 0.519 15.886 u_cpu/exe_stage/dcacop_op_en + SLICE_X31Y27 LUT6 (Prop_lut6_I5_O) 0.124 16.010 r u_cpu/exe_stage/request_buffer_offset[3]_i_3/O + net (fo=4, routed) 0.767 16.777 u_cpu/exe_stage/main_idle2lookup + SLICE_X41Y28 LUT5 (Prop_lut5_I4_O) 0.124 16.901 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O + net (fo=2, routed) 0.416 17.317 u_cpu/dcache/tagv_ram_way[1].u/p_23_in + SLICE_X41Y27 LUT5 (Prop_lut5_I4_O) 0.124 17.441 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O + net (fo=11, routed) 0.890 18.331 u_cpu/exe_stage/data_addr_ok + SLICE_X42Y24 LUT6 (Prop_lut6_I2_O) 0.124 18.455 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O + net (fo=6, routed) 0.503 18.958 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 + SLICE_X44Y21 LUT6 (Prop_lut6_I2_O) 0.124 19.082 r u_cpu/exe_stage/btb_add_entry_r_i_3/O + net (fo=18, routed) 0.485 19.567 u_cpu/btb/btb_operate_en + SLICE_X45Y19 LUT5 (Prop_lut5_I3_O) 0.124 19.691 f u_cpu/btb/btb_counter[23][1]_i_4/O + net (fo=26, routed) 3.899 23.590 u_cpu/btb/btb_counter[23][1]_i_4_n_0 + SLICE_X114Y6 LUT4 (Prop_lut4_I0_O) 0.124 23.714 r u_cpu/btb/btb_pc[23][29]_i_1/O + net (fo=30, routed) 0.848 24.562 u_cpu/btb/btb_pc[23][29]_i_1_n_0 + SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][1]/CE + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.911 28.405 u_cpu/btb/cpu_clk + SLICE_X114Y12 FDRE r u_cpu/btb/btb_pc_reg[23][1]/C + clock pessimism -0.490 27.915 + clock uncertainty -0.074 27.841 + SLICE_X114Y12 FDRE (Setup_fdre_C_CE) -0.205 27.636 u_cpu/btb/btb_pc_reg[23][1] + ------------------------------------------------------------------- + required time 27.636 + arrival time -24.562 + ------------------------------------------------------------------- + slack 3.074 @@ -6491,3623 +6396,157 @@ Period(ns): 30.323 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y1 u_cpu/btb/btb_add_entry_index_r_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y3 u_cpu/btb/btb_add_entry_index_r_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X47Y0 u_cpu/btb/btb_add_entry_index_r_reg[2]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[3]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[4]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y6 u_cpu/btb/btb_add_entry_r_reg/C +Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[0]/C +Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[1]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 10.807ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.557ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.299ns (logic 0.704ns (2.488%) route 27.595ns (97.512%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.357 25.485 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[952]_i_1/O - net (fo=1, routed) 0.000 25.609 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_474 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.609 - ------------------------------------------------------------------- - slack 11.557 - -Slack (MET) : 11.686ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.168ns (logic 0.704ns (2.499%) route 27.464ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.100ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.227 25.355 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.479 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[955]_i_1/O - net (fo=1, routed) 0.000 25.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_477 - SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.545 37.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/C - clock pessimism -0.507 37.210 - clock uncertainty -0.077 37.134 - SLICE_X43Y132 FDCE (Setup_fdce_C_D) 0.031 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.479 - ------------------------------------------------------------------- - slack 11.686 - -Slack (MET) : 11.688ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.252ns (logic 0.704ns (2.492%) route 27.548ns (97.508%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.013ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.196ns = ( 37.804 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.311 25.438 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X41Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1020]_i_1/O - net (fo=1, routed) 0.000 25.562 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1186 - SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.632 37.804 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/C - clock pessimism -0.507 37.297 - clock uncertainty -0.077 37.221 - SLICE_X41Y133 FDCE (Setup_fdce_C_D) 0.029 37.250 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020] - ------------------------------------------------------------------- - required time 37.250 - arrival time -25.562 - ------------------------------------------------------------------- - slack 11.688 - -Slack (MET) : 11.690ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.161ns (logic 0.704ns (2.500%) route 27.457ns (97.500%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.220 25.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X47Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1016]_i_1/O - net (fo=1, routed) 0.000 25.471 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1182 - SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X47Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.471 - ------------------------------------------------------------------- - slack 11.690 - -Slack (MET) : 11.731ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.172ns (logic 0.704ns (2.499%) route 27.468ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.230 25.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.482 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1005]_i_1/O - net (fo=1, routed) 0.000 25.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1171 - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.482 - ------------------------------------------------------------------- - slack 11.731 - -Slack (MET) : 11.735ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.114ns (logic 0.704ns (2.504%) route 27.410ns (97.496%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.173 25.301 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.425 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[653]_i_1/O - net (fo=1, routed) 0.000 25.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_906 - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653] - ------------------------------------------------------------------- - required time 37.160 - arrival time -25.425 - ------------------------------------------------------------------- - slack 11.735 - -Slack (MET) : 11.764ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.140ns (logic 0.704ns (2.502%) route 27.436ns (97.498%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.198 25.326 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.450 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[880]_i_1/O - net (fo=1, routed) 0.000 25.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1117 - SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X44Y131 FDCE (Setup_fdce_C_D) 0.081 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.450 - ------------------------------------------------------------------- - slack 11.764 - -Slack (MET) : 11.777ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.166ns (logic 0.704ns (2.499%) route 27.462ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.012ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.225 25.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X41Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[968]_i_1/O - net (fo=1, routed) 0.000 25.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1142 - SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.633 37.805 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/C - clock pessimism -0.507 37.298 - clock uncertainty -0.077 37.222 - SLICE_X41Y134 FDCE (Setup_fdce_C_D) 0.031 37.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968] - ------------------------------------------------------------------- - required time 37.253 - arrival time -25.476 - ------------------------------------------------------------------- - slack 11.777 - -Slack (MET) : 11.846ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.007ns (logic 0.704ns (2.514%) route 27.303ns (97.486%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.066 25.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.318 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[825]_i_1/O - net (fo=1, routed) 0.000 25.318 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_468 - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.029 37.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825] - ------------------------------------------------------------------- - required time 37.164 - arrival time -25.318 - ------------------------------------------------------------------- - slack 11.846 - -Slack (MET) : 11.849ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.006ns (logic 0.704ns (2.514%) route 27.302ns (97.486%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.065 25.193 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.317 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[921]_i_1/O - net (fo=1, routed) 0.000 25.317 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1006 - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.317 - ------------------------------------------------------------------- - slack 11.849 - -Slack (MET) : 11.911ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.944ns (logic 0.704ns (2.519%) route 27.240ns (97.481%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.002 25.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.254 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[794]_i_1/O - net (fo=1, routed) 0.000 25.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1000 - SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X43Y134 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.254 - ------------------------------------------------------------------- - slack 11.911 - -Slack (MET) : 11.944ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.955ns (logic 0.704ns (2.518%) route 27.251ns (97.482%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.102ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.285ns = ( 37.715 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.013 25.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.265 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[941]_i_1/O - net (fo=1, routed) 0.000 25.265 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_335 - SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.543 37.715 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/C - clock pessimism -0.507 37.208 - clock uncertainty -0.077 37.132 - SLICE_X46Y130 FDCE (Setup_fdce_C_D) 0.077 37.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941] - ------------------------------------------------------------------- - required time 37.209 - arrival time -25.265 - ------------------------------------------------------------------- - slack 11.944 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.947ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.960ns (logic 0.704ns (2.518%) route 27.256ns (97.482%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.018 25.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1006]_i_1/O - net (fo=1, routed) 0.000 25.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1172 - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.270 - ------------------------------------------------------------------- - slack 11.947 - -Slack (MET) : 11.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[698]_i_1/O - net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_462 - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698] - ------------------------------------------------------------------- - required time 37.160 - arrival time -25.202 - ------------------------------------------------------------------- - slack 11.958 - -Slack (MET) : 11.960ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[996]_i_1/O - net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_785 - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.202 - ------------------------------------------------------------------- - slack 11.960 - -Slack (MET) : 11.962ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.889ns (logic 0.704ns (2.524%) route 27.185ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.948 25.076 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[997]_i_1/O - net (fo=1, routed) 0.000 25.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_786 - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.200 - ------------------------------------------------------------------- - slack 11.962 - -Slack (MET) : 11.975ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.867ns (logic 0.704ns (2.526%) route 27.163ns (97.474%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.110ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.293ns = ( 37.707 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.926 25.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X55Y125 LUT6 (Prop_lut6_I1_O) 0.124 25.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[713]_i_1/O - net (fo=1, routed) 0.000 25.178 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1029 - SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.535 37.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/C - clock pessimism -0.507 37.200 - clock uncertainty -0.077 37.124 - SLICE_X55Y125 FDCE (Setup_fdce_C_D) 0.029 37.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713] - ------------------------------------------------------------------- - required time 37.153 - arrival time -25.178 - ------------------------------------------------------------------- - slack 11.975 - -Slack (MET) : 12.001ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.895ns (logic 0.704ns (2.524%) route 27.191ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.104ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.287ns = ( 37.713 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.954 25.082 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X52Y128 LUT6 (Prop_lut6_I1_O) 0.124 25.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[714]_i_1/O - net (fo=1, routed) 0.000 25.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1030 - SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.541 37.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/C - clock pessimism -0.507 37.206 - clock uncertainty -0.077 37.130 - SLICE_X52Y128 FDCE (Setup_fdce_C_D) 0.077 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714] - ------------------------------------------------------------------- - required time 37.207 - arrival time -25.206 - ------------------------------------------------------------------- - slack 12.001 - -Slack (MET) : 12.017ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.835ns (logic 0.704ns (2.529%) route 27.131ns (97.471%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.894 25.021 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X53Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[701]_i_1/O - net (fo=1, routed) 0.000 25.145 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_465 - SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X53Y130 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.145 - ------------------------------------------------------------------- - slack 12.017 - -Slack (MET) : 12.030ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.884 25.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1002]_i_1/O - net (fo=1, routed) 0.000 25.136 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1168 - SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X43Y135 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.136 - ------------------------------------------------------------------- - slack 12.030 - -Slack (MET) : 12.046ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.810ns (logic 0.704ns (2.531%) route 27.106ns (97.469%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.869 24.997 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.121 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[781]_i_1/O - net (fo=1, routed) 0.000 25.121 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_913 - SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y136 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781] - ------------------------------------------------------------------- - required time 37.167 - arrival time -25.121 - ------------------------------------------------------------------- - slack 12.046 - -Slack (MET) : 12.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.885 25.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[712]_i_1/O - net (fo=1, routed) 0.000 25.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1028 - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/C - clock pessimism -0.507 37.202 - clock uncertainty -0.077 37.126 - SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.077 37.203 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712] - ------------------------------------------------------------------- - required time 37.203 - arrival time -25.137 - ------------------------------------------------------------------- - slack 12.066 - -Slack (MET) : 12.080ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.816ns (logic 0.704ns (2.531%) route 27.112ns (97.469%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.875 25.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.127 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[716]_i_1/O - net (fo=1, routed) 0.000 25.127 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1032 - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/C - clock pessimism -0.507 37.202 - clock uncertainty -0.077 37.126 - SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.081 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716] - ------------------------------------------------------------------- - required time 37.207 - arrival time -25.127 - ------------------------------------------------------------------- - slack 12.080 - -Slack (MET) : 12.098ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.803ns (logic 0.704ns (2.532%) route 27.099ns (97.468%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.862 24.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.114 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[920]_i_1/O - net (fo=1, routed) 0.000 25.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1005 - SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X42Y133 FDCE (Setup_fdce_C_D) 0.077 37.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920] - ------------------------------------------------------------------- - required time 37.212 - arrival time -25.114 - ------------------------------------------------------------------- - slack 12.098 - -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490] - ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 - ------------------------------------------------------------------- - slack 12.111 - -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491] - ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 - ------------------------------------------------------------------- - slack 12.111 - -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778] - ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 - ------------------------------------------------------------------- - slack 12.111 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: mlkem_clk_clk_pll -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I -Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C -Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK @@ -10115,7 +6554,7 @@ High Pulse Width Fast RAMD32/CLK n/a 1.250 20.00 From Clock: sys_clk To Clock: sys_clk -Setup : 0 Failing Endpoints, Worst Slack 0.167ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 0.146ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- @@ -10123,168 +6562,20 @@ PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Vio Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.146ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] + Destination: base_ram_be_n[3] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.529ns (logic 6.868ns (44.228%) route 8.661ns (55.772%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -10302,48 +6593,46 @@ Slack (MET) : 0.377ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.092 6.469 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.593 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[3]_inst_i_1/O + net (fo=1, routed) 3.064 9.657 base_ram_be_n_OBUF[3] + K25 OBUF (Prop_obuf_I_O) 3.551 13.208 r base_ram_be_n_OBUF[3]_inst/O + net (fo=0) 0.000 13.208 base_ram_be_n[3] + K25 r base_ram_be_n[3] (OUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -10358,115 +6647,238 @@ Slack (MET) : 0.377ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.977 + arrival time -13.208 ------------------------------------------------------------------- - slack 0.377 + slack 0.146 -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.243ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.438ns (logic 0.818ns (4.208%) route 18.620ns (95.792%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.620 16.589 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1066]_i_2_n_0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.238 16.951 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1066]_i_1/O + net (fo=1, routed) 0.000 16.951 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_51 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066]/C + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1066] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.951 + ------------------------------------------------------------------- + slack 0.243 + +Slack (MET) : 0.272ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.409ns (logic 0.792ns (4.081%) route 18.617ns (95.919%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.617 16.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.710 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2/O + net (fo=1, routed) 0.000 16.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1065]_i_2_n_0 + SLICE_X77Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.922 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1065]_i_1/O + net (fo=1, routed) 0.000 16.922 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_52 + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X77Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065]/C + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y144 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1065] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.922 + ------------------------------------------------------------------- + slack 0.272 + +Slack (MET) : 0.275ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.399ns (logic 6.859ns (44.544%) route 8.540ns (55.456%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.265 9.536 ext_ram_data_IOBUF[23]_inst/T + AA15 OBUFT (TriStatE_obuft_T_O) + 3.542 13.079 r ext_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.079 ext_ram_data[23] + AA15 r ext_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.079 + ------------------------------------------------------------------- + slack 0.275 + +Slack (MET) : 0.280ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) + Data Path Delay: 15.395ns (logic 6.881ns (44.698%) route 8.514ns (55.302%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -10484,30 +6896,46 @@ Slack (MET) : 0.424ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.132 9.510 base_ram_data_IOBUF[1]_inst/T + L25 OBUFT (TriStatE_obuft_T_O) + 3.564 13.074 r base_ram_data_IOBUF[1]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.074 base_ram_data[1] L25 r base_ram_data[1] (INOUT) ------------------------------------------------------------------- ------------------- @@ -10523,98 +6951,24 @@ Slack (MET) : 0.424ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.931 + arrival time -13.074 ------------------------------------------------------------------- - slack 0.424 + slack 0.280 -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.281ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] + Destination: ext_ram_data[21] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.394ns (logic 6.863ns (44.584%) route 8.531ns (55.416%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -10632,48 +6986,47 @@ Slack (MET) : 0.455ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.256 9.527 ext_ram_data_IOBUF[21]_inst/T + AC16 OBUFT (TriStatE_obuft_T_O) + 3.546 13.073 r ext_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.073 ext_ram_data[21] + AC16 r ext_ram_data[21] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -10688,189 +7041,24 @@ Slack (MET) : 0.455ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.899 + arrival time -13.073 ------------------------------------------------------------------- - slack 0.455 + slack 0.281 -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.287ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: base_ram_data[30] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.388ns (logic 6.876ns (44.688%) route 8.511ns (55.312%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -10888,47 +7076,46 @@ Slack (MET) : 0.555ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.130 9.508 base_ram_data_IOBUF[30]_inst/T M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] + 3.559 13.067 r base_ram_data_IOBUF[30]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.067 base_ram_data[30] M24 r base_ram_data[30] (INOUT) ------------------------------------------------------------------- ------------------- @@ -10944,24 +7131,24 @@ Slack (MET) : 0.555ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.799 + arrival time -13.067 ------------------------------------------------------------------- - slack 0.555 + slack 0.287 -Slack (MET) : 0.558ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.311ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[24] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.118ns (logic 6.871ns (45.448%) route 8.247ns (54.552%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.364ns (logic 6.875ns (44.747%) route 8.489ns (55.253%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -10979,47 +7166,46 @@ Slack (MET) : 0.558ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.444 9.239 ext_ram_data_IOBUF[24]_inst/T + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.214 9.485 ext_ram_data_IOBUF[24]_inst/T AD17 OBUFT (TriStatE_obuft_T_O) - 3.558 12.797 r ext_ram_data_IOBUF[24]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.797 ext_ram_data[24] + 3.558 13.043 r ext_ram_data_IOBUF[24]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.043 ext_ram_data[24] AD17 r ext_ram_data[24] (INOUT) ------------------------------------------------------------------- ------------------- @@ -11035,24 +7221,24 @@ Slack (MET) : 0.558ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.797 + arrival time -13.043 ------------------------------------------------------------------- - slack 0.558 + slack 0.311 -Slack (MET) : 0.584ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.324ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[17] + Destination: base_ram_be_n[1] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.092ns (logic 6.859ns (45.448%) route 8.233ns (54.552%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.350ns (logic 6.848ns (44.608%) route 8.503ns (55.392%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -11070,50 +7256,3119 @@ Slack (MET) : 0.584ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.694 9.224 base_ram_data_IOBUF[17]_inst/T + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 1.095 6.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X0Y77 LUT6 (Prop_lut6_I5_O) 0.124 6.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O + net (fo=1, routed) 2.903 9.499 base_ram_be_n_OBUF[1] + L22 OBUF (Prop_obuf_I_O) 3.531 13.030 r base_ram_be_n_OBUF[1]_inst/O + net (fo=0) 0.000 13.030 base_ram_be_n[1] + L22 r base_ram_be_n[1] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.030 + ------------------------------------------------------------------- + slack 0.324 + +Slack (MET) : 0.328ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.347ns (logic 6.853ns (44.657%) route 8.493ns (55.343%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.219 9.490 ext_ram_data_IOBUF[16]_inst/T + AB16 OBUFT (TriStatE_obuft_T_O) + 3.536 13.026 r ext_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.026 ext_ram_data[16] + AB16 r ext_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.026 + ------------------------------------------------------------------- + slack 0.328 + +Slack (MET) : 0.329ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.400ns (logic 0.789ns (4.067%) route 18.611ns (95.933%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.314ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.611 16.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.704 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2/O + net (fo=1, routed) 0.000 16.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[810]_i_2_n_0 + SLICE_X76Y142 MUXF7 (Prop_muxf7_I0_O) 0.209 16.913 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[810]_i_1/O + net (fo=1, routed) 0.000 16.913 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_307 + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.534 17.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X76Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810]/C + clock pessimism -0.507 17.199 + clock uncertainty -0.071 17.129 + SLICE_X76Y142 FDCE (Setup_fdce_C_D) 0.113 17.242 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[810] + ------------------------------------------------------------------- + required time 17.242 + arrival time -16.913 + ------------------------------------------------------------------- + slack 0.329 + +Slack (MET) : 0.332ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.340ns (logic 0.818ns (4.230%) route 18.522ns (95.770%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.522 16.492 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X79Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.616 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2/O + net (fo=1, routed) 0.000 16.616 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[940]_i_2_n_0 + SLICE_X79Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.854 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[940]_i_1/O + net (fo=1, routed) 0.000 16.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_177 + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.527 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X79Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940]/C + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X79Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[940] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.854 + ------------------------------------------------------------------- + slack 0.332 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.331ns (logic 6.877ns (44.857%) route 8.454ns (55.143%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[0]_inst/T + L24 OBUFT (TriStatE_obuft_T_O) + 3.560 13.010 r base_ram_data_IOBUF[0]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.010 base_ram_data[0] + L24 r base_ram_data[0] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.010 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.344ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.387ns (logic 0.821ns (4.235%) route 18.566ns (95.765%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.311ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.291ns = ( 17.709 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.566 16.535 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X74Y142 LUT4 (Prop_lut4_I2_O) 0.124 16.659 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[619]_i_2/O + net (fo=1, routed) 0.000 16.659 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[619]_i_2_n_0 + SLICE_X74Y142 MUXF7 (Prop_muxf7_I0_O) 0.241 16.900 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[619]_i_1/O + net (fo=1, routed) 0.000 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_498 + SLICE_X74Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.537 17.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X74Y142 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619]/C + clock pessimism -0.507 17.202 + clock uncertainty -0.071 17.132 + SLICE_X74Y142 FDCE (Setup_fdce_C_D) 0.113 17.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[619] + ------------------------------------------------------------------- + required time 17.245 + arrival time -16.900 + ------------------------------------------------------------------- + slack 0.344 + +Slack (MET) : 0.353ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[18] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.322ns (logic 6.859ns (44.764%) route 8.463ns (55.236%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.189 9.460 ext_ram_data_IOBUF[18]_inst/T + AB17 OBUFT (TriStatE_obuft_T_O) + 3.542 13.002 r ext_ram_data_IOBUF[18]_inst/OBUFT/O + net (fo=1, unset) 0.000 13.002 ext_ram_data[18] + AB17 r ext_ram_data[18] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -13.002 + ------------------------------------------------------------------- + slack 0.353 + +Slack (MET) : 0.357ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.324ns (logic 0.792ns (4.099%) route 18.532ns (95.901%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.532 16.501 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.625 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[520]_i_2/O + net (fo=1, routed) 0.000 16.625 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[520]_i_2_n_0 + SLICE_X77Y145 MUXF7 (Prop_muxf7_I0_O) 0.212 16.837 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[520]_i_1/O + net (fo=1, routed) 0.000 16.837 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_597 + SLICE_X77Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X77Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520]/C + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y145 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[520] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.837 + ------------------------------------------------------------------- + slack 0.357 + +Slack (MET) : 0.359ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[17] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.316ns (logic 6.863ns (44.810%) route 8.453ns (55.190%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.071 9.449 base_ram_data_IOBUF[17]_inst/T M21 OBUFT (TriStatE_obuft_T_O) - 3.546 12.770 r base_ram_data_IOBUF[17]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.770 base_ram_data[17] + 3.546 12.995 r base_ram_data_IOBUF[17]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.995 base_ram_data[17] M21 r base_ram_data[17] (INOUT) ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.995 + ------------------------------------------------------------------- + slack 0.359 + +Slack (MET) : 0.360ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[21] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.315ns (logic 6.861ns (44.798%) route 8.454ns (55.202%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.072 9.450 base_ram_data_IOBUF[21]_inst/T + M20 OBUFT (TriStatE_obuft_T_O) + 3.544 12.994 r base_ram_data_IOBUF[21]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.994 base_ram_data[21] + M20 r base_ram_data[21] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.994 + ------------------------------------------------------------------- + slack 0.360 + +Slack (MET) : 0.371ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.302ns (logic 0.792ns (4.103%) route 18.510ns (95.897%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.510 16.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X78Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.603 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[937]_i_2/O + net (fo=1, routed) 0.000 16.603 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[937]_i_2_n_0 + SLICE_X78Y145 MUXF7 (Prop_muxf7_I0_O) 0.212 16.815 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[937]_i_1/O + net (fo=1, routed) 0.000 16.815 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_180 + SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.527 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937]/C + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X78Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[937] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.815 + ------------------------------------------------------------------- + slack 0.371 + +Slack (MET) : 0.399ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[3] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.276ns (logic 6.887ns (45.082%) route 8.389ns (54.918%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.007 9.386 base_ram_data_IOBUF[3]_inst/T + M25 OBUFT (TriStatE_obuft_T_O) + 3.570 12.955 r base_ram_data_IOBUF[3]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.955 base_ram_data[3] + M25 r base_ram_data[3] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.955 + ------------------------------------------------------------------- + slack 0.399 + +Slack (MET) : 0.422ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[0] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.253ns (logic 6.848ns (44.897%) route 8.405ns (55.103%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 2.219 7.595 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] + SLICE_X5Y133 LUT6 (Prop_lut6_I5_O) 0.124 7.719 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O + net (fo=1, routed) 1.682 9.401 base_ram_be_n_OBUF[0] + L20 OBUF (Prop_obuf_I_O) 3.531 12.932 r base_ram_be_n_OBUF[0]_inst/O + net (fo=0) 0.000 12.932 base_ram_be_n[0] + L20 r base_ram_be_n[0] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.932 + ------------------------------------------------------------------- + slack 0.422 + +Slack (MET) : 0.427ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[22] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.248ns (logic 6.860ns (44.990%) route 8.388ns (55.010%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.113 9.384 ext_ram_data_IOBUF[22]_inst/T + Y15 OBUFT (TriStatE_obuft_T_O) + 3.543 12.927 r ext_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.927 ext_ram_data[22] + Y15 r ext_ram_data[22] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.927 + ------------------------------------------------------------------- + slack 0.427 + +Slack (MET) : 0.428ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.253ns (logic 0.792ns (4.114%) route 18.461ns (95.886%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.461 16.430 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X77Y143 LUT4 (Prop_lut4_I2_O) 0.124 16.554 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[617]_i_2/O + net (fo=1, routed) 0.000 16.554 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[617]_i_2_n_0 + SLICE_X77Y143 MUXF7 (Prop_muxf7_I0_O) 0.212 16.766 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[617]_i_1/O + net (fo=1, routed) 0.000 16.766 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_500 + SLICE_X77Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X77Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617]/C + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X77Y143 FDCE (Setup_fdce_C_D) 0.064 17.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[617] + ------------------------------------------------------------------- + required time 17.194 + arrival time -16.766 + ------------------------------------------------------------------- + slack 0.428 + +Slack (MET) : 0.429ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[16] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.245ns (logic 6.844ns (44.894%) route 8.401ns (55.106%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 3.019 9.398 base_ram_data_IOBUF[16]_inst/T + P21 OBUFT (TriStatE_obuft_T_O) + 3.527 12.925 r base_ram_data_IOBUF[16]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.925 base_ram_data[16] + P21 r base_ram_data[16] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.925 + ------------------------------------------------------------------- + slack 0.429 + +Slack (MET) : 0.432ns (required time - arrival time) + Source: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/crc_reg_reg[19]/D + (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.243ns (logic 5.206ns (27.054%) route 14.037ns (72.946%)) + Logic Levels: 18 (CARRY4=3 LUT2=2 LUT4=1 LUT5=6 LUT6=6) + Clock Path Skew: -0.284ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.180ns = ( 17.820 - 20.000 ) + Source Clock Delay (SCD): -2.403ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.939 -2.403 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk + SLICE_X24Y91 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X24Y91 FDRE (Prop_fdre_C_Q) 0.419 -1.984 r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[3]/Q + net (fo=1, routed) 0.845 -1.138 u_matmul_axi_slave/mult_inst[2].u_mult/Q[3] + SLICE_X22Y91 LUT2 (Prop_lut2_I1_O) 0.297 -0.841 r u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_28/O + net (fo=1, routed) 0.000 -0.841 u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_28_n_0 + SLICE_X22Y91 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 -0.465 r u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_22/CO[3] + net (fo=1, routed) 0.000 -0.465 u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_22_n_0 + SLICE_X22Y92 CARRY4 (Prop_carry4_CI_O[0]) + 0.219 -0.246 r u_matmul_axi_slave/mult_inst[2].u_mult/b1_c_reg_r1_0_15_0_5_i_27/O[0] + net (fo=1, routed) 1.005 0.758 u_matmul_axi_slave/calc_c_result0[4] + SLICE_X21Y90 LUT2 (Prop_lut2_I1_O) 0.295 1.053 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_17/O + net (fo=1, routed) 0.000 1.053 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_17_n_0 + SLICE_X21Y90 CARRY4 (Prop_carry4_S[0]_O[1]) + 0.424 1.477 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] + net (fo=8, routed) 0.827 2.304 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 + SLICE_X24Y92 LUT4 (Prop_lut4_I1_O) 0.298 2.602 r u_matmul_axi_slave/crc_reg[23]_i_43/O + net (fo=7, routed) 0.630 3.232 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 + SLICE_X24Y93 LUT5 (Prop_lut5_I1_O) 0.358 3.590 r u_matmul_axi_slave/crc_reg[27]_i_17/O + net (fo=10, routed) 0.892 4.482 u_matmul_axi_slave/crc32_word_next_return7[3] + SLICE_X27Y92 LUT6 (Prop_lut6_I1_O) 0.332 4.814 r u_matmul_axi_slave/crc_reg[23]_i_34/O + net (fo=10, routed) 1.132 5.946 u_matmul_axi_slave/crc32_word_next_return4[5] + SLICE_X30Y94 LUT5 (Prop_lut5_I2_O) 0.152 6.098 r u_matmul_axi_slave/crc_reg[27]_i_13/O + net (fo=11, routed) 0.848 6.946 u_matmul_axi_slave/crc32_word_next_return1[3] + SLICE_X27Y95 LUT6 (Prop_lut6_I3_O) 0.326 7.272 r u_matmul_axi_slave/crc_reg[12]_i_49/O + net (fo=9, routed) 0.681 7.953 u_matmul_axi_slave/crc32_word_next0_return10[4] + SLICE_X29Y96 LUT5 (Prop_lut5_I1_O) 0.152 8.105 r u_matmul_axi_slave/crc_reg[23]_i_21/O + net (fo=12, routed) 0.729 8.833 u_matmul_axi_slave/crc32_word_next0_return7[2] + SLICE_X30Y98 LUT6 (Prop_lut6_I3_O) 0.332 9.165 r u_matmul_axi_slave/crc_reg[12]_i_20/O + net (fo=11, routed) 1.049 10.214 u_matmul_axi_slave/crc32_word_next0_return4[3] + SLICE_X25Y95 LUT6 (Prop_lut6_I3_O) 0.124 10.338 r u_matmul_axi_slave/crc_reg[20]_i_20/O + net (fo=10, routed) 1.041 11.380 u_matmul_axi_slave/crc32_word_next0_return1[4] + SLICE_X24Y97 LUT5 (Prop_lut5_I2_O) 0.124 11.504 r u_matmul_axi_slave/crc_reg[12]_i_10/O + net (fo=10, routed) 0.872 12.375 u_matmul_axi_slave/crc_reg[12]_i_10_n_0 + SLICE_X20Y97 LUT6 (Prop_lut6_I5_O) 0.124 12.499 r u_matmul_axi_slave/crc_reg[31]_i_10/O + net (fo=14, routed) 1.275 13.775 u_matmul_axi_slave/crc32_word_next1_return7[7] + SLICE_X20Y103 LUT5 (Prop_lut5_I3_O) 0.150 13.925 r u_matmul_axi_slave/crc_reg[20]_i_3/O + net (fo=13, routed) 1.383 15.308 u_matmul_axi_slave/crc32_word_next1_return4[5] + SLICE_X22Y111 LUT5 (Prop_lut5_I4_O) 0.356 15.664 r u_matmul_axi_slave/crc_reg[19]_i_2/O + net (fo=1, routed) 0.828 16.492 u_matmul_axi_slave/crc32_word_next1_return3[25] + SLICE_X23Y111 LUT6 (Prop_lut6_I0_O) 0.348 16.840 r u_matmul_axi_slave/crc_reg[19]_i_1/O + net (fo=1, routed) 0.000 16.840 u_matmul_axi_slave/crc32_word_next1_return[19] + SLICE_X23Y111 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.648 17.820 u_matmul_axi_slave/sys_clk + SLICE_X23Y111 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/C + clock pessimism -0.507 17.313 + clock uncertainty -0.071 17.243 + SLICE_X23Y111 FDSE (Setup_fdse_C_D) 0.029 17.272 u_matmul_axi_slave/crc_reg_reg[19] + ------------------------------------------------------------------- + required time 17.272 + arrival time -16.840 + ------------------------------------------------------------------- + slack 0.432 + +Slack (MET) : 0.433ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.235ns (logic 0.792ns (4.118%) route 18.442ns (95.882%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.306ns = ( 17.694 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.442 16.412 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X82Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.536 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[682]_i_2/O + net (fo=1, routed) 0.000 16.536 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[682]_i_2_n_0 + SLICE_X82Y145 MUXF7 (Prop_muxf7_I0_O) 0.212 16.748 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[682]_i_1/O + net (fo=1, routed) 0.000 16.748 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_435 + SLICE_X82Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.522 17.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X82Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682]/C + clock pessimism -0.507 17.187 + clock uncertainty -0.071 17.117 + SLICE_X82Y145 FDCE (Setup_fdce_C_D) 0.064 17.181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[682] + ------------------------------------------------------------------- + required time 17.181 + arrival time -16.748 + ------------------------------------------------------------------- + slack 0.433 + +Slack (MET) : 0.444ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.252ns (logic 0.580ns (3.013%) route 18.672ns (96.987%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.312ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.292ns = ( 17.708 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.672 16.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X74Y139 LUT5 (Prop_lut5_I3_O) 0.124 16.766 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[989]_i_1/O + net (fo=1, routed) 0.000 16.766 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_128 + SLICE_X74Y139 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.536 17.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X74Y139 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989]/C + clock pessimism -0.507 17.201 + clock uncertainty -0.071 17.131 + SLICE_X74Y139 FDCE (Setup_fdce_C_D) 0.079 17.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[989] + ------------------------------------------------------------------- + required time 17.210 + arrival time -16.766 + ------------------------------------------------------------------- + slack 0.444 + +Slack (MET) : 0.446ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.284ns (logic 0.821ns (4.257%) route 18.463ns (95.742%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.463 16.432 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y143 LUT4 (Prop_lut4_I2_O) 0.124 16.556 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[812]_i_2/O + net (fo=1, routed) 0.000 16.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[812]_i_2_n_0 + SLICE_X76Y143 MUXF7 (Prop_muxf7_I0_O) 0.241 16.797 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[812]_i_1/O + net (fo=1, routed) 0.000 16.797 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_305 + SLICE_X76Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X76Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812]/C + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X76Y143 FDCE (Setup_fdce_C_D) 0.113 17.243 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[812] + ------------------------------------------------------------------- + required time 17.243 + arrival time -16.797 + ------------------------------------------------------------------- + slack 0.446 + +Slack (MET) : 0.453ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[25] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.222ns (logic 6.870ns (45.135%) route 8.352ns (54.865%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 3.077 9.348 ext_ram_data_IOBUF[25]_inst/T + AC17 OBUFT (TriStatE_obuft_T_O) + 3.553 12.902 r ext_ram_data_IOBUF[25]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.902 ext_ram_data[25] + AC17 r ext_ram_data[25] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.902 + ------------------------------------------------------------------- + slack 0.453 + +Slack (MET) : 0.495ns (required time - arrival time) + Source: u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg[5]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[23] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.281ns (logic 5.106ns (33.413%) route 10.175ns (66.586%)) + Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=1 LUT6=4 OBUFT=1 RAMD32=1) + Output Delay: 0.300ns + Clock Path Skew: -3.854ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.422ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.920 -2.422 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X25Y75 FDRE r u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X25Y75 FDRE (Prop_fdre_C_Q) 0.419 -2.003 r u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg[5]/Q + net (fo=3, routed) 0.821 -1.182 u_snix_axil_cdma_mux_8ch/ext_wr_word_addr_r_reg_n_0_[5] + SLICE_X25Y74 LUT4 (Prop_lut4_I3_O) 0.299 -0.883 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O + net (fo=4, routed) 1.108 0.226 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] + SLICE_X23Y75 LUT6 (Prop_lut6_I4_O) 0.124 0.350 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_2/O + net (fo=136, routed) 0.574 0.923 u_snix_axil_cdma_mux_8ch/ADDRA[2] + SLICE_X23Y75 LUT6 (Prop_lut6_I3_O) 0.124 1.047 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O + net (fo=167, routed) 1.350 2.397 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 + SLICE_X18Y74 RAMD32 (Prop_ramd32_RADR0_O) + 0.124 2.521 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC_D1/O + net (fo=1, routed) 0.947 3.468 u_snix_axil_cdma_mux_8ch/ep_rd_c1[23] + SLICE_X20Y78 LUT6 (Prop_lut6_I0_O) 0.124 3.592 r u_snix_axil_cdma_mux_8ch/stream_wdata[23]_i_4/O + net (fo=1, routed) 0.298 3.890 u_snix_axil_cdma_mux_8ch/stream_wdata[23]_i_4_n_0 + SLICE_X21Y76 LUT5 (Prop_lut5_I4_O) 0.124 4.014 r u_snix_axil_cdma_mux_8ch/stream_wdata[23]_i_3/O + net (fo=1, routed) 0.529 4.543 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/matmul_ep_rd_data[21] + SLICE_X24Y76 LUT6 (Prop_lut6_I0_O) 0.124 4.667 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/stream_wdata[23]_i_2/O + net (fo=3, routed) 1.225 5.892 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[23] + SLICE_X7Y73 LUT3 (Prop_lut3_I0_O) 0.124 6.016 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[23]_inst_i_1/O + net (fo=2, routed) 3.323 9.340 base_ram_data_IOBUF[23]_inst/I + N21 OBUFT (Prop_obuft_I_O) 3.520 12.859 r base_ram_data_IOBUF[23]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.859 base_ram_data[23] + N21 r base_ram_data[23] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.859 + ------------------------------------------------------------------- + slack 0.495 + +Slack (MET) : 0.499ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[31] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.176ns (logic 6.863ns (45.225%) route 8.313ns (54.775%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 2.931 9.309 base_ram_data_IOBUF[31]_inst/T + M22 OBUFT (TriStatE_obuft_T_O) + 3.546 12.855 r base_ram_data_IOBUF[31]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.855 base_ram_data[31] + M22 r base_ram_data[31] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.855 + ------------------------------------------------------------------- + slack 0.499 + +Slack (MET) : 0.518ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[28] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.157ns (logic 6.853ns (45.212%) route 8.304ns (54.788%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 2.922 9.301 base_ram_data_IOBUF[28]_inst/T + N22 OBUFT (TriStatE_obuft_T_O) + 3.536 12.837 r base_ram_data_IOBUF[28]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.837 base_ram_data[28] + N22 r base_ram_data[28] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.837 + ------------------------------------------------------------------- + slack 0.518 + +Slack (MET) : 0.530ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.200ns (logic 0.789ns (4.109%) route 18.411ns (95.891%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.313ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.293ns = ( 17.707 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.411 16.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X76Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.504 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1068]_i_2/O + net (fo=1, routed) 0.000 16.504 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1068]_i_2_n_0 + SLICE_X76Y144 MUXF7 (Prop_muxf7_I0_O) 0.209 16.713 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1068]_i_1/O + net (fo=1, routed) 0.000 16.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_49 + SLICE_X76Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.535 17.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X76Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068]/C + clock pessimism -0.507 17.200 + clock uncertainty -0.071 17.130 + SLICE_X76Y144 FDCE (Setup_fdce_C_D) 0.113 17.243 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1068] + ------------------------------------------------------------------- + required time 17.243 + arrival time -16.713 + ------------------------------------------------------------------- + slack 0.530 + +Slack (MET) : 0.532ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[20] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.143ns (logic 6.877ns (45.411%) route 8.267ns (54.589%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.992 9.263 ext_ram_data_IOBUF[20]_inst/T + AD18 OBUFT (TriStatE_obuft_T_O) + 3.560 12.823 r ext_ram_data_IOBUF[20]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.823 ext_ram_data[20] + AD18 r ext_ram_data[20] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.823 + ------------------------------------------------------------------- + slack 0.532 + +Slack (MET) : 0.544ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.189ns (logic 0.789ns (4.112%) route 18.400ns (95.888%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.310ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.290ns = ( 17.710 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.400 16.369 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X74Y143 LUT4 (Prop_lut4_I2_O) 0.124 16.493 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1084]_i_2/O + net (fo=1, routed) 0.000 16.493 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[1084]_i_2_n_0 + SLICE_X74Y143 MUXF7 (Prop_muxf7_I0_O) 0.209 16.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[1084]_i_1/O + net (fo=1, routed) 0.000 16.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_33 + SLICE_X74Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.538 17.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X74Y143 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084]/C + clock pessimism -0.507 17.203 + clock uncertainty -0.071 17.133 + SLICE_X74Y143 FDCE (Setup_fdce_C_D) 0.113 17.246 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[1084] + ------------------------------------------------------------------- + required time 17.246 + arrival time -16.702 + ------------------------------------------------------------------- + slack 0.544 + +Slack (MET) : 0.547ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[22] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.128ns (logic 6.869ns (45.407%) route 8.259ns (54.593%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 2.877 9.255 base_ram_data_IOBUF[22]_inst/T + N24 OBUFT (TriStatE_obuft_T_O) + 3.552 12.808 r base_ram_data_IOBUF[22]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.808 base_ram_data[22] + N24 r base_ram_data[22] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.808 + ------------------------------------------------------------------- + slack 0.547 + +Slack (MET) : 0.551ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[10] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.124ns (logic 6.900ns (45.622%) route 8.224ns (54.378%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.950 9.220 ext_ram_data_IOBUF[10]_inst/T + W26 OBUFT (TriStatE_obuft_T_O) + 3.583 12.803 r ext_ram_data_IOBUF[10]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.803 ext_ram_data[10] + W26 r ext_ram_data[10] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.803 + ------------------------------------------------------------------- + slack 0.551 + +Slack (MET) : 0.556ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[27] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.118ns (logic 6.840ns (45.240%) route 8.279ns (54.760%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 2.897 9.275 base_ram_data_IOBUF[27]_inst/T + P20 OBUFT (TriStatE_obuft_T_O) + 3.523 12.798 r base_ram_data_IOBUF[27]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.798 base_ram_data[27] + P20 r base_ram_data[27] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.798 + ------------------------------------------------------------------- + slack 0.556 + +Slack (MET) : 0.561ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[13] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.113ns (logic 6.896ns (45.630%) route 8.217ns (54.370%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.943 9.214 ext_ram_data_IOBUF[13]_inst/T + U25 OBUFT (TriStatE_obuft_T_O) + 3.579 12.793 r ext_ram_data_IOBUF[13]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.793 ext_ram_data[13] + U25 r ext_ram_data[13] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.793 + ------------------------------------------------------------------- + slack 0.561 + +Slack (MET) : 0.563ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_be_n[2] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.112ns (logic 6.852ns (45.343%) route 8.260ns (54.657%)) + Logic Levels: 14 (CARRY4=6 LUT4=2 LUT5=1 LUT6=4 OBUF=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 2.074 7.450 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] + SLICE_X5Y127 LUT6 (Prop_lut6_I5_O) 0.124 7.574 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O + net (fo=1, routed) 1.682 9.256 base_ram_be_n_OBUF[2] + L23 OBUF (Prop_obuf_I_O) 3.535 12.791 r base_ram_be_n_OBUF[2]_inst/O + net (fo=0) 0.000 12.791 base_ram_be_n[2] + L23 r base_ram_be_n[2] (OUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.791 + ------------------------------------------------------------------- + slack 0.563 + +Slack (MET) : 0.563ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[14] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.112ns (logic 6.897ns (45.638%) route 8.215ns (54.362%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.941 9.211 ext_ram_data_IOBUF[14]_inst/T + U26 OBUFT (TriStatE_obuft_T_O) + 3.580 12.791 r ext_ram_data_IOBUF[14]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.791 ext_ram_data[14] + U26 r ext_ram_data[14] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.791 + ------------------------------------------------------------------- + slack 0.563 + +Slack (MET) : 0.564ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[15] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.111ns (logic 6.875ns (45.500%) route 8.235ns (54.500%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.961 9.232 ext_ram_data_IOBUF[15]_inst/T + U24 OBUFT (TriStatE_obuft_T_O) + 3.558 12.790 r ext_ram_data_IOBUF[15]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.790 ext_ram_data[15] + U24 r ext_ram_data[15] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.790 + ------------------------------------------------------------------- + slack 0.564 + +Slack (MET) : 0.572ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[29] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.102ns (logic 6.880ns (45.554%) route 8.223ns (54.446%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.948 9.219 ext_ram_data_IOBUF[29]_inst/T + AC21 OBUFT (TriStatE_obuft_T_O) + 3.563 12.782 r ext_ram_data_IOBUF[29]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.782 ext_ram_data[29] + AC21 r ext_ram_data[29] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.782 + ------------------------------------------------------------------- + slack 0.572 + +Slack (MET) : 0.574ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.093ns (logic 0.792ns (4.148%) route 18.301ns (95.852%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.306ns = ( 17.694 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.301 16.271 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X82Y144 LUT4 (Prop_lut4_I2_O) 0.124 16.395 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[680]_i_2/O + net (fo=1, routed) 0.000 16.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[680]_i_2_n_0 + SLICE_X82Y144 MUXF7 (Prop_muxf7_I0_O) 0.212 16.607 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[680]_i_1/O + net (fo=1, routed) 0.000 16.607 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_437 + SLICE_X82Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.522 17.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X82Y144 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680]/C + clock pessimism -0.507 17.187 + clock uncertainty -0.071 17.117 + SLICE_X82Y144 FDCE (Setup_fdce_C_D) 0.064 17.181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[680] + ------------------------------------------------------------------- + required time 17.181 + arrival time -16.607 + ------------------------------------------------------------------- + slack 0.574 + +Slack (MET) : 0.576ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: ext_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.099ns (logic 6.874ns (45.528%) route 8.225ns (54.472%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.950 9.221 ext_ram_data_IOBUF[19]_inst/T + AC18 OBUFT (TriStatE_obuft_T_O) + 3.557 12.778 r ext_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.778 ext_ram_data[19] + AC18 r ext_ram_data[19] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.778 + ------------------------------------------------------------------- + slack 0.576 + +Slack (MET) : 0.582ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[29] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.093ns (logic 6.868ns (45.504%) route 8.225ns (54.496%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 2.843 9.221 base_ram_data_IOBUF[29]_inst/T + N23 OBUFT (TriStatE_obuft_T_O) + 3.551 12.772 r base_ram_data_IOBUF[29]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.772 base_ram_data[29] + N23 r base_ram_data[29] (INOUT) + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + clock pessimism -0.601 13.725 + clock uncertainty -0.071 13.654 + output delay -0.300 13.354 + ------------------------------------------------------------------- + required time 13.354 + arrival time -12.772 + ------------------------------------------------------------------- + slack 0.582 + +Slack (MET) : 0.585ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[19] + (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Max at Slow Process Corner + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 15.090ns (logic 6.835ns (45.291%) route 8.256ns (54.709%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) + Output Delay: 0.300ns + Clock Path Skew: -3.955ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) + Source Clock Delay (SCD): -2.321ns + Clock Pessimism Removal (CPR): -0.601ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 2.874 9.252 base_ram_data_IOBUF[19]_inst/T + P19 OBUFT (TriStatE_obuft_T_O) + 3.518 12.770 r base_ram_data_IOBUF[19]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.770 base_ram_data[19] + P19 r base_ram_data[19] (INOUT) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 20.000 20.000 r K21 0.000 20.000 r clk (IN) net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 @@ -11128,3026 +10383,22 @@ Slack (MET) : 0.584ns (required time - arrival time) required time 13.354 arrival time -12.770 ------------------------------------------------------------------- - slack 0.584 + slack 0.585 -Slack (MET) : 0.597ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[23] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.079ns (logic 6.848ns (45.415%) route 8.231ns (54.585%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.693 9.222 base_ram_data_IOBUF[23]_inst/T - N21 OBUFT (TriStatE_obuft_T_O) - 3.535 12.757 r base_ram_data_IOBUF[23]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.757 base_ram_data[23] - N21 r base_ram_data[23] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.757 - ------------------------------------------------------------------- - slack 0.597 - -Slack (MET) : 0.647ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[19] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.124ns (logic 5.128ns (33.905%) route 9.996ns (66.095%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.513 2.665 u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/ADDRB0 - SLICE_X36Y74 RAMD32 (Prop_ramd32_RADR0_O) - 0.124 2.789 r u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/RAMB_D1/O - net (fo=1, routed) 0.605 3.393 u_snix_axil_cdma_mux_8ch/ep_rd_c0[51] - SLICE_X34Y74 LUT6 (Prop_lut6_I1_O) 0.124 3.517 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_14__0/O - net (fo=2, routed) 0.775 4.293 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1_0 - SLICE_X30Y77 LUT5 (Prop_lut5_I3_O) 0.124 4.417 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_7__0/O - net (fo=2, routed) 1.453 5.869 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[19] - SLICE_X6Y79 LUT3 (Prop_lut3_I0_O) 0.124 5.993 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1/O - net (fo=2, routed) 3.172 9.165 ext_ram_data_IOBUF[19]_inst/I - AC18 OBUFT (Prop_obuft_I_O) 3.542 12.707 r ext_ram_data_IOBUF[19]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.707 ext_ram_data[19] - AC18 r ext_ram_data[19] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.707 - ------------------------------------------------------------------- - slack 0.647 - -Slack (MET) : 0.675ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[2] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.000ns (logic 6.848ns (45.654%) route 8.152ns (54.346%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 2.270 7.078 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] - SLICE_X11Y127 LUT6 (Prop_lut6_I5_O) 0.124 7.202 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O - net (fo=1, routed) 1.941 9.143 base_ram_be_n_OBUF[2] - L23 OBUF (Prop_obuf_I_O) 3.535 12.679 r base_ram_be_n_OBUF[2]_inst/O - net (fo=0) 0.000 12.679 base_ram_be_n[2] - L23 r base_ram_be_n[2] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.679 - ------------------------------------------------------------------- - slack 0.675 - -Slack (MET) : 0.680ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.996ns (logic 6.840ns (45.614%) route 8.156ns (54.386%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.617 9.147 base_ram_data_IOBUF[16]_inst/T - P21 OBUFT (TriStatE_obuft_T_O) - 3.527 12.674 r base_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.674 base_ram_data[16] - P21 r base_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.674 - ------------------------------------------------------------------- - slack 0.680 - -Slack (MET) : 0.681ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.090ns (logic 5.359ns (35.512%) route 9.732ns (64.488%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.167 9.136 base_ram_data_IOBUF[22]_inst/I - N24 OBUFT (Prop_obuft_I_O) 3.537 12.673 r base_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.673 base_ram_data[22] - N24 r base_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.673 - ------------------------------------------------------------------- - slack 0.681 - -Slack (MET) : 0.682ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.993ns (logic 6.873ns (45.840%) route 8.120ns (54.160%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.582 9.112 base_ram_data_IOBUF[0]_inst/T - L24 OBUFT (TriStatE_obuft_T_O) - 3.560 12.672 r base_ram_data_IOBUF[0]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.672 base_ram_data[0] - L24 r base_ram_data[0] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.672 - ------------------------------------------------------------------- - slack 0.682 - -Slack (MET) : 0.692ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[23] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.984ns (logic 6.855ns (45.753%) route 8.128ns (54.247%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.325 9.120 ext_ram_data_IOBUF[23]_inst/T - AA15 OBUFT (TriStatE_obuft_T_O) - 3.542 12.662 r ext_ram_data_IOBUF[23]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.662 ext_ram_data[23] - AA15 r ext_ram_data[23] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.662 - ------------------------------------------------------------------- - slack 0.692 - -Slack (MET) : 0.697ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[29] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.075ns (logic 5.121ns (33.974%) route 9.953ns (66.026%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 - SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O - net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] - SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O - net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 - SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O - net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 - SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O - net (fo=2, routed) 2.916 9.122 base_ram_data_IOBUF[29]_inst/I - N23 OBUFT (Prop_obuft_I_O) 3.535 12.657 r base_ram_data_IOBUF[29]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.657 base_ram_data[29] - N23 r base_ram_data[29] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.657 - ------------------------------------------------------------------- - slack 0.697 - -Slack (MET) : 0.700ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[3] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.976ns (logic 6.883ns (45.959%) route 8.093ns (54.041%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.555 9.084 base_ram_data_IOBUF[3]_inst/T - M25 OBUFT (TriStatE_obuft_T_O) - 3.570 12.654 r base_ram_data_IOBUF[3]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.654 base_ram_data[3] - M25 r base_ram_data[3] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.654 - ------------------------------------------------------------------- - slack 0.700 - -Slack (MET) : 0.717ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[31] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.959ns (logic 6.859ns (45.853%) route 8.100ns (54.147%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.562 9.091 base_ram_data_IOBUF[31]_inst/T - M22 OBUFT (TriStatE_obuft_T_O) - 3.546 12.638 r base_ram_data_IOBUF[31]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.638 base_ram_data[31] - M22 r base_ram_data[31] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.638 - ------------------------------------------------------------------- - slack 0.717 - -Slack (MET) : 0.724ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.048ns (logic 5.340ns (35.487%) route 9.708ns (64.513%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 2.954 9.128 base_ram_data_IOBUF[20]_inst/I - N19 OBUFT (Prop_obuft_I_O) 3.502 12.630 r base_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.630 base_ram_data[20] - N19 r base_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.630 - ------------------------------------------------------------------- - slack 0.724 - -Slack (MET) : 0.737ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.035ns (logic 5.349ns (35.580%) route 9.685ns (64.420%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 3.564 9.084 base_ram_data_IOBUF[18]_inst/I - P23 OBUFT (Prop_obuft_I_O) 3.533 12.617 r base_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.617 base_ram_data[18] - P23 r base_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.617 - ------------------------------------------------------------------- - slack 0.737 - -Slack (MET) : 0.793ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.978ns (logic 5.374ns (35.881%) route 9.604ns (64.119%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 2.870 9.008 ext_ram_data_IOBUF[28]_inst/I - AD21 OBUFT (Prop_obuft_I_O) 3.552 12.561 r ext_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.561 ext_ram_data[28] - AD21 r ext_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.561 - ------------------------------------------------------------------- - slack 0.793 - -Slack (MET) : 0.827ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[26] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.945ns (logic 5.374ns (35.959%) route 9.571ns (64.041%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 0.957 2.289 u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/ADDRC1 - SLICE_X36Y70 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.442 r u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/RAMC/O - net (fo=1, routed) 0.739 3.181 u_snix_axil_cdma_mux_8ch/ep_rd_c1[58] - SLICE_X39Y71 LUT6 (Prop_lut6_I0_O) 0.331 3.512 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_23__0/O - net (fo=1, routed) 0.706 4.218 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][26]_i_2_0 - SLICE_X35Y73 LUT4 (Prop_lut4_I2_O) 0.124 4.342 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_10__0/O - net (fo=6, routed) 1.406 5.748 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[26] - SLICE_X2Y73 LUT3 (Prop_lut3_I0_O) 0.124 5.872 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[26]_inst_i_1/O - net (fo=2, routed) 3.104 8.975 ext_ram_data_IOBUF[26]_inst/I - AD20 OBUFT (Prop_obuft_I_O) 3.552 12.527 r ext_ram_data_IOBUF[26]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.527 ext_ram_data[26] - AD20 r ext_ram_data[26] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.527 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.830ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[19] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.845ns (logic 6.831ns (46.012%) route 8.015ns (53.988%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.476 9.006 base_ram_data_IOBUF[19]_inst/T - P19 OBUFT (TriStatE_obuft_T_O) - 3.518 12.524 r base_ram_data_IOBUF[19]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.524 base_ram_data[19] - P19 r base_ram_data[19] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.524 - ------------------------------------------------------------------- - slack 0.830 - -Slack (MET) : 0.836ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[2]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.109ns (logic 5.382ns (28.164%) route 13.727ns (71.836%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT3=1 LUT4=4 LUT5=2 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 1.005 16.243 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X71Y60 LUT3 (Prop_lut3_I1_O) 0.331 16.574 r u_matmul_axi_slave/crc_reg[2]_i_1/O - net (fo=1, routed) 0.000 16.574 u_matmul_axi_slave/crc32_word_next1_return[2] - SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X71Y60 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[2] - ------------------------------------------------------------------- - required time 17.410 - arrival time -16.574 - ------------------------------------------------------------------- - slack 0.836 - -Slack (MET) : 0.845ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.830ns (logic 6.844ns (46.150%) route 7.986ns (53.850%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 1.799 6.608 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] - SLICE_X0Y112 LUT6 (Prop_lut6_I5_O) 0.124 6.732 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O - net (fo=1, routed) 2.246 8.977 base_ram_be_n_OBUF[0] - L20 OBUF (Prop_obuf_I_O) 3.531 12.509 r base_ram_be_n_OBUF[0]_inst/O - net (fo=0) 0.000 12.509 base_ram_be_n[0] - L20 r base_ram_be_n[0] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.509 - ------------------------------------------------------------------- - slack 0.845 - -Slack (MET) : 0.860ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[17] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.912ns (logic 5.126ns (34.375%) route 9.786ns (65.625%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.285 2.617 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 - SLICE_X40Y73 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.741 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/O - net (fo=1, routed) 0.600 3.341 u_snix_axil_cdma_mux_8ch/ep_rd_c1[49] - SLICE_X35Y74 LUT6 (Prop_lut6_I0_O) 0.124 3.465 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_12_17_i_6__0/O - net (fo=2, routed) 0.596 4.061 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1_0 - SLICE_X34Y73 LUT5 (Prop_lut5_I3_O) 0.124 4.185 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_12_17_i_3__0/O - net (fo=2, routed) 1.313 5.498 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[17] - SLICE_X8Y69 LUT3 (Prop_lut3_I0_O) 0.124 5.622 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1/O - net (fo=2, routed) 3.333 8.954 ext_ram_data_IOBUF[17]_inst/I - AC19 OBUFT (Prop_obuft_I_O) 3.540 12.494 r ext_ram_data_IOBUF[17]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.494 ext_ram_data[17] - AC19 r ext_ram_data[17] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.494 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.862ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[29] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.910ns (logic 5.133ns (34.429%) route 9.777ns (65.571%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 - SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O - net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] - SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O - net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 - SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O - net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 - SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O - net (fo=2, routed) 2.740 8.945 ext_ram_data_IOBUF[29]_inst/I - AC21 OBUFT (Prop_obuft_I_O) 3.547 12.492 r ext_ram_data_IOBUF[29]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.492 ext_ram_data[29] - AC21 r ext_ram_data[29] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.492 - ------------------------------------------------------------------- - slack 0.862 - -Slack (MET) : 0.870ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[19]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.071ns (logic 5.382ns (28.221%) route 13.689ns (71.779%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.018ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.967 16.204 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X71Y64 LUT6 (Prop_lut6_I3_O) 0.331 16.535 r u_matmul_axi_slave/crc_reg[19]_i_1/O - net (fo=1, routed) 0.000 16.535 u_matmul_axi_slave/crc32_word_next1_return[19] - SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.701 17.873 u_matmul_axi_slave/sys_clk - SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/C - clock pessimism -0.426 17.446 - clock uncertainty -0.071 17.376 - SLICE_X71Y64 FDSE (Setup_fdse_C_D) 0.029 17.405 u_matmul_axi_slave/crc_reg_reg[19] - ------------------------------------------------------------------- - required time 17.405 - arrival time -16.535 - ------------------------------------------------------------------- - slack 0.870 - -Slack (MET) : 0.875ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[27] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.896ns (logic 5.131ns (34.446%) route 9.765ns (65.554%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.268 2.600 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRB1 - SLICE_X36Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.724 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/O - net (fo=1, routed) 0.724 3.448 u_snix_axil_cdma_mux_8ch/ep_rd_c0[27] - SLICE_X34Y71 LUT6 (Prop_lut6_I1_O) 0.124 3.572 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_21__0/O - net (fo=1, routed) 0.977 4.549 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][27]_i_2_1 - SLICE_X23Y72 LUT4 (Prop_lut4_I3_O) 0.124 4.673 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_9__0/O - net (fo=6, routed) 1.188 5.861 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[27] - SLICE_X0Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.985 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[27]_inst_i_1/O - net (fo=2, routed) 2.949 8.934 ext_ram_data_IOBUF[27]_inst/I - AB21 OBUFT (Prop_obuft_I_O) 3.545 12.479 r ext_ram_data_IOBUF[27]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.479 ext_ram_data[27] - AB21 r ext_ram_data[27] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.479 - ------------------------------------------------------------------- - slack 0.875 - -Slack (MET) : 0.883ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.888ns (logic 5.398ns (36.257%) route 9.490ns (63.743%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.146 2.991 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O - net (fo=1, routed) 0.751 3.742 u_snix_axil_cdma_mux_8ch/ep_rd_c0[0] - SLICE_X34Y76 LUT6 (Prop_lut6_I1_O) 0.328 4.070 r u_snix_axil_cdma_mux_8ch/ram_reg_i_80/O - net (fo=1, routed) 0.416 4.485 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.609 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_48/O - net (fo=9, routed) 1.361 5.971 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.095 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O - net (fo=2, routed) 2.790 8.885 ext_ram_data_IOBUF[0]_inst/I - AF24 OBUFT (Prop_obuft_I_O) 3.586 12.471 r ext_ram_data_IOBUF[0]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.471 ext_ram_data[0] - AF24 r ext_ram_data[0] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.471 - ------------------------------------------------------------------- - slack 0.883 - -Slack (MET) : 0.890ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_addr[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.786ns (logic 6.749ns (45.642%) route 8.037ns (54.358%)) - Logic Levels: 13 (CARRY4=7 LUT4=1 LUT5=1 LUT6=3 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.925 4.220 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X0Y70 LUT6 (Prop_lut6_I5_O) 0.313 4.533 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2/O - net (fo=2, routed) 0.648 5.181 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2_n_0 - SLICE_X0Y71 LUT6 (Prop_lut6_I1_O) 0.124 5.305 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_1/O - net (fo=2, routed) 3.599 8.905 ext_ram_addr_OBUF[16] - AE17 OBUF (Prop_obuf_I_O) 3.560 12.464 r ext_ram_addr_OBUF[16]_inst/O - net (fo=0) 0.000 12.464 ext_ram_addr[16] - AE17 r ext_ram_addr[16] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.464 - ------------------------------------------------------------------- - slack 0.890 - -Slack (MET) : 0.905ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[18]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.087ns (logic 5.382ns (28.198%) route 13.705ns (71.802%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.983 16.220 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.551 r u_matmul_axi_slave/crc_reg[18]_i_1/O - net (fo=1, routed) 0.000 16.551 u_matmul_axi_slave/crc32_word_next1_return[18] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.077 17.456 u_matmul_axi_slave/crc_reg_reg[18] - ------------------------------------------------------------------- - required time 17.456 - arrival time -16.551 - ------------------------------------------------------------------- - slack 0.905 - -Slack (MET) : 0.911ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[25]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.085ns (logic 5.382ns (28.201%) route 13.703ns (71.799%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.981 16.218 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.549 r u_matmul_axi_slave/crc_reg[25]_i_1/O - net (fo=1, routed) 0.000 16.549 u_matmul_axi_slave/crc32_word_next1_return0[23] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.081 17.460 u_matmul_axi_slave/crc_reg_reg[25] - ------------------------------------------------------------------- - required time 17.460 - arrival time -16.549 - ------------------------------------------------------------------- - slack 0.911 - -Slack (MET) : 0.948ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.823ns (logic 5.154ns (34.770%) route 9.669ns (65.230%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 2.927 8.838 ext_ram_data_IOBUF[1]_inst/I - AE23 OBUFT (Prop_obuft_I_O) 3.568 12.406 r ext_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.406 ext_ram_data[1] - AE23 r ext_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.406 - ------------------------------------------------------------------- - slack 0.948 - -Slack (MET) : 0.949ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[26] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.726ns (logic 6.846ns (46.488%) route 7.880ns (53.512%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.342 8.872 base_ram_data_IOBUF[26]_inst/T - R21 OBUFT (TriStatE_obuft_T_O) - 3.533 12.405 r base_ram_data_IOBUF[26]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.405 base_ram_data[26] - R21 r base_ram_data[26] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.405 - ------------------------------------------------------------------- - slack 0.949 - -Slack (MET) : 0.959ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[13]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.035ns (logic 5.382ns (28.275%) route 13.653ns (71.725%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.931 16.168 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT4 (Prop_lut4_I1_O) 0.331 16.499 r u_matmul_axi_slave/crc_reg[13]_i_1/O - net (fo=1, routed) 0.000 16.499 u_matmul_axi_slave/crc32_word_next1_return[13] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.079 17.458 u_matmul_axi_slave/crc_reg_reg[13] - ------------------------------------------------------------------- - required time 17.458 - arrival time -16.499 - ------------------------------------------------------------------- - slack 0.959 - -Slack (MET) : 0.962ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[29]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.029ns (logic 5.382ns (28.283%) route 13.647ns (71.717%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) - Clock Path Skew: -0.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X70Y62 LUT5 (Prop_lut5_I4_O) 0.331 16.493 r u_matmul_axi_slave/crc_reg[29]_i_1/O - net (fo=1, routed) 0.000 16.493 u_matmul_axi_slave/crc32_word_next1_return0[27] - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/C - clock pessimism -0.426 17.447 - clock uncertainty -0.071 17.377 - SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.079 17.456 u_matmul_axi_slave/crc_reg_reg[29] - ------------------------------------------------------------------- - required time 17.456 - arrival time -16.493 - ------------------------------------------------------------------- - slack 0.962 - -Slack (MET) : 0.969ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[30]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.061ns (logic 5.414ns (28.404%) route 13.647ns (71.596%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) - Clock Path Skew: -0.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X70Y62 LUT4 (Prop_lut4_I3_O) 0.363 16.525 r u_matmul_axi_slave/crc_reg[30]_i_1/O - net (fo=1, routed) 0.000 16.525 u_matmul_axi_slave/crc32_word_next1_return0[28] - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/C - clock pessimism -0.426 17.447 - clock uncertainty -0.071 17.377 - SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.118 17.495 u_matmul_axi_slave/crc_reg_reg[30] - ------------------------------------------------------------------- - required time 17.495 - arrival time -16.525 - ------------------------------------------------------------------- - slack 0.969 - -Slack (MET) : 0.971ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[27]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 18.975ns (logic 5.382ns (28.364%) route 13.593ns (71.636%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.871 16.108 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X69Y63 LUT5 (Prop_lut5_I3_O) 0.331 16.439 r u_matmul_axi_slave/crc_reg[27]_i_1/O - net (fo=1, routed) 0.000 16.439 u_matmul_axi_slave/crc32_word_next1_return0[25] - SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X69Y63 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[27] - ------------------------------------------------------------------- - required time 17.410 - arrival time -16.439 - ------------------------------------------------------------------- - slack 0.971 - -Slack (MET) : 1.008ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[5] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.764ns (logic 5.026ns (34.045%) route 9.738ns (65.955%)) - Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O - net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] - SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O - net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 - SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O - net (fo=2, routed) 3.685 8.782 ext_ram_data_IOBUF[5]_inst/I - AE21 OBUFT (Prop_obuft_I_O) 3.564 12.347 r ext_ram_data_IOBUF[5]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.347 ext_ram_data[5] - AE21 r ext_ram_data[5] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.347 - ------------------------------------------------------------------- - slack 1.008 - -Slack (MET) : 1.012ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[27] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.664ns (logic 6.836ns (46.615%) route 7.828ns (53.385%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.290 8.820 base_ram_data_IOBUF[27]_inst/T - P20 OBUFT (TriStatE_obuft_T_O) - 3.523 12.342 r base_ram_data_IOBUF[27]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.342 base_ram_data[27] - P20 r base_ram_data[27] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.342 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.016ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[3] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.660ns (logic 6.906ns (47.111%) route 7.753ns (52.889%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.950 8.745 ext_ram_data_IOBUF[3]_inst/T - AE22 OBUFT (TriStatE_obuft_T_O) - 3.593 12.338 r ext_ram_data_IOBUF[3]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.338 ext_ram_data[3] - AE22 r ext_ram_data[3] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.338 - ------------------------------------------------------------------- - slack 1.016 - -Slack (MET) : 1.017ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.659ns (logic 6.844ns (46.685%) route 7.815ns (53.314%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 1.983 6.791 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] - SLICE_X0Y121 LUT6 (Prop_lut6_I5_O) 0.124 6.915 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O - net (fo=1, routed) 1.892 8.807 base_ram_be_n_OBUF[1] - L22 OBUF (Prop_obuf_I_O) 3.531 12.337 r base_ram_be_n_OBUF[1]_inst/O - net (fo=0) 0.000 12.337 base_ram_be_n[1] - L22 r base_ram_be_n[1] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.337 - ------------------------------------------------------------------- - slack 1.017 - -Slack (MET) : 1.017ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C +Slack (MET) : 0.585ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: ext_ram_data[4] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.659ns (logic 6.905ns (47.105%) route 7.754ns (52.895%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.090ns (logic 6.909ns (45.786%) route 8.181ns (54.214%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -14165,47 +10416,46 @@ Slack (MET) : 1.017ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.951 8.745 ext_ram_data_IOBUF[4]_inst/T + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.770 6.147 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y63 LUT3 (Prop_lut3_I2_O) 0.124 6.271 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O + net (fo=32, routed) 2.906 9.177 ext_ram_data_IOBUF[4]_inst/T AF22 OBUFT (TriStatE_obuft_T_O) - 3.592 12.337 r ext_ram_data_IOBUF[4]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.337 ext_ram_data[4] + 3.592 12.769 r ext_ram_data_IOBUF[4]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.769 ext_ram_data[4] AF22 r ext_ram_data[4] (INOUT) ------------------------------------------------------------------- ------------------- @@ -14221,96 +10471,86 @@ Slack (MET) : 1.017ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.337 + arrival time -12.769 ------------------------------------------------------------------- - slack 1.017 + slack 0.585 -Slack (MET) : 1.018ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C +Slack (MET) : 0.587ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[5] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.754ns (logic 5.001ns (33.893%) route 9.753ns (66.107%)) - Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O - net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] - SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O - net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 - SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O - net (fo=2, routed) 3.700 8.798 base_ram_data_IOBUF[5]_inst/I - P24 OBUFT (Prop_obuft_I_O) 3.539 12.336 r base_ram_data_IOBUF[5]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.336 base_ram_data[5] - P24 r base_ram_data[5] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.336 - ------------------------------------------------------------------- - slack 1.018 - -Slack (MET) : 1.019ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[30] + Path Group: sys_clk + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) + Data Path Delay: 19.085ns (logic 0.818ns (4.286%) route 18.267ns (95.714%)) + Logic Levels: 2 (LUT4=1 MUXF7=1) + Clock Path Skew: -0.321ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) + Source Clock Delay (SCD): -2.487ns + Clock Pessimism Removal (CPR): -0.507ns + Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.855 -2.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X123Y83 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X123Y83 FDRE (Prop_fdre_C_Q) 0.456 -2.031 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg/Q + net (fo=1088, routed) 18.267 16.237 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[902]_3 + SLICE_X78Y145 LUT4 (Prop_lut4_I2_O) 0.124 16.361 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[938]_i_2/O + net (fo=1, routed) 0.000 16.361 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r[938]_i_2_n_0 + SLICE_X78Y145 MUXF7 (Prop_muxf7_I0_O) 0.238 16.599 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/dj_block_r_reg[938]_i_1/O + net (fo=1, routed) 0.000 16.599 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram_n_179 + SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 20.000 20.000 r + K21 0.000 20.000 r clk (IN) + net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.527 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X78Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938]/C + clock pessimism -0.507 17.192 + clock uncertainty -0.071 17.122 + SLICE_X78Y145 FDCE (Setup_fdce_C_D) 0.064 17.186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[938] + ------------------------------------------------------------------- + required time 17.186 + arrival time -16.599 + ------------------------------------------------------------------- + slack 0.587 + +Slack (MET) : 0.596ns (required time - arrival time) + Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: base_ram_data[7] (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Max at Slow Process Corner Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.656ns (logic 6.857ns (46.787%) route 7.799ns (53.213%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) + Data Path Delay: 15.079ns (logic 6.877ns (45.604%) route 8.202ns (54.396%)) + Logic Levels: 14 (CARRY4=6 LUT3=1 LUT4=2 LUT5=1 LUT6=3 OBUFT=1) Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) + Clock Path Skew: -3.955ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns + Source Clock Delay (SCD): -2.321ns Clock Pessimism Removal (CPR): -0.601ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -14328,48 +10568,47 @@ Slack (MET) : 1.019ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C + net (fo=35652, routed) 2.021 -2.321 u_axi_ram/u_axi_sram_sp/sys_clk + SLICE_X7Y62 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.996 8.790 ext_ram_data_IOBUF[30]_inst/T - AA19 OBUFT (TriStatE_obuft_T_O) - 3.544 12.335 r ext_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.335 ext_ram_data[30] - AA19 r ext_ram_data[30] (INOUT) + SLICE_X7Y62 FDCE (Prop_fdce_C_Q) 0.456 -1.865 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[3]/Q + net (fo=54, routed) 0.726 -1.139 u_axi_ram/u_axi_sram_sp/len[3] + SLICE_X7Y61 LUT4 (Prop_lut4_I3_O) 0.124 -1.015 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O + net (fo=4, routed) 0.946 -0.068 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 + SLICE_X7Y58 LUT5 (Prop_lut5_I1_O) 0.124 0.056 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O + net (fo=2, routed) 0.619 0.675 u_axi_ram/u_axi_sram_sp/state_d2[7] + SLICE_X6Y59 LUT6 (Prop_lut6_I5_O) 0.124 0.799 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15/O + net (fo=1, routed) 0.000 0.799 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_15_n_0 + SLICE_X6Y59 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 1.175 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] + net (fo=1, routed) 0.000 1.175 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 + SLICE_X6Y60 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.292 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] + net (fo=1, routed) 0.000 1.292 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 + SLICE_X6Y61 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 1.409 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] + net (fo=1, routed) 0.000 1.409 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 + SLICE_X6Y62 CARRY4 (Prop_carry4_CI_O[2]) + 0.239 1.648 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/O[2] + net (fo=3, routed) 0.929 2.576 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[20] + SLICE_X5Y65 LUT4 (Prop_lut4_I2_O) 0.301 2.877 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7/O + net (fo=1, routed) 0.000 2.877 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_7_n_0 + SLICE_X5Y65 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.550 3.427 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1/CO[3] + net (fo=1, routed) 0.000 3.427 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_n_0 + SLICE_X5Y66 CARRY4 (Prop_carry4_CI_CO[2]) + 0.228 3.655 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2/CO[2] + net (fo=22, routed) 0.735 4.390 u_axi_ram/u_axi_sram_sp/req_addr_d1 + SLICE_X5Y68 LUT6 (Prop_lut6_I0_O) 0.313 4.703 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O + net (fo=2, routed) 0.550 5.253 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 + SLICE_X4Y68 LUT6 (Prop_lut6_I1_O) 0.124 5.377 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O + net (fo=80, routed) 0.877 6.254 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] + SLICE_X1Y74 LUT3 (Prop_lut3_I2_O) 0.124 6.378 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O + net (fo=32, routed) 2.821 9.199 base_ram_data_IOBUF[7]_inst/T + P25 OBUFT (TriStatE_obuft_T_O) + 3.560 12.758 r base_ram_data_IOBUF[7]_inst/OBUFT/O + net (fo=1, unset) 0.000 12.758 base_ram_data[7] + P25 r base_ram_data[7] (INOUT) ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -14384,9 +10623,9 @@ Slack (MET) : 1.019ns (required time - arrival time) output delay -0.300 13.354 ------------------------------------------------------------------- required time 13.354 - arrival time -12.335 + arrival time -12.758 ------------------------------------------------------------------- - slack 1.019 + slack 0.596 @@ -14400,6175 +10639,157 @@ Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y7 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[17]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[18]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[19]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y63 u_cdma_matmul_bridge/load_next_idx_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[20]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[21]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[22]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[23]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y69 u_cdma_matmul_bridge/load_next_idx_reg[24]/C +Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X141Y157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[105][11]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 14.363ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 14.363ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.986ns (logic 1.344ns (26.958%) route 3.642ns (73.042%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 3.642 22.469 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.260 36.832 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 36.832 - arrival time -22.469 - ------------------------------------------------------------------- - slack 14.363 - -Slack (MET) : 14.642ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.902ns (logic 1.317ns (26.864%) route 3.585ns (73.136%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.800 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 3.585 22.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[15] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.064 37.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 37.028 - arrival time -22.386 - ------------------------------------------------------------------- - slack 14.642 - -Slack (MET) : 14.889ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.419ns (logic 1.344ns (30.411%) route 3.075ns (69.589%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 3.075 21.905 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[18] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.299 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 36.794 - arrival time -21.905 - ------------------------------------------------------------------- - slack 14.889 - -Slack (MET) : 15.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.297ns (logic 1.336ns (31.089%) route 2.961ns (68.911%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 2.961 21.783 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[28] - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.252 36.842 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 36.842 - arrival time -21.783 - ------------------------------------------------------------------- - slack 15.059 - -Slack (MET) : 15.085ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.257ns (logic 1.344ns (31.570%) route 2.913ns (68.429%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 2.913 21.743 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.266 36.827 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 36.827 - arrival time -21.743 - ------------------------------------------------------------------- - slack 15.085 - -Slack (MET) : 15.131ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.202ns (logic 1.344ns (31.982%) route 2.858ns (68.018%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.511ns = ( 17.489 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.831 17.489 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/WCLK - SLICE_X56Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/O - net (fo=1, routed) 2.858 21.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[36] - SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X110Y71 FDRE (Setup_fdre_C_D) -0.271 36.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 36.823 - arrival time -21.692 - ------------------------------------------------------------------- - slack 15.131 - -Slack (MET) : 15.149ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.015ns (logic 1.344ns (33.474%) route 2.671ns (66.526%)) - Logic Levels: 0 - Clock Path Skew: -0.327ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 2.671 21.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[6] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.313 36.746 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.746 - arrival time -21.597 - ------------------------------------------------------------------- - slack 15.149 - -Slack (MET) : 15.187ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.166ns (logic 1.336ns (32.067%) route 2.830ns (67.933%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 2.830 21.652 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.254 36.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 36.839 - arrival time -21.652 - ------------------------------------------------------------------- - slack 15.187 - -Slack (MET) : 15.190ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.336ns (logic 1.314ns (30.303%) route 3.022ns (69.697%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 3.022 21.822 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.081 37.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 37.012 - arrival time -21.822 - ------------------------------------------------------------------- - slack 15.190 - -Slack (MET) : 15.238ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.936ns (logic 1.344ns (34.149%) route 2.592ns (65.851%)) - Logic Levels: 0 - Clock Path Skew: -0.321ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) - Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.924 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 2.592 21.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[0] - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.260 - clock uncertainty -0.197 37.063 - SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.309 36.754 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.754 - arrival time -21.516 - ------------------------------------------------------------------- - slack 15.238 - -Slack (MET) : 15.346ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.027ns (logic 1.336ns (33.179%) route 2.691ns (66.821%)) - Logic Levels: 0 - Clock Path Skew: -0.193ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 2.691 21.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[16] - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.238 36.856 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 36.856 - arrival time -21.510 - ------------------------------------------------------------------- - slack 15.346 - -Slack (MET) : 15.359ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.218ns (logic 1.317ns (31.224%) route 2.901ns (68.776%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.807 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 2.901 21.708 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[3] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.028 37.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 37.067 - arrival time -21.708 - ------------------------------------------------------------------- - slack 15.359 - -Slack (MET) : 15.360ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.008ns (logic 1.336ns (33.331%) route 2.672ns (66.669%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 2.672 21.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[4] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.237 36.858 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 36.858 - arrival time -21.499 - ------------------------------------------------------------------- - slack 15.360 - -Slack (MET) : 15.365ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.184ns (logic 1.309ns (31.283%) route 2.875ns (68.717%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.792 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 2.875 21.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.059 37.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 37.033 - arrival time -21.668 - ------------------------------------------------------------------- - slack 15.365 - -Slack (MET) : 15.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.144ns (logic 1.309ns (31.591%) route 2.835ns (68.409%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 2.835 21.629 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.093 37.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 37.000 - arrival time -21.629 - ------------------------------------------------------------------- - slack 15.371 - -Slack (MET) : 15.375ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.000ns (logic 1.309ns (32.724%) route 2.691ns (67.276%)) - Logic Levels: 0 - Clock Path Skew: -0.327ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 2.691 21.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.102 36.957 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 36.957 - arrival time -21.583 - ------------------------------------------------------------------- - slack 15.375 - -Slack (MET) : 15.382ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.988ns (logic 1.344ns (33.703%) route 2.644ns (66.297%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.834 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 2.644 21.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[0] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.860 - arrival time -21.478 - ------------------------------------------------------------------- - slack 15.382 - -Slack (MET) : 15.406ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.814ns (logic 1.344ns (35.240%) route 2.470ns (64.760%)) - Logic Levels: 0 - Clock Path Skew: -0.324ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 2.470 21.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.260 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.795 - arrival time -21.389 - ------------------------------------------------------------------- - slack 15.406 - -Slack (MET) : 15.426ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.896ns (logic 1.343ns (34.471%) route 2.553ns (65.529%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 2.553 21.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[14] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.287 36.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 36.805 - arrival time -21.379 - ------------------------------------------------------------------- - slack 15.426 - -Slack (MET) : 15.429ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.762ns (logic 1.343ns (35.695%) route 2.419ns (64.305%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 2.419 21.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[8] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.287 36.768 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 36.768 - arrival time -21.339 - ------------------------------------------------------------------- - slack 15.429 - -Slack (MET) : 15.440ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.128ns (logic 1.314ns (31.835%) route 2.814ns (68.165%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 2.814 21.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[29] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.040 37.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 37.053 - arrival time -21.613 - ------------------------------------------------------------------- - slack 15.440 - -Slack (MET) : 15.459ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.955ns (logic 1.317ns (33.302%) route 2.638ns (66.698%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.893 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/O - net (fo=1, routed) 2.638 21.531 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[9] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.065 36.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 36.990 - arrival time -21.531 - ------------------------------------------------------------------- - slack 15.459 - -Slack (MET) : 15.477ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.733ns (logic 1.336ns (35.784%) route 2.397ns (64.216%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.912 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 2.397 21.310 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[10] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.268 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 36.787 - arrival time -21.310 - ------------------------------------------------------------------- - slack 15.477 - -Slack (MET) : 15.480ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.063ns (logic 1.314ns (32.340%) route 2.749ns (67.660%)) - Logic Levels: 0 - Clock Path Skew: -0.194ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.797 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 2.749 21.547 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[17] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.067 37.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 37.026 - arrival time -21.547 - ------------------------------------------------------------------- - slack 15.480 - -Slack (MET) : 15.482ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.864ns (logic 1.344ns (34.786%) route 2.520ns (65.214%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 2.520 21.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.271 36.824 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 36.824 - arrival time -21.342 - ------------------------------------------------------------------- - slack 15.482 - -Slack (MET) : 15.506ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.864ns (logic 1.317ns (34.080%) route 2.547ns (65.920%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.900 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/O - net (fo=1, routed) 2.547 21.448 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[15] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.105 36.954 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 36.954 - arrival time -21.448 - ------------------------------------------------------------------- - slack 15.506 - -Slack (MET) : 15.550ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.822ns (logic 1.309ns (34.245%) route 2.513ns (65.755%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O - net (fo=1, routed) 2.513 21.406 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.103 36.956 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 36.956 - arrival time -21.406 - ------------------------------------------------------------------- - slack 15.550 - -Slack (MET) : 15.552ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.834ns (logic 1.309ns (34.141%) route 2.525ns (65.859%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.884 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 2.525 21.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.093 36.961 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 36.961 - arrival time -21.410 - ------------------------------------------------------------------- - slack 15.552 - -Slack (MET) : 15.552ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.012ns (logic 1.317ns (32.824%) route 2.695ns (67.176%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 2.695 21.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[27] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.043 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 37.050 - arrival time -21.498 - ------------------------------------------------------------------- - slack 15.552 - -Slack (MET) : 15.555ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.961ns (logic 1.317ns (33.248%) route 2.644ns (66.752%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 2.644 21.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.092 37.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 37.001 - arrival time -21.447 - ------------------------------------------------------------------- - slack 15.555 - -Slack (MET) : 15.555ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.607ns (logic 1.343ns (37.237%) route 2.264ns (62.763%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 2.264 21.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.317 36.737 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 36.737 - arrival time -21.182 - ------------------------------------------------------------------- - slack 15.555 - -Slack (MET) : 15.654ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.719ns (logic 1.309ns (35.195%) route 2.410ns (64.805%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.150ns = ( 37.850 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.885 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 2.410 21.296 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] - SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.678 37.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 37.249 - clock uncertainty -0.197 37.052 - SLICE_X78Y72 FDRE (Setup_fdre_C_D) -0.103 36.949 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 36.949 - arrival time -21.296 - ------------------------------------------------------------------- - slack 15.654 - -Slack (MET) : 15.659ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.762ns (logic 1.317ns (35.012%) route 2.445ns (64.988%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 2.445 21.337 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.058 36.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 36.996 - arrival time -21.337 - ------------------------------------------------------------------- - slack 15.659 - -Slack (MET) : 15.683ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.690ns (logic 1.309ns (35.473%) route 2.381ns (64.527%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) - Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 2.381 21.271 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[1] - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.253 - clock uncertainty -0.197 37.056 - SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.103 36.953 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 36.953 - arrival time -21.271 - ------------------------------------------------------------------- - slack 15.683 - -Slack (MET) : 15.729ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.413ns (logic 1.343ns (39.347%) route 2.070ns (60.653%)) - Logic Levels: 0 - Clock Path Skew: -0.330ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.925 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 2.070 20.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[8] - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 37.253 - clock uncertainty -0.197 37.056 - SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.332 36.724 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 36.724 - arrival time -20.996 - ------------------------------------------------------------------- - slack 15.729 - -Slack (MET) : 15.768ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.779ns (logic 1.309ns (34.643%) route 2.470ns (65.357%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 2.470 21.264 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.061 37.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25] - ------------------------------------------------------------------- - required time 37.032 - arrival time -21.264 - ------------------------------------------------------------------- - slack 15.768 - -Slack (MET) : 15.770ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.381ns (logic 1.343ns (39.723%) route 2.038ns (60.277%)) - Logic Levels: 0 - Clock Path Skew: -0.324ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 2.038 20.964 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[14] - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 37.260 - clock uncertainty -0.197 37.063 - SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.329 36.734 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 36.734 - arrival time -20.964 - ------------------------------------------------------------------- - slack 15.770 - -Slack (MET) : 15.794ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.497ns (logic 1.343ns (38.409%) route 2.154ns (61.591%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 2.154 20.982 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.317 36.776 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 36.776 - arrival time -20.982 - ------------------------------------------------------------------- - slack 15.794 - -Slack (MET) : 15.816ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.720ns (logic 1.309ns (35.188%) route 2.411ns (64.812%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.787 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 2.411 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.081 37.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time 37.014 - arrival time -21.198 - ------------------------------------------------------------------- - slack 15.816 - -Slack (MET) : 15.821ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.408ns (logic 1.336ns (39.197%) route 2.072ns (60.803%)) - Logic Levels: 0 - Clock Path Skew: -0.320ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.136ns = ( 37.864 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 2.072 20.991 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[10] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.692 37.864 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 37.263 - clock uncertainty -0.197 37.066 - SLICE_X76Y67 FDRE (Setup_fdre_C_D) -0.254 36.812 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 36.812 - arrival time -20.991 - ------------------------------------------------------------------- - slack 15.821 - -Slack (MET) : 15.826ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.590ns (logic 1.314ns (36.599%) route 2.276ns (63.401%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/O - net (fo=1, routed) 2.276 21.166 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[5] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.062 36.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 36.992 - arrival time -21.166 - ------------------------------------------------------------------- - slack 15.826 - -Slack (MET) : 15.830ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.395ns (logic 1.336ns (39.356%) route 2.059ns (60.644%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.911 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 2.059 20.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[4] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.254 36.800 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 36.800 - arrival time -20.970 - ------------------------------------------------------------------- - slack 15.830 - -Slack (MET) : 15.834ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.501ns (logic 1.343ns (38.357%) route 2.158ns (61.643%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 2.158 20.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[2] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.269 36.826 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 36.826 - arrival time -20.992 - ------------------------------------------------------------------- - slack 15.834 - -Slack (MET) : 15.836ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.395ns (logic 1.344ns (39.592%) route 2.051ns (60.408%)) - Logic Levels: 0 - Clock Path Skew: -0.326ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.920 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 2.051 20.971 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.247 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.807 - arrival time -20.971 - ------------------------------------------------------------------- - slack 15.836 - -Slack (MET) : 15.842ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.469ns (logic 1.344ns (38.739%) route 2.125ns (61.261%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.525ns = ( 17.475 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.475 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 2.125 20.945 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] - SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X114Y72 FDRE (Setup_fdre_C_D) -0.307 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.787 - arrival time -20.945 - ------------------------------------------------------------------- - slack 15.842 - -Slack (MET) : 15.908ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.473ns (logic 1.336ns (38.463%) route 2.137ns (61.537%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.814 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 2.137 20.952 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[34] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 36.860 - arrival time -20.952 - ------------------------------------------------------------------- - slack 15.908 - -Slack (MET) : 15.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.613ns (logic 1.317ns (36.447%) route 2.296ns (63.553%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.795 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 2.296 21.092 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[33] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.045 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 37.050 - arrival time -21.092 - ------------------------------------------------------------------- - slack 15.958 - -Slack (MET) : 15.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.633ns (logic 1.314ns (36.165%) route 2.319ns (63.835%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.804 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 2.319 21.124 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[5] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.013 37.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 37.082 - arrival time -21.124 - ------------------------------------------------------------------- - slack 15.958 - -Slack (MET) : 15.961ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.365ns (logic 1.343ns (39.913%) route 2.022ns (60.087%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 2.022 20.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[26] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.282 36.811 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 36.811 - arrival time -20.850 - ------------------------------------------------------------------- - slack 15.961 - -Slack (MET) : 15.990ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.572ns (logic 1.309ns (36.651%) route 2.263ns (63.349%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 2.263 21.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.043 37.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 37.052 - arrival time -21.062 - ------------------------------------------------------------------- - slack 15.990 - - - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 16.175ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 16.175ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.211ns (logic 1.343ns (41.819%) route 1.868ns (58.181%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 1.868 0.691 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.305 16.866 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 16.866 - arrival time -0.691 - ------------------------------------------------------------------- - slack 16.175 - -Slack (MET) : 16.288ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.133ns (logic 1.344ns (42.898%) route 1.789ns (57.102%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 1.789 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 16.900 - arrival time -0.612 - ------------------------------------------------------------------- - slack 16.288 - -Slack (MET) : 16.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.253ns (logic 1.309ns (40.244%) route 1.944ns (59.756%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 1.944 0.738 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.109 17.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 17.060 - arrival time -0.738 - ------------------------------------------------------------------- - slack 16.322 - -Slack (MET) : 16.382ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.989ns (logic 1.343ns (44.934%) route 1.646ns (55.066%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.173 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 1.646 0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.316 16.855 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 16.855 - arrival time -0.473 - ------------------------------------------------------------------- - slack 16.382 - -Slack (MET) : 16.446ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.152ns (logic 1.309ns (41.524%) route 1.843ns (58.476%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.212 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 1.843 0.632 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 17.078 - arrival time -0.632 - ------------------------------------------------------------------- - slack 16.446 - -Slack (MET) : 16.520ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.917ns (logic 1.336ns (45.800%) route 1.581ns (54.200%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 1.581 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.250 16.921 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 16.921 - arrival time -0.401 - ------------------------------------------------------------------- - slack 16.520 - -Slack (MET) : 16.587ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.822ns (logic 1.336ns (47.335%) route 1.486ns (52.665%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 1.486 0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.274 16.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 16.895 - arrival time -0.308 - ------------------------------------------------------------------- - slack 16.587 - -Slack (MET) : 16.599ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.995ns (logic 1.309ns (43.709%) route 1.686ns (56.291%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 1.686 0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 17.078 - arrival time -0.479 - ------------------------------------------------------------------- - slack 16.599 - -Slack (MET) : 16.680ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.736ns (logic 1.344ns (49.121%) route 1.392ns (50.879%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 1.392 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 16.900 - arrival time -0.221 - ------------------------------------------------------------------- - slack 16.680 - -Slack (MET) : 16.714ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.930ns (logic 1.314ns (44.850%) route 1.616ns (55.150%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 1.616 0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.043 17.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 17.128 - arrival time -0.414 - ------------------------------------------------------------------- - slack 16.714 - -Slack (MET) : 16.930ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.383ns (logic 1.343ns (56.369%) route 1.040ns (43.631%)) - Logic Levels: 0 - Clock Path Skew: -0.205ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 1.040 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.286 16.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 16.793 - arrival time 0.137 - ------------------------------------------------------------------- - slack 16.930 - -Slack (MET) : 16.970ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.472ns (logic 1.344ns (54.377%) route 1.128ns (45.623%)) - Logic Levels: 0 - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.171 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 1.128 -0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.244 16.927 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 16.927 - arrival time 0.043 - ------------------------------------------------------------------- - slack 16.970 - -Slack (MET) : 16.987ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.297ns (logic 1.343ns (58.459%) route 0.954ns (41.541%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.954 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.317 16.762 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 16.762 - arrival time 0.225 - ------------------------------------------------------------------- - slack 16.987 - -Slack (MET) : 16.991ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.542ns (logic 1.317ns (51.811%) route 1.225ns (48.189%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 1.225 0.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.061 17.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 17.119 - arrival time -0.128 - ------------------------------------------------------------------- - slack 16.991 - -Slack (MET) : 17.017ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.587ns (logic 1.317ns (50.909%) route 1.270ns (49.091%)) - Logic Levels: 0 - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.199 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 1.270 0.071 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.081 17.088 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 17.088 - arrival time -0.071 - ------------------------------------------------------------------- - slack 17.017 - -Slack (MET) : 17.045ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.595ns (logic 1.317ns (50.744%) route 1.278ns (49.256%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.198 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 1.278 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.043 17.126 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 17.126 - arrival time -0.081 - ------------------------------------------------------------------- - slack 17.045 - -Slack (MET) : 17.067ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.418ns (logic 0.456ns (18.857%) route 1.962ns (81.143%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.419ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.456 -1.963 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 1.962 -0.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X24Y73 FDCE (Setup_fdce_C_D) -0.105 17.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.067 - arrival time 0.000 - ------------------------------------------------------------------- - slack 17.067 - -Slack (MET) : 17.092ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.462ns (logic 1.314ns (53.376%) route 1.148ns (46.624%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 1.148 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.043 17.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 17.034 - arrival time 0.058 - ------------------------------------------------------------------- - slack 17.092 - -Slack (MET) : 17.095ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.436ns (logic 1.317ns (54.066%) route 1.119ns (45.934%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 1.119 0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.061 17.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time 17.122 - arrival time -0.027 - ------------------------------------------------------------------- - slack 17.095 - -Slack (MET) : 17.100ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.301ns (logic 1.343ns (58.359%) route 0.958ns (41.641%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.958 -0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.282 16.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 16.887 - arrival time 0.213 - ------------------------------------------------------------------- - slack 17.100 - -Slack (MET) : 17.150ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.212ns (logic 1.336ns (60.403%) route 0.876ns (39.597%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.876 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.238 16.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 16.839 - arrival time 0.311 - ------------------------------------------------------------------- - slack 17.150 - -Slack (MET) : 17.198ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.407ns (logic 1.314ns (54.587%) route 1.093ns (45.413%)) - Logic Levels: 0 - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.201 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 1.093 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.081 17.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 17.090 - arrival time 0.107 - ------------------------------------------------------------------- - slack 17.198 - -Slack (MET) : 17.220ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.336ns (logic 1.317ns (56.385%) route 1.019ns (43.615%)) - Logic Levels: 0 - Clock Path Skew: -0.205ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 1.019 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.043 17.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 17.036 - arrival time 0.184 - ------------------------------------------------------------------- - slack 17.220 - -Slack (MET) : 17.264ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.241ns (logic 1.314ns (58.629%) route 0.927ns (41.371%)) - Logic Levels: 0 - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.927 -0.279 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.093 16.984 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 16.984 - arrival time 0.279 - ------------------------------------------------------------------- - slack 17.264 - -Slack (MET) : 17.264ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.063ns (logic 1.336ns (64.747%) route 0.727ns (35.253%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.184 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.727 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.269 16.808 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 16.808 - arrival time 0.456 - ------------------------------------------------------------------- - slack 17.264 - -Slack (MET) : 17.267ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.053ns (logic 1.336ns (65.060%) route 0.717ns (34.940%)) - Logic Levels: 0 - Clock Path Skew: -0.218ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK - SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.717 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X28Y72 FDRE (Setup_fdre_C_D) -0.265 16.907 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 16.907 - arrival time 0.360 - ------------------------------------------------------------------- - slack 17.267 - -Slack (MET) : 17.269ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.055ns (logic 1.336ns (65.010%) route 0.719ns (34.990%)) - Logic Levels: 0 - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.719 -0.466 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.274 16.803 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 16.803 - arrival time 0.466 - ------------------------------------------------------------------- - slack 17.269 - -Slack (MET) : 17.276ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.013ns (logic 1.343ns (66.730%) route 0.670ns (33.270%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.071 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.670 -0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.305 16.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 16.875 - arrival time 0.401 - ------------------------------------------------------------------- - slack 17.276 - -Slack (MET) : 17.295ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.030ns (logic 0.419ns (20.636%) route 1.611ns (79.364%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.419 -1.981 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 1.611 -0.369 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.265 16.926 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 16.926 - arrival time 0.369 - ------------------------------------------------------------------- - slack 17.295 - -Slack (MET) : 17.298ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.211ns (logic 1.309ns (59.215%) route 0.902ns (40.785%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.902 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.093 16.986 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 16.986 - arrival time 0.312 - ------------------------------------------------------------------- - slack 17.298 - -Slack (MET) : 17.298ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.200ns (logic 0.456ns (20.732%) route 1.744ns (79.268%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) - Source Clock Delay (SCD): -2.416ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.926 -2.416 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.456 -1.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 1.744 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.372 - clock uncertainty -0.197 17.175 - SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.093 17.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.082 - arrival time 0.216 - ------------------------------------------------------------------- - slack 17.298 - -Slack (MET) : 17.351ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.004ns (logic 0.419ns (20.911%) route 1.585ns (79.089%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.419ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.419 -2.000 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 1.585 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X26Y73 FDCE (Setup_fdce_C_D) -0.236 16.936 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 16.936 - arrival time 0.415 - ------------------------------------------------------------------- - slack 17.351 - -Slack (MET) : 17.368ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.159ns (logic 1.309ns (60.638%) route 0.850ns (39.362%)) - Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.850 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.058 17.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time 17.113 - arrival time 0.255 - ------------------------------------------------------------------- - slack 17.368 - -Slack (MET) : 17.377ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 1.652 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.105 17.086 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.086 - arrival time 0.291 - ------------------------------------------------------------------- - slack 17.377 - -Slack (MET) : 17.380ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.944ns (logic 0.419ns (21.557%) route 1.525ns (78.443%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 17.891 - 20.000 ) - Source Clock Delay (SCD): -2.501ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.419 -2.082 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 1.525 -0.557 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.719 17.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.290 - clock uncertainty -0.197 17.093 - SLICE_X114Y76 FDCE (Setup_fdce_C_D) -0.270 16.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 16.823 - arrival time 0.557 - ------------------------------------------------------------------- - slack 17.380 - -Slack (MET) : 17.388ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) - Source Clock Delay (SCD): -2.417ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.925 -2.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.456 -1.961 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 1.652 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.372 - clock uncertainty -0.197 17.175 - SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.095 17.080 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.080 - arrival time 0.308 - ------------------------------------------------------------------- - slack 17.388 - -Slack (MET) : 17.399ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.106ns (logic 0.518ns (24.592%) route 1.588ns (75.408%)) - Logic Levels: 0 - Clock Path Skew: -0.203ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.096ns = ( 17.904 - 20.000 ) - Source Clock Delay (SCD): -2.495ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.518 -1.977 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q - net (fo=2, routed) 1.588 -0.388 u_fft_mlkem_axi_slave/mlkem_intr_m - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.732 17.904 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - clock pessimism -0.601 17.303 - clock uncertainty -0.197 17.106 - SLICE_X117Y61 FDCE (Setup_fdce_C_D) -0.095 17.011 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] - ------------------------------------------------------------------- - required time 17.011 - arrival time 0.388 - ------------------------------------------------------------------- - slack 17.399 - -Slack (MET) : 17.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.095ns (logic 0.456ns (21.761%) route 1.639ns (78.239%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.425ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.917 -2.425 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.969 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 1.639 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X30Y74 FDCE (Setup_fdce_C_D) -0.095 17.074 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.074 - arrival time 0.329 - ------------------------------------------------------------------- - slack 17.403 - -Slack (MET) : 17.408ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.088ns (logic 0.456ns (21.835%) route 1.632ns (78.165%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 1.632 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.389 - clock uncertainty -0.197 17.192 - SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.095 17.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.097 - arrival time 0.311 - ------------------------------------------------------------------- - slack 17.408 - -Slack (MET) : 17.411ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.087ns (logic 0.456ns (21.845%) route 1.631ns (78.155%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 1.631 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.601 17.389 - clock uncertainty -0.197 17.192 - SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.093 17.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 17.099 - arrival time 0.312 - ------------------------------------------------------------------- - slack 17.411 - -Slack (MET) : 17.415ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.084ns (logic 0.456ns (21.879%) route 1.628ns (78.121%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.423ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.919 -2.423 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.967 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 1.628 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X29Y74 FDCE (Setup_fdce_C_D) -0.093 17.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.076 - arrival time 0.338 - ------------------------------------------------------------------- - slack 17.415 - -Slack (MET) : 17.422ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.877ns (logic 1.344ns (71.587%) route 0.533ns (28.413%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.533 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.297 16.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 16.780 - arrival time 0.642 - ------------------------------------------------------------------- - slack 17.422 - -Slack (MET) : 17.426ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.860ns (logic 1.343ns (72.194%) route 0.517ns (27.806%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.517 -0.548 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.305 16.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 16.878 - arrival time 0.548 - ------------------------------------------------------------------- - slack 17.426 - -Slack (MET) : 17.461ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.860ns (logic 1.344ns (72.269%) route 0.516ns (27.731%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O - net (fo=1, routed) 0.516 -0.549 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.271 16.912 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 16.912 - arrival time 0.549 - ------------------------------------------------------------------- - slack 17.461 - -Slack (MET) : 17.463ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.069ns (logic 1.317ns (63.642%) route 0.752ns (36.358%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.752 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.067 17.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 17.012 - arrival time 0.451 - ------------------------------------------------------------------- - slack 17.463 - -Slack (MET) : 17.464ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.079ns (logic 1.317ns (63.334%) route 0.762ns (36.666%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.762 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.058 17.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 17.021 - arrival time 0.443 - ------------------------------------------------------------------- - slack 17.464 - -Slack (MET) : 17.494ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.834ns (logic 1.336ns (72.831%) route 0.498ns (27.169%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.498 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.265 16.915 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 16.915 - arrival time 0.579 - ------------------------------------------------------------------- - slack 17.494 - -Slack (MET) : 17.513ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.042ns (logic 1.314ns (64.342%) route 0.728ns (35.658%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.728 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.045 17.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 17.032 - arrival time 0.480 - ------------------------------------------------------------------- - slack 17.513 - -Slack (MET) : 17.526ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.999ns (logic 1.309ns (65.487%) route 0.690ns (34.513%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.100 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.690 -0.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X15Y78 FDRE (Setup_fdre_C_D) -0.067 17.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time 17.116 - arrival time 0.410 - ------------------------------------------------------------------- - slack 17.526 - -Slack (MET) : 17.534ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.826ns (logic 1.344ns (73.607%) route 0.482ns (26.393%)) - Logic Levels: 0 - Clock Path Skew: -0.209ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.130ns = ( 17.870 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.482 -0.697 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.698 17.870 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C - clock pessimism -0.601 17.269 - clock uncertainty -0.197 17.072 - SLICE_X62Y76 FDRE (Setup_fdre_C_D) -0.235 16.837 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 16.837 - arrival time 0.697 - ------------------------------------------------------------------- - slack 17.534 - - +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK @@ -20577,854 +10798,14 @@ Path Group: **async_default** From Clock: cpu_clk To Clock: cpu_clk -Setup : 0 Failing Endpoints, Worst Slack 25.793ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 26.490ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.837ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 27.371 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.837 - -Slack (MET) : 25.837ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 27.371 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.837 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.995ns (required time - arrival time) +Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR @@ -21432,12 +10813,12 @@ Slack (MET) : 25.995ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) + Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21453,15 +10834,15 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in + SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21472,19 +10853,19 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 + required time 27.595 + arrival time -1.105 ------------------------------------------------------------------- - slack 25.995 + slack 26.490 -Slack (MET) : 25.995ns (required time - arrival time) +Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR @@ -21492,12 +10873,12 @@ Slack (MET) : 25.995ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) + Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21513,15 +10894,15 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in + SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21532,19 +10913,19 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 + required time 27.595 + arrival time -1.105 ------------------------------------------------------------------- - slack 25.995 + slack 26.490 -Slack (MET) : 25.995ns (required time - arrival time) +Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR @@ -21552,12 +10933,12 @@ Slack (MET) : 25.995ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) + Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21573,15 +10954,15 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in + SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21592,19 +10973,19 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 + required time 27.595 + arrival time -1.105 ------------------------------------------------------------------- - slack 25.995 + slack 26.490 -Slack (MET) : 25.995ns (required time - arrival time) +Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR @@ -21612,12 +10993,12 @@ Slack (MET) : 25.995ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) + Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21633,15 +11014,15 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in + SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21652,19 +11033,19 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 + required time 27.595 + arrival time -1.105 ------------------------------------------------------------------- - slack 25.995 + slack 26.490 -Slack (MET) : 25.995ns (required time - arrival time) +Slack (MET) : 26.490ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR @@ -21672,12 +11053,12 @@ Slack (MET) : 25.995ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) + Data Path Delay: 3.236ns (logic 0.580ns (17.922%) route 2.656ns (82.078%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21693,15 +11074,15 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.769 1.105 u_Axi_CDC/arFifo/p_0_in + SLICE_X17Y47 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21712,19 +11093,199 @@ Slack (MET) : 25.995ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X17Y47 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 + required time 27.595 + arrival time -1.105 ------------------------------------------------------------------- - slack 25.995 + slack 26.490 -Slack (MET) : 26.032ns (required time - arrival time) +Slack (MET) : 26.685ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 27.638 + arrival time -0.953 + ------------------------------------------------------------------- + slack 26.685 + +Slack (MET) : 26.685ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 27.638 + arrival time -0.953 + ------------------------------------------------------------------- + slack 26.685 + +Slack (MET) : 26.685ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 27.638 + arrival time -0.953 + ------------------------------------------------------------------- + slack 26.685 + +Slack (MET) : 26.727ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR @@ -21732,12 +11293,12 @@ Slack (MET) : 26.032ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) + Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21753,15 +11314,15 @@ Slack (MET) : 26.032ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21772,19 +11333,19 @@ Slack (MET) : 26.032ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 + required time 27.680 + arrival time -0.953 ------------------------------------------------------------------- - slack 26.032 + slack 26.727 -Slack (MET) : 26.032ns (required time - arrival time) +Slack (MET) : 26.727ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR @@ -21792,12 +11353,12 @@ Slack (MET) : 26.032ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) + Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21813,15 +11374,15 @@ Slack (MET) : 26.032ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21832,19 +11393,19 @@ Slack (MET) : 26.032ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 + required time 27.680 + arrival time -0.953 ------------------------------------------------------------------- - slack 26.032 + slack 26.727 -Slack (MET) : 26.032ns (required time - arrival time) +Slack (MET) : 26.727ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR @@ -21852,12 +11413,12 @@ Slack (MET) : 26.032ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) + Data Path Delay: 3.085ns (logic 0.580ns (18.801%) route 2.505ns (81.199%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21873,15 +11434,15 @@ Slack (MET) : 26.032ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.617 0.953 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in + SLICE_X16Y45 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21892,32 +11453,32 @@ Slack (MET) : 26.032ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X16Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 + required time 27.680 + arrival time -0.953 ------------------------------------------------------------------- - slack 26.032 + slack 26.727 -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 26.870ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) + Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21933,15 +11494,15 @@ Slack (MET) : 26.072ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -21952,32 +11513,32 @@ Slack (MET) : 26.072ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 + required time 27.639 + arrival time -0.769 ------------------------------------------------------------------- - slack 26.072 + slack 26.870 -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 26.870ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) + Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -21993,15 +11554,15 @@ Slack (MET) : 26.072ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22012,32 +11573,32 @@ Slack (MET) : 26.072ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 + required time 27.639 + arrival time -0.769 ------------------------------------------------------------------- - slack 26.072 + slack 26.870 -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 26.870ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) + Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22053,15 +11614,15 @@ Slack (MET) : 26.072ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22072,32 +11633,32 @@ Slack (MET) : 26.072ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 + required time 27.639 + arrival time -0.769 ------------------------------------------------------------------- - slack 26.072 + slack 26.870 -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 26.912ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) + Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22113,15 +11674,15 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22132,32 +11693,32 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 + required time 27.681 + arrival time -0.769 ------------------------------------------------------------------- - slack 26.076 + slack 26.912 -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 26.912ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) + Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22173,15 +11734,15 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22192,32 +11753,32 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 + required time 27.681 + arrival time -0.769 ------------------------------------------------------------------- - slack 26.076 + slack 26.912 -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 26.912ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) + Data Path Delay: 2.901ns (logic 0.580ns (19.994%) route 2.321ns (80.006%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22233,15 +11794,15 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.433 0.769 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y45 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22252,32 +11813,32 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y45 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 + required time 27.681 + arrival time -0.769 ------------------------------------------------------------------- - slack 26.076 + slack 26.912 -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 27.000ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) + Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22293,15 +11854,15 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22312,32 +11873,32 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 + required time 27.594 + arrival time -0.594 ------------------------------------------------------------------- - slack 26.076 + slack 27.000 -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 27.000ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) + Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22353,15 +11914,15 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22372,32 +11933,32 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 + required time 27.594 + arrival time -0.594 ------------------------------------------------------------------- - slack 26.076 + slack 27.000 -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 27.000ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) + Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22413,15 +11974,15 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22432,32 +11993,32 @@ Slack (MET) : 26.076ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 + required time 27.594 + arrival time -0.594 ------------------------------------------------------------------- - slack 26.076 + slack 27.000 -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 27.000ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) + Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22473,15 +12034,15 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22492,32 +12053,32 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 + required time 27.594 + arrival time -0.594 ------------------------------------------------------------------- - slack 26.198 + slack 27.000 -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 27.000ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) + Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22533,15 +12094,15 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22552,32 +12113,32 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 + required time 27.594 + arrival time -0.594 ------------------------------------------------------------------- - slack 26.198 + slack 27.000 -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 27.000ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) + Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22593,15 +12154,15 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22612,32 +12173,32 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 + required time 27.594 + arrival time -0.594 ------------------------------------------------------------------- - slack 26.198 + slack 27.000 -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 27.000ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) + Data Path Delay: 2.726ns (logic 0.580ns (21.279%) route 2.146ns (78.721%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22653,15 +12214,15 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 1.258 0.594 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22672,139 +12233,19 @@ Slack (MET) : 26.198ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X13Y42 FDCE (Recov_fdce_C_CLR) -0.405 27.594 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 + required time 27.594 + arrival time -0.594 ------------------------------------------------------------------- - slack 26.198 + slack 27.000 -Slack (MET) : 26.255ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.216 - ------------------------------------------------------------------- - slack 26.255 - -Slack (MET) : 26.255ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.216 - ------------------------------------------------------------------- - slack 26.255 - -Slack (MET) : 26.639ns (required time - arrival time) +Slack (MET) : 27.162ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR @@ -22812,12 +12253,12 @@ Slack (MET) : 26.639ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.322ns (logic 0.718ns (21.614%) route 2.604ns (78.386%)) + Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22833,15 +12274,15 @@ Slack (MET) : 26.639ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.972 0.918 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22852,32 +12293,32 @@ Slack (MET) : 26.639ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X6Y74 FDCE (Recov_fdce_C_CLR) -0.319 27.557 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 27.557 - arrival time -0.918 + required time 27.639 + arrival time -0.477 ------------------------------------------------------------------- - slack 26.639 + slack 27.162 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 27.204ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22893,15 +12334,15 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22912,32 +12353,32 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 27.681 + arrival time -0.477 ------------------------------------------------------------------- - slack 27.242 + slack 27.204 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 27.204ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -22953,15 +12394,15 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -22972,32 +12413,32 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 27.681 + arrival time -0.477 ------------------------------------------------------------------- - slack 27.242 + slack 27.204 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 27.204ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Data Path Delay: 2.688ns (logic 0.718ns (26.710%) route 1.970ns (73.290%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23013,15 +12454,15 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 1.155 0.477 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23032,32 +12473,32 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X14Y43 FDCE (Recov_fdce_C_CLR) -0.319 27.681 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 27.681 + arrival time -0.477 ------------------------------------------------------------------- - slack 27.242 + slack 27.204 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23073,15 +12514,15 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23092,32 +12533,32 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.242 + slack 27.300 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23133,15 +12574,15 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23152,32 +12593,32 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.242 + slack 27.300 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23193,15 +12634,15 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23212,32 +12653,32 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.242 + slack 27.300 -Slack (MET) : 27.242ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23253,15 +12694,15 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23272,32 +12713,32 @@ Slack (MET) : 27.242ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.242 + slack 27.300 -Slack (MET) : 27.248ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23313,15 +12754,15 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23332,32 +12773,32 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.248 + slack 27.300 -Slack (MET) : 27.248ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23373,15 +12814,15 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23392,32 +12833,32 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.248 + slack 27.300 -Slack (MET) : 27.248ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23433,15 +12874,15 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23452,32 +12893,32 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.248 + slack 27.300 -Slack (MET) : 27.248ns (required time - arrival time) +Slack (MET) : 27.300ns (required time - arrival time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) + Data Path Delay: 2.506ns (logic 0.718ns (28.648%) route 1.788ns (71.352%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23493,15 +12934,15 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.973 0.295 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23512,19 +12953,379 @@ Slack (MET) : 27.248ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y44 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 + required time 27.595 + arrival time -0.295 ------------------------------------------------------------------- - slack 27.248 + slack 27.300 -Slack (MET) : 27.338ns (required time - arrival time) +Slack (MET) : 27.439ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 27.595 + arrival time -0.156 + ------------------------------------------------------------------- + slack 27.439 + +Slack (MET) : 27.439ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 27.595 + arrival time -0.156 + ------------------------------------------------------------------- + slack 27.439 + +Slack (MET) : 27.439ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 27.595 + arrival time -0.156 + ------------------------------------------------------------------- + slack 27.439 + +Slack (MET) : 27.439ns (required time - arrival time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.368ns (logic 0.718ns (30.323%) route 1.650ns (69.677%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.212ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.419 -1.793 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.815 -0.978 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.299 -0.679 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.835 0.156 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X13Y43 FDCE (Recov_fdce_C_CLR) -0.405 27.595 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 27.595 + arrival time -0.156 + ------------------------------------------------------------------- + slack 27.439 + +Slack (MET) : 27.470ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 27.638 + arrival time -0.168 + ------------------------------------------------------------------- + slack 27.470 + +Slack (MET) : 27.470ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 27.638 + arrival time -0.168 + ------------------------------------------------------------------- + slack 27.470 + +Slack (MET) : 27.470ns (required time - arrival time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR @@ -23532,12 +13333,12 @@ Slack (MET) : 27.338ns (required time - arrival time) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.252ns (logic 0.580ns (25.756%) route 1.672ns (74.244%)) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.298ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.928ns = ( 28.394 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.130ns @@ -23553,15 +13354,15 @@ Slack (MET) : 27.338ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.014 0.123 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 30.323 30.323 r @@ -23572,3531 +13373,437 @@ Slack (MET) : 27.338ns (required time - arrival time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.900 28.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.896 - clock uncertainty -0.074 27.822 - SLICE_X6Y50 FDCE (Recov_fdce_C_CLR) -0.361 27.461 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 27.461 - arrival time -0.123 + required time 27.638 + arrival time -0.168 ------------------------------------------------------------------- - slack 27.338 + slack 27.470 - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 23.497ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 23.497ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 27.470ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324] - ------------------------------------------------------------------- - required time 36.621 - arrival time -13.124 - ------------------------------------------------------------------- - slack 23.497 - -Slack (MET) : 23.497ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931] - ------------------------------------------------------------------- - required time 36.621 - arrival time -13.124 - ------------------------------------------------------------------- - slack 23.497 - -Slack (MET) : 23.954ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.155ns (logic 0.609ns (4.018%) route 14.546ns (95.982%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.295 12.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X38Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X38Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X38Y100 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293] - ------------------------------------------------------------------- - required time 36.621 - arrival time -12.667 - ------------------------------------------------------------------- - slack 23.954 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.267ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.442 - ------------------------------------------------------------------- - slack 24.267 - -Slack (MET) : 24.267ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.442 - ------------------------------------------------------------------- - slack 24.267 - -Slack (MET) : 24.272ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.272 - -Slack (MET) : 24.272ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.272 - -Slack (MET) : 24.284ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.564 36.840 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269] - ------------------------------------------------------------------- - required time 36.840 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.284 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.326ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.522 36.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268] - ------------------------------------------------------------------- - required time 36.882 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.326 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.441ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.441 - -Slack (MET) : 24.441ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.441 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.578ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.216 - ------------------------------------------------------------------- - slack 24.578 - -Slack (MET) : 24.578ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.216 - ------------------------------------------------------------------- - slack 24.578 - -Slack (MET) : 24.582ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.212 - ------------------------------------------------------------------- - slack 24.582 - -Slack (MET) : 24.582ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.212 - ------------------------------------------------------------------- - slack 24.582 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.654ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.628ns (logic 0.609ns (4.163%) route 14.019ns (95.837%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.768 12.139 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X38Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X38Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X38Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.139 - ------------------------------------------------------------------- - slack 24.654 - -Slack (MET) : 24.658ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.624ns (logic 0.609ns (4.165%) route 14.015ns (95.835%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.764 12.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X39Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X39Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X39Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.135 - ------------------------------------------------------------------- - slack 24.658 - -Slack (MET) : 24.680ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/C - clock pessimism -0.498 37.391 - clock uncertainty -0.077 37.315 - SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.564 36.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533] - ------------------------------------------------------------------- - required time 36.751 - arrival time -12.071 - ------------------------------------------------------------------- - slack 24.680 - -Slack (MET) : 24.722ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/C - clock pessimism -0.498 37.391 - clock uncertainty -0.077 37.315 - SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.522 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.071 - ------------------------------------------------------------------- - slack 24.722 - -Slack (MET) : 25.212ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.580 - ------------------------------------------------------------------- - slack 25.212 - -Slack (MET) : 25.212ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.580 - ------------------------------------------------------------------- - slack 25.212 - -Slack (MET) : 25.217ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.064ns (logic 0.609ns (4.330%) route 13.455ns (95.670%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.204 11.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X39Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X39Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X39Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.575 - ------------------------------------------------------------------- - slack 25.217 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 9.156ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 9.156ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.215ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C - clock pessimism -0.601 37.298 - clock uncertainty -0.197 37.101 - SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[0] - ------------------------------------------------------------------- - required time 36.492 - arrival time -27.336 - ------------------------------------------------------------------- - slack 9.156 - -Slack (MET) : 9.156ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.215ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - clock pessimism -0.601 37.298 - clock uncertainty -0.197 37.101 - SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[1] - ------------------------------------------------------------------- - required time 36.492 - arrival time -27.336 - ------------------------------------------------------------------- - slack 9.156 - -Slack (MET) : 11.865ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - clock pessimism -0.601 37.373 - clock uncertainty -0.197 37.176 - SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 36.567 - arrival time -24.702 - ------------------------------------------------------------------- - slack 11.865 - -Slack (MET) : 11.865ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.601 37.373 - clock uncertainty -0.197 37.176 - SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 36.567 - arrival time -24.702 - ------------------------------------------------------------------- - slack 11.865 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 11.249ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 11.249ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.124ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.361 27.638 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] ------------------------------------------------------------------- - required time 16.786 - arrival time -5.537 + required time 27.638 + arrival time -0.168 ------------------------------------------------------------------- - slack 11.249 + slack 27.470 -Slack (MET) : 11.249ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 27.512ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.124ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 16.786 - arrival time -5.537 + required time 27.680 + arrival time -0.168 ------------------------------------------------------------------- - slack 11.249 + slack 27.512 + +Slack (MET) : 27.512ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 27.680 + arrival time -0.168 + ------------------------------------------------------------------- + slack 27.512 + +Slack (MET) : 27.512ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 27.680 + arrival time -0.168 + ------------------------------------------------------------------- + slack 27.512 + +Slack (MET) : 27.512ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.300ns (logic 0.580ns (25.220%) route 1.720ns (74.780%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.118ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.832ns = ( 28.491 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.832 0.168 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 28.491 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.418 28.073 + clock uncertainty -0.074 27.999 + SLICE_X10Y41 FDCE (Recov_fdce_C_CLR) -0.319 27.680 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 27.680 + arrival time -0.168 + ------------------------------------------------------------------- + slack 27.512 + +Slack (MET) : 27.560ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.211ns (logic 0.580ns (26.238%) route 1.631ns (73.762%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.743 0.079 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y44 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + ------------------------------------------------------------------- + required time 27.639 + arrival time -0.079 + ------------------------------------------------------------------- + slack 27.560 + +Slack (MET) : 27.560ns (required time - arrival time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Recovery (Max at Slow Process Corner) + Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) + Data Path Delay: 2.211ns (logic 0.580ns (26.238%) route 1.631ns (73.762%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.117ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.831ns = ( 28.492 - 30.323 ) + Source Clock Delay (SCD): -2.132ns + Clock Pessimism Removal (CPR): -0.418ns + Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.210 -2.132 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.456 -1.676 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.887 -0.788 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.124 -0.664 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.743 0.079 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 30.323 30.323 r + K21 0.000 30.323 r clk (IN) + net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 28.492 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.418 28.074 + clock uncertainty -0.074 28.000 + SLICE_X10Y44 FDCE (Recov_fdce_C_CLR) -0.361 27.639 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + ------------------------------------------------------------------- + required time 27.639 + arrival time -0.079 + ------------------------------------------------------------------- + slack 27.560 @@ -27107,27 +13814,27 @@ Path Group: **async_default** From Clock: sys_clk To Clock: sys_clk -Setup : 0 Failing Endpoints, Worst Slack 4.581ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 8.003ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 4.581ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.003ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.151ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 ) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27144,14 +13851,14 @@ Slack (MET) : 4.581ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X63Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27163,31 +13870,31 @@ Slack (MET) : 4.581ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.696 17.868 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X85Y50 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/C - clock pessimism -0.507 17.361 - clock uncertainty -0.071 17.290 - SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2] + net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X63Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0]/C + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X63Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][0] ------------------------------------------------------------------- - required time 16.681 - arrival time -12.101 + required time 16.482 + arrival time -8.480 ------------------------------------------------------------------- - slack 4.581 + slack 8.003 -Slack (MET) : 5.171ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.089ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27204,14 +13911,14 @@ Slack (MET) : 5.171ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27223,31 +13930,31 @@ Slack (MET) : 5.171ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.701 17.873 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X77Y52 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/C - clock pessimism -0.507 17.366 - clock uncertainty -0.071 17.295 - SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0] + net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X62Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10]/C + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[208][10] ------------------------------------------------------------------- - required time 16.686 - arrival time -11.515 + required time 16.568 + arrival time -8.480 ------------------------------------------------------------------- - slack 5.171 + slack 8.089 -Slack (MET) : 5.624ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.089ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27264,14 +13971,14 @@ Slack (MET) : 5.624ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27283,31 +13990,31 @@ Slack (MET) : 5.624ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X90Y57 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2] + net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X62Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0]/C + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][0] ------------------------------------------------------------------- - required time 16.782 - arrival time -11.158 + required time 16.568 + arrival time -8.480 ------------------------------------------------------------------- - slack 5.624 + slack 8.089 -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.089ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) + Data Path Delay: 10.967ns (logic 0.668ns (6.091%) route 10.299ns (93.909%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.331ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.305ns = ( 17.695 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27324,14 +14031,14 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 9.247 8.480 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X62Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27343,31 +14050,31 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2] + net (fo=35652, routed) 1.524 17.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X62Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11]/C + clock pessimism -0.514 17.182 + clock uncertainty -0.071 17.111 + SLICE_X62Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.568 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][11] ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 16.568 + arrival time -8.480 ------------------------------------------------------------------- - slack 6.450 + slack 8.089 -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27384,14 +14091,14 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27403,31 +14110,31 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][2] ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 16.486 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.450 + slack 8.372 -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27444,14 +14151,14 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27463,31 +14170,31 @@ Slack (MET) : 6.450ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[202][9] ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 + required time 16.486 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.450 + slack 8.372 -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27504,14 +14211,14 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27523,31 +14230,31 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][0] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 + required time 16.486 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.650 + slack 8.372 -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27564,14 +14271,14 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27583,31 +14290,31 @@ Slack (MET) : 6.650ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][11] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 + required time 16.486 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.650 + slack 8.372 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.372ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27624,14 +14331,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X61Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27643,31 +14350,31 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X61Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X61Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[202][4] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.486 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.654 + slack 8.372 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27684,14 +14391,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27703,31 +14410,31 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][2] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.572 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.654 + slack 8.458 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27744,14 +14451,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27763,31 +14470,31 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][4] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.572 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.654 + slack 8.458 -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27804,14 +14511,14 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27823,31 +14530,31 @@ Slack (MET) : 6.654ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][5] ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 + required time 16.572 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.654 + slack 8.458 -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.458ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.601ns (logic 0.668ns (6.301%) route 9.933ns (93.699%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27864,14 +14571,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.881 8.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X60Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27883,31 +14590,31 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X60Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X60Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[216][9] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.572 + arrival time -8.114 ------------------------------------------------------------------- - slack 6.814 + slack 8.458 -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.665ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27924,14 +14631,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X57Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -27943,31 +14650,31 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X57Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X57Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][4] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.486 + arrival time -7.821 ------------------------------------------------------------------- - slack 6.814 + slack 8.665 -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.751ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.309ns (logic 0.668ns (6.480%) route 9.641ns (93.520%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.327ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.301ns = ( 17.699 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -27984,14 +14691,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.589 7.821 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X56Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28003,31 +14710,31 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19] + net (fo=35652, routed) 1.528 17.699 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X56Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9]/C + clock pessimism -0.514 17.186 + clock uncertainty -0.071 17.115 + SLICE_X56Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.572 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[218][9] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.572 + arrival time -7.821 ------------------------------------------------------------------- - slack 6.814 + slack 8.751 -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.856ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28044,14 +14751,14 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28063,31 +14770,31 @@ Slack (MET) : 6.814ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1] + net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X53Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][10] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 + required time 16.484 + arrival time -7.628 ------------------------------------------------------------------- - slack 6.814 + slack 8.856 -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.856ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28104,14 +14811,14 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28123,31 +14830,31 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5] + net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X53Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][3] ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 + required time 16.484 + arrival time -7.628 ------------------------------------------------------------------- - slack 6.881 + slack 8.856 -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.856ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28164,14 +14871,14 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28183,31 +14890,31 @@ Slack (MET) : 6.881ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg + net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X53Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X53Y169 FDCE (Recov_fdce_C_CLR) -0.629 16.484 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[214][8] ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 + required time 16.484 + arrival time -7.628 ------------------------------------------------------------------- - slack 6.881 + slack 8.856 -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28224,14 +14931,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28243,31 +14950,31 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4] + net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1]/C + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][1] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.654 + arrival time -7.758 ------------------------------------------------------------------- - slack 6.947 + slack 8.896 -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28284,14 +14991,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28303,31 +15010,31 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5] + net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2]/C + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][2] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.654 + arrival time -7.758 ------------------------------------------------------------------- - slack 6.947 + slack 8.896 -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28344,14 +15051,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28363,31 +15070,31 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6] + net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4]/C + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][4] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.654 + arrival time -7.758 ------------------------------------------------------------------- - slack 6.947 + slack 8.896 -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.896ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28404,14 +15111,14 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X159Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28423,31 +15130,31 @@ Slack (MET) : 6.947ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7] + net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X159Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5]/C + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X159Y190 FDCE (Recov_fdce_C_CLR) -0.629 16.654 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[45][5] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 + required time 16.654 + arrival time -7.758 ------------------------------------------------------------------- - slack 6.947 + slack 8.896 -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28464,14 +15171,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28483,31 +15190,31 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14] + net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X149Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0]/C + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][0] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.773 + arrival time -7.850 ------------------------------------------------------------------- - slack 6.955 + slack 8.923 -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28524,14 +15231,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28543,31 +15250,31 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15] + net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X149Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2]/C + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][2] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.773 + arrival time -7.850 ------------------------------------------------------------------- - slack 6.955 + slack 8.923 -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.923ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28584,14 +15291,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X149Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28603,31 +15310,31 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5] + net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X149Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5]/C + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X149Y205 FDCE (Recov_fdce_C_CLR) -0.629 16.773 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][5] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.773 + arrival time -7.850 ------------------------------------------------------------------- - slack 6.955 + slack 8.923 -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.942ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.115ns (logic 0.668ns (6.604%) route 9.447ns (93.396%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.329ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.303ns = ( 17.697 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28644,14 +15351,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.395 7.628 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X52Y169 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28663,31 +15370,31 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6] + net (fo=35652, routed) 1.526 17.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X52Y169 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8]/C + clock pessimism -0.514 17.184 + clock uncertainty -0.071 17.113 + SLICE_X52Y169 FDCE (Recov_fdce_C_CLR) -0.543 16.570 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[222][8] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.570 + arrival time -7.628 ------------------------------------------------------------------- - slack 6.955 + slack 8.942 -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.944ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28704,14 +15411,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28723,31 +15430,31 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7] + net (fo=35652, routed) 1.890 18.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X156Y206 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1/C + clock pessimism -0.514 17.548 + clock uncertainty -0.071 17.478 + SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[4]_rep__1 ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.849 + arrival time -7.904 ------------------------------------------------------------------- - slack 6.955 + slack 8.944 -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.944ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28764,14 +15471,14 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28783,31 +15490,31 @@ Slack (MET) : 6.955ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8] + net (fo=35652, routed) 1.890 18.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X156Y206 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1/C + clock pessimism -0.514 17.548 + clock uncertainty -0.071 17.478 + SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__1 ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 + required time 16.849 + arrival time -7.904 ------------------------------------------------------------------- - slack 6.955 + slack 8.944 -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.944ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) + Data Path Delay: 10.392ns (logic 0.668ns (6.428%) route 9.724ns (93.572%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.938ns = ( 18.062 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28824,14 +15531,14 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.672 7.904 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y206 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28843,31 +15550,31 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7] + net (fo=35652, routed) 1.890 18.062 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X156Y206 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2/C + clock pessimism -0.514 17.548 + clock uncertainty -0.071 17.478 + SLICE_X156Y206 FDCE (Recov_fdce_C_CLR) -0.629 16.849 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt_reg[5]_rep__2 ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 + required time 16.849 + arrival time -7.904 ------------------------------------------------------------------- - slack 6.967 + slack 8.944 -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.982ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28884,14 +15591,14 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X158Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28903,31 +15610,31 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8] + net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X158Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4]/C + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X158Y190 FDCE (Recov_fdce_C_CLR) -0.543 16.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][4] ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 + required time 16.740 + arrival time -7.758 ------------------------------------------------------------------- - slack 6.967 + slack 8.982 -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 8.982ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) + Data Path Delay: 10.245ns (logic 0.668ns (6.520%) route 9.577ns (93.480%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.133ns = ( 17.867 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -28944,14 +15651,14 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.525 7.758 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X158Y190 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -28963,31 +15670,31 @@ Slack (MET) : 6.967ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9] + net (fo=35652, routed) 1.696 17.867 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X158Y190 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8]/C + clock pessimism -0.514 17.354 + clock uncertainty -0.071 17.283 + SLICE_X158Y190 FDCE (Recov_fdce_C_CLR) -0.543 16.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[237][8] ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 + required time 16.740 + arrival time -7.758 ------------------------------------------------------------------- - slack 6.967 + slack 8.982 -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.009ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29004,14 +15711,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X148Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29023,31 +15730,31 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0] + net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X148Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10]/C + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X148Y205 FDCE (Recov_fdce_C_CLR) -0.543 16.859 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][10] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.859 + arrival time -7.850 ------------------------------------------------------------------- - slack 6.996 + slack 9.009 -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.009ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.338ns (logic 0.668ns (6.462%) route 9.670ns (93.538%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.040ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.014ns = ( 17.986 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29064,14 +15771,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.617 7.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X148Y205 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29083,31 +15790,31 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10] + net (fo=35652, routed) 1.814 17.986 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X148Y205 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6]/C + clock pessimism -0.514 17.472 + clock uncertainty -0.071 17.402 + SLICE_X148Y205 FDCE (Recov_fdce_C_CLR) -0.543 16.859 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[198][6] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.859 + arrival time -7.850 ------------------------------------------------------------------- - slack 6.996 + slack 9.009 -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.014ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29124,14 +15831,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X53Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29143,31 +15850,31 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3] + net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X53Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3]/C + clock pessimism -0.514 17.187 + clock uncertainty -0.071 17.116 + SLICE_X53Y167 FDCE (Recov_fdce_C_CLR) -0.629 16.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[198][3] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.487 + arrival time -7.473 ------------------------------------------------------------------- - slack 6.996 + slack 9.014 -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.038ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.118ns (logic 0.668ns (6.602%) route 9.450ns (93.398%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.205ns = ( 17.795 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29184,14 +15891,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.397 7.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X148Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29203,31 +15910,31 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4] + net (fo=35652, routed) 1.624 17.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X148Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11]/C + clock pessimism -0.514 17.282 + clock uncertainty -0.071 17.211 + SLICE_X148Y199 FDCE (Recov_fdce_C_CLR) -0.543 16.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][11] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.668 + arrival time -7.630 ------------------------------------------------------------------- - slack 6.996 + slack 9.038 -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.038ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.118ns (logic 0.668ns (6.602%) route 9.450ns (93.398%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.205ns = ( 17.795 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29244,14 +15951,14 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.397 7.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X148Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29263,31 +15970,31 @@ Slack (MET) : 6.996ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9] + net (fo=35652, routed) 1.624 17.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X148Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1]/C + clock pessimism -0.514 17.282 + clock uncertainty -0.071 17.211 + SLICE_X148Y199 FDCE (Recov_fdce_C_CLR) -0.543 16.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][1] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 + required time 16.668 + arrival time -7.630 ------------------------------------------------------------------- - slack 6.996 + slack 9.038 -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.038ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.118ns (logic 0.668ns (6.602%) route 9.450ns (93.398%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.205ns = ( 17.795 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29304,14 +16011,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.397 7.630 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X148Y199 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29323,31 +16030,31 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10] + net (fo=35652, routed) 1.624 17.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X148Y199 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6]/C + clock pessimism -0.514 17.282 + clock uncertainty -0.071 17.211 + SLICE_X148Y199 FDCE (Recov_fdce_C_CLR) -0.543 16.668 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[178][6] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.668 + arrival time -7.630 ------------------------------------------------------------------- - slack 7.098 + slack 9.038 -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.061ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.083ns (logic 0.668ns (6.625%) route 9.415ns (93.375%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.157ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29364,14 +16071,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.363 7.595 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29383,31 +16090,31 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11] + net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X156Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4]/C + clock pessimism -0.514 17.356 + clock uncertainty -0.071 17.285 + SLICE_X156Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][4] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.656 + arrival time -7.595 ------------------------------------------------------------------- - slack 7.098 + slack 9.061 -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.061ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.083ns (logic 0.668ns (6.625%) route 9.415ns (93.375%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.157ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29424,14 +16131,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.363 7.595 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29443,31 +16150,31 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8] + net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X156Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7]/C + clock pessimism -0.514 17.356 + clock uncertainty -0.071 17.285 + SLICE_X156Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][7] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.656 + arrival time -7.595 ------------------------------------------------------------------- - slack 7.098 + slack 9.061 -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.065ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) + Data Path Delay: 10.079ns (logic 0.668ns (6.628%) route 9.411ns (93.372%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.157ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29484,14 +16191,14 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.358 7.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X157Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29503,31 +16210,31 @@ Slack (MET) : 7.098ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9] + net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X157Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3]/C + clock pessimism -0.514 17.356 + clock uncertainty -0.071 17.285 + SLICE_X157Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][3] ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 + required time 16.656 + arrival time -7.591 ------------------------------------------------------------------- - slack 7.098 + slack 9.065 -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.065ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.079ns (logic 0.668ns (6.628%) route 9.411ns (93.372%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.157ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.131ns = ( 17.869 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29544,14 +16251,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.358 7.591 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X157Y195 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29563,31 +16270,31 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13] + net (fo=35652, routed) 1.698 17.869 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X157Y195 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8]/C + clock pessimism -0.514 17.356 + clock uncertainty -0.071 17.285 + SLICE_X157Y195 FDCE (Recov_fdce_C_CLR) -0.629 16.656 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[187][8] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.656 + arrival time -7.591 ------------------------------------------------------------------- - slack 7.115 + slack 9.065 -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.094ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.243ns (logic 0.668ns (6.521%) route 9.575ns (93.479%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.937ns = ( 18.063 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29604,14 +16311,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.523 7.756 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y202 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29623,31 +16330,31 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16] + net (fo=35652, routed) 1.891 18.063 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X156Y202 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6]/C + clock pessimism -0.514 17.549 + clock uncertainty -0.071 17.479 + SLICE_X156Y202 FDCE (Recov_fdce_C_CLR) -0.629 16.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][6] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.850 + arrival time -7.756 ------------------------------------------------------------------- - slack 7.115 + slack 9.094 -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.094ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 10.243ns (logic 0.668ns (6.521%) route 9.575ns (93.479%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.937ns = ( 18.063 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29664,14 +16371,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.523 7.756 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X156Y202 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29683,31 +16390,31 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21] + net (fo=35652, routed) 1.891 18.063 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X156Y202 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7]/C + clock pessimism -0.514 17.549 + clock uncertainty -0.071 17.479 + SLICE_X156Y202 FDCE (Recov_fdce_C_CLR) -0.629 16.850 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[191][7] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.850 + arrival time -7.756 ------------------------------------------------------------------- - slack 7.115 + slack 9.094 -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.095ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 9.886ns (logic 0.668ns (6.757%) route 9.218ns (93.243%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.320ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29724,14 +16431,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.166 7.398 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X50Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29743,31 +16450,31 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22] + net (fo=35652, routed) 1.535 17.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X50Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10]/C + clock pessimism -0.514 17.193 + clock uncertainty -0.071 17.122 + SLICE_X50Y160 FDCE (Recov_fdce_C_CLR) -0.629 16.493 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[87][10] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.493 + arrival time -7.398 ------------------------------------------------------------------- - slack 7.115 + slack 9.095 -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.099ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) + Data Path Delay: 9.882ns (logic 0.668ns (6.760%) route 9.214ns (93.240%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.320ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.294ns = ( 17.706 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29784,14 +16491,14 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.161 7.394 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X51Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29803,31 +16510,31 @@ Slack (MET) : 7.115ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23] + net (fo=35652, routed) 1.535 17.706 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X51Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10]/C + clock pessimism -0.514 17.193 + clock uncertainty -0.071 17.122 + SLICE_X51Y160 FDCE (Recov_fdce_C_CLR) -0.629 16.493 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[83][10] ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 + required time 16.493 + arrival time -7.394 ------------------------------------------------------------------- - slack 7.115 + slack 9.099 -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.100ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) + Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29844,14 +16551,14 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29863,31 +16570,31 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17] + net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3]/C + clock pessimism -0.514 17.187 + clock uncertainty -0.071 17.116 + SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][3] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 + required time 16.573 + arrival time -7.473 ------------------------------------------------------------------- - slack 7.136 + slack 9.100 -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.100ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) + Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29904,14 +16611,14 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29923,31 +16630,31 @@ Slack (MET) : 7.136ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18] + net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6]/C + clock pessimism -0.514 17.187 + clock uncertainty -0.071 17.116 + SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][6] ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 + required time 16.573 + arrival time -7.473 ------------------------------------------------------------------- - slack 7.136 + slack 9.100 -Slack (MET) : 7.143ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.100ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) + Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -29964,14 +16671,14 @@ Slack (MET) : 7.143ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -29983,31 +16690,31 @@ Slack (MET) : 7.143ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y1 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6] + net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7]/C + clock pessimism -0.514 17.187 + clock uncertainty -0.071 17.116 + SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][7] ------------------------------------------------------------------- - required time 17.069 - arrival time -9.926 + required time 16.573 + arrival time -7.473 ------------------------------------------------------------------- - slack 7.143 + slack 9.100 -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.100ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) + Data Path Delay: 9.960ns (logic 0.668ns (6.706%) route 9.292ns (93.294%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.326ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.300ns = ( 17.700 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -30024,14 +16731,14 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.240 7.473 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/delay_reg[1] + SLICE_X52Y167 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -30043,31 +16750,31 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/C - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0] + net (fo=35652, routed) 1.529 17.700 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X52Y167 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8]/C + clock pessimism -0.514 17.187 + clock uncertainty -0.071 17.116 + SLICE_X52Y167 FDCE (Recov_fdce_C_CLR) -0.543 16.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[208][8] ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 + required time 16.573 + arrival time -7.473 ------------------------------------------------------------------- - slack 7.222 + slack 9.100 -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C +Slack (MET) : 9.104ns (required time - arrival time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4]/CLR (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) + Data Path Delay: 10.157ns (logic 0.668ns (6.576%) route 9.489ns (93.424%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.039ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.013ns = ( 17.987 - 20.000 ) Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns + Clock Pessimism Removal (CPR): -0.514ns Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.122ns @@ -30084,14 +16791,14 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.854 -2.488 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.518 -1.970 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/Q + net (fo=5, routed) 1.052 -0.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[3] + SLICE_X112Y66 LUT5 (Prop_lut5_I4_O) 0.150 -0.767 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 8.437 7.670 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/valid_sr_reg[6] + SLICE_X155Y204 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 20.000 20.000 r @@ -30103,16 +16810,16 @@ Slack (MET) : 7.222ns (required time - arrival time) -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/C - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1] + net (fo=35652, routed) 1.815 17.987 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/sys_clk + SLICE_X155Y204 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4]/C + clock pessimism -0.514 17.473 + clock uncertainty -0.071 17.403 + SLICE_X155Y204 FDCE (Recov_fdce_C_CLR) -0.629 16.774 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[254][4] ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 + required time 16.774 + arrival time -7.670 ------------------------------------------------------------------- - slack 7.222 + slack 9.104 @@ -30137,11 +16844,11 @@ Slack: inf (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) + Data Path Delay: 12.140ns (logic 0.580ns (4.778%) route 11.560ns (95.222%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.470ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.662ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.834ns + Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -30160,14 +16867,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 10.834 9.644 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 + SLICE_X11Y38 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30178,9 +16885,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.995 -1.834 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C @@ -30189,11 +16896,11 @@ Slack: inf (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) + Data Path Delay: 12.140ns (logic 0.580ns (4.778%) route 11.560ns (95.222%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.470ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.662ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.834ns + Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -30212,14 +16919,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 10.834 9.644 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 + SLICE_X11Y38 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30230,9 +16937,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.995 -1.834 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C @@ -30241,11 +16948,11 @@ Slack: inf (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) + Data Path Delay: 12.115ns (logic 0.580ns (4.787%) route 11.535ns (95.213%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.738ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.743ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.753ns + Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -30264,14 +16971,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 - SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 10.809 9.620 pll_clk.u_rst_cpu/p_0_in_0 + SLICE_X5Y45 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30282,9 +16989,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.076 -1.753 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C Slack: inf Source: pll_clk.u_rst_sys/delay_reg[1]/C @@ -30293,11 +17000,11 @@ Slack: inf (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) + Data Path Delay: 12.115ns (logic 0.580ns (4.787%) route 11.535ns (95.213%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.738ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns - Source Clock Delay (SCD): -2.488ns + Clock Path Skew: 0.743ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.753ns + Source Clock Delay (SCD): -2.496ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -30316,14 +17023,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.846 -2.496 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 - SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.456 -2.040 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.726 -1.314 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.124 -1.190 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 10.809 9.620 pll_clk.u_rst_cpu/p_0_in_0 + SLICE_X5Y45 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30334,22 +17041,72 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.076 -1.753 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C Slack: inf - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[5]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 4.254ns (logic 0.419ns (9.850%) route 3.835ns (90.150%)) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.883ns (logic 0.175ns (9.295%) route 1.708ns (90.705%)) Logic Levels: 0 - Clock Path Skew: 0.544ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.939ns - Source Clock Delay (SCD): -2.483ns + Clock Path Skew: -0.225ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.608ns + Source Clock Delay (SCD): -0.383ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X113Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X113Y69 FDCE (Prop_fdce_C_Q) 0.175 -0.208 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q + net (fo=2, routed) 1.708 1.500 u_cpu/u_csr/interrupt[3] + SLICE_X47Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.654 -0.608 u_cpu/u_csr/cpu_clk + SLICE_X47Y54 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 3.767ns (logic 1.314ns (34.882%) route 2.453ns (65.118%)) + Logic Levels: 0 + Clock Path Skew: 0.559ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.844ns + Source Clock Delay (SCD): -2.403ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -30368,12 +17125,13 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.859 -2.483 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C + net (fo=35652, routed) 1.939 -2.403 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.419 -2.064 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q - net (fo=1, routed) 3.835 1.771 u_cpu/u_csr/interrupt[3] - SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.314 -1.089 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O + net (fo=1, routed) 2.453 1.364 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30384,22 +17142,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.890 -1.939 u_cpu/u_csr/cpu_clk - SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.985 -1.844 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.608ns (logic 0.595ns (37.010%) route 1.013ns (62.990%)) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 3.751ns (logic 1.317ns (35.109%) route 2.434ns (64.891%)) Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: 0.556ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.847ns + Source Clock Delay (SCD): -2.403ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -30412,83 +17170,32 @@ Slack: inf (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.939 -2.403 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 1.013 1.256 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.317 -1.086 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O + net (fo=1, routed) 2.434 1.349 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] + SLICE_X17Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.565ns (logic 0.612ns (39.107%) route 0.953ns (60.893%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.953 1.215 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] - SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.982 -1.847 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y23 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK @@ -30497,11 +17204,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.566ns (logic 0.612ns (39.088%) route 0.954ns (60.912%)) + Data Path Delay: 1.655ns (logic 0.612ns (36.985%) route 1.043ns (63.015%)) Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.505ns + Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -30520,13 +17227,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK + net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.954 1.214 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.270 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O + net (fo=1, routed) 1.043 1.313 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -30537,519 +17244,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.491ns (logic 0.482ns (32.335%) route 1.009ns (67.665%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 1.009 1.138 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.465ns (logic 0.612ns (41.773%) route 0.853ns (58.227%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 0.853 1.113 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.455ns (logic 0.612ns (42.062%) route 0.843ns (57.938%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.843 1.105 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.417ns (logic 0.480ns (33.882%) route 0.937ns (66.118%)) - Logic Levels: 0 - Clock Path Skew: -0.145ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.127 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.937 1.063 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.406ns (logic 0.595ns (42.317%) route 0.811ns (57.683%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.811 1.056 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.401ns (logic 0.491ns (35.055%) route 0.910ns (64.945%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.910 1.050 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.394ns (logic 0.480ns (34.421%) route 0.914ns (65.579%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.914 1.044 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.361ns (logic 0.480ns (35.268%) route 0.881ns (64.732%)) - Logic Levels: 0 - Clock Path Skew: -0.145ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.497ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.881 1.009 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.354ns (logic 0.485ns (35.824%) route 0.869ns (64.176%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 0.869 1.004 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.323ns (logic 0.612ns (46.260%) route 0.711ns (53.740%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.711 0.970 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK @@ -31058,11 +17255,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.317ns (logic 0.595ns (45.169%) route 0.722ns (54.831%)) + Data Path Delay: 1.619ns (logic 0.595ns (36.745%) route 1.024ns (63.255%)) Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: -0.167ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.510ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31081,13 +17278,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 0.722 0.967 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.252 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 1.024 1.276 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31098,22 +17295,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.310ns (logic 0.595ns (45.409%) route 0.715ns (54.591%)) + Data Path Delay: 1.592ns (logic 0.491ns (30.847%) route 1.101ns (69.153%)) Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: -0.166ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.510ns + Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31132,13 +17329,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 0.715 0.958 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.147 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 1.101 1.248 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] + SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31149,22 +17346,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.304ns (logic 0.491ns (37.657%) route 0.813ns (62.343%)) + Data Path Delay: 1.553ns (logic 0.595ns (38.309%) route 0.958ns (61.691%)) Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.505ns + Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31183,13 +17380,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK + net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.813 0.954 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.253 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 0.958 1.211 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31200,22 +17397,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.294ns (logic 0.612ns (47.295%) route 0.682ns (52.705%)) + Data Path Delay: 1.548ns (logic 0.612ns (39.544%) route 0.936ns (60.456%)) Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.353ns + Clock Path Skew: -0.166ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.509ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31234,13 +17431,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 0.682 0.941 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.269 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.936 1.204 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31251,22 +17448,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.754 -0.509 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.256ns (logic 0.482ns (38.384%) route 0.774ns (61.616%)) + Data Path Delay: 1.546ns (logic 0.612ns (39.595%) route 0.934ns (60.405%)) Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.506ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31285,13 +17482,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.129 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.774 0.903 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.269 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.934 1.202 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31302,22 +17499,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.248ns (logic 0.595ns (47.682%) route 0.653ns (52.318%)) + Data Path Delay: 1.529ns (logic 0.612ns (40.036%) route 0.917ns (59.964%)) Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns + Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31336,13 +17533,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 0.653 0.895 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.268 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.917 1.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31353,315 +17550,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.241ns (logic 0.491ns (39.556%) route 0.750ns (60.444%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.750 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.241ns (logic 0.485ns (39.089%) route 0.756ns (60.911%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.756 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.233ns (logic 0.482ns (39.088%) route 0.751ns (60.912%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.751 0.883 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.235ns (logic 0.491ns (39.769%) route 0.744ns (60.231%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 0.744 0.882 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.232ns (logic 0.595ns (48.288%) route 0.637ns (51.712%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.637 0.879 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.225ns (logic 0.482ns (39.361%) route 0.743ns (60.639%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 0.743 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK @@ -31670,11 +17561,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.222ns (logic 0.482ns (39.449%) route 0.740ns (60.551%)) + Data Path Delay: 1.523ns (logic 0.482ns (31.652%) route 1.041ns (68.348%)) Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: -0.167ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.510ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31693,13 +17584,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.740 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 1.041 1.180 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31710,9 +17601,264 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.464ns (logic 0.485ns (33.126%) route 0.979ns (66.874%)) + Logic Levels: 0 + Clock Path Skew: -0.167ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.510ns + Source Clock Delay (SCD): -0.343ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.142 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.979 1.121 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.438ns (logic 0.595ns (41.382%) route 0.843ns (58.618%)) + Logic Levels: 0 + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns + Source Clock Delay (SCD): -0.344ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.251 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.843 1.094 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.405ns (logic 0.482ns (34.311%) route 0.923ns (65.689%)) + Logic Levels: 0 + Clock Path Skew: -0.166ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.508ns + Source Clock Delay (SCD): -0.342ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.140 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.923 1.063 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] + SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.378ns (logic 0.482ns (34.967%) route 0.896ns (65.033%)) + Logic Levels: 0 + Clock Path Skew: -0.165ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.508ns + Source Clock Delay (SCD): -0.343ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 0.896 1.035 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] + SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.755 -0.508 u_Axi_CDC/rFifo/cpu_clk + SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.378ns (logic 0.491ns (35.636%) route 0.887ns (64.364%)) + Logic Levels: 0 + Clock Path Skew: -0.165ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.509ns + Source Clock Delay (SCD): -0.344ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.147 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 0.887 1.034 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.754 -0.509 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK @@ -31721,11 +17867,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.215ns (logic 0.480ns (39.516%) route 0.735ns (60.484%)) + Data Path Delay: 1.375ns (logic 0.480ns (34.917%) route 0.895ns (65.083%)) Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: -0.164ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31744,13 +17890,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.735 0.863 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.137 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.895 1.031 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31761,9 +17907,264 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.373ns (logic 0.595ns (43.346%) route 0.778ns (56.654%)) + Logic Levels: 0 + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.506ns + Source Clock Delay (SCD): -0.343ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.252 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.778 1.029 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.372ns (logic 0.485ns (35.358%) route 0.887ns (64.642%)) + Logic Levels: 0 + Clock Path Skew: -0.162ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.506ns + Source Clock Delay (SCD): -0.344ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.887 1.027 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.370ns (logic 0.595ns (43.428%) route 0.775ns (56.572%)) + Logic Levels: 0 + Clock Path Skew: -0.162ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.506ns + Source Clock Delay (SCD): -0.344ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.251 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.775 1.026 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.368ns (logic 0.491ns (35.893%) route 0.877ns (64.107%)) + Logic Levels: 0 + Clock Path Skew: -0.164ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns + Source Clock Delay (SCD): -0.343ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.148 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.877 1.025 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.362ns (logic 0.612ns (44.930%) route 0.750ns (55.070%)) + Logic Levels: 0 + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.505ns + Source Clock Delay (SCD): -0.344ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.268 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.750 1.018 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] + SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK @@ -31772,11 +18173,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.194ns (logic 0.480ns (40.215%) route 0.714ns (59.785%)) + Data Path Delay: 1.351ns (logic 0.480ns (35.518%) route 0.871ns (64.482%)) Logic Levels: 0 - Clock Path Skew: -0.217ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.567ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: -0.162ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.506ns + Source Clock Delay (SCD): -0.344ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31795,13 +18196,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.714 0.843 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.136 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O + net (fo=1, routed) 0.871 1.007 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31812,21 +18213,174 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C Slack: inf - Source: u_confreg/int_out_or_q2_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[2]/D + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.180ns (logic 0.175ns (14.825%) route 1.005ns (85.175%)) + Data Path Delay: 1.350ns (logic 0.482ns (35.709%) route 0.868ns (64.291%)) Logic Levels: 0 - Clock Path Skew: -0.172ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.509ns + Clock Path Skew: -0.161ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.505ns + Source Clock Delay (SCD): -0.344ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 0.868 1.006 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.336ns (logic 0.485ns (36.291%) route 0.851ns (63.709%)) + Logic Levels: 0 + Clock Path Skew: -0.165ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns + Source Clock Delay (SCD): -0.342ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.143 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.851 0.994 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] + SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.337ns (logic 0.485ns (36.281%) route 0.852ns (63.719%)) + Logic Levels: 0 + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns + Source Clock Delay (SCD): -0.344ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.964 -0.344 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.852 0.993 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.327ns (logic 0.595ns (44.836%) route 0.732ns (55.164%)) + Logic Levels: 0 + Clock Path Skew: -0.170ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -31846,12 +18400,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.971 -0.337 u_confreg/sys_clk - SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.175 -0.162 r u_confreg/int_out_or_q2_reg/Q - net (fo=1, routed) 1.005 0.843 u_cpu/u_csr/interrupt[0] - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.258 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.732 0.990 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31862,22 +18417,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.135ns (logic 0.491ns (43.278%) route 0.644ns (56.722%)) + Data Path Delay: 1.331ns (logic 0.491ns (36.899%) route 0.840ns (63.101%)) Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns + Clock Path Skew: -0.162ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.504ns + Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31896,13 +18451,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.644 0.781 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.149 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 0.840 0.988 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31913,22 +18468,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.759 -0.504 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.130ns (logic 0.485ns (42.936%) route 0.645ns (57.064%)) + Data Path Delay: 1.325ns (logic 0.485ns (36.591%) route 0.840ns (63.409%)) Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns + Clock Path Skew: -0.167ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.510ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31947,13 +18502,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.645 0.776 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.142 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.840 0.982 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -31964,22 +18519,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.753 -0.510 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.122ns (logic 0.485ns (43.231%) route 0.637ns (56.769%)) + Data Path Delay: 1.310ns (logic 0.612ns (46.719%) route 0.698ns (53.281%)) Logic Levels: 0 - Clock Path Skew: -0.216ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: -0.170ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.507ns + Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -31998,13 +18553,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.637 0.772 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.275 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.698 0.973 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32015,22 +18570,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.756 -0.507 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.111ns (logic 0.491ns (44.191%) route 0.620ns (55.809%)) + Data Path Delay: 1.311ns (logic 0.491ns (37.451%) route 0.820ns (62.549%)) Logic Levels: 0 - Clock Path Skew: -0.214ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.567ns - Source Clock Delay (SCD): -0.353ns + Clock Path Skew: -0.162ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.505ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -32049,13 +18604,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 0.620 0.758 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.148 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.820 0.968 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32066,22 +18621,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.758 -0.505 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.097ns (logic 0.485ns (44.212%) route 0.612ns (55.788%)) + Data Path Delay: 1.310ns (logic 0.480ns (36.641%) route 0.830ns (63.358%)) Logic Levels: 0 - Clock Path Skew: -0.214ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: -0.162ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.504ns + Source Clock Delay (SCD): -0.342ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -32100,13 +18655,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + net (fo=35652, routed) 0.966 -0.342 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 0.612 0.745 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 0.830 0.968 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32117,22 +18672,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.759 -0.504 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.089ns (logic 0.482ns (44.271%) route 0.607ns (55.729%)) + Data Path Delay: 1.290ns (logic 0.480ns (37.196%) route 0.810ns (62.804%)) Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.569ns - Source Clock Delay (SCD): -0.350ns + Clock Path Skew: -0.163ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.506ns + Source Clock Delay (SCD): -0.343ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -32151,13 +18706,13 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + net (fo=35652, routed) 0.965 -0.343 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 0.607 0.739 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.137 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 0.810 0.947 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32168,9 +18723,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.693 -0.569 u_Axi_CDC/rFifo/cpu_clk - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C Slack: inf Source: u_matmul_axi_slave/done_reg/C @@ -32179,11 +18734,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.975ns (logic 0.204ns (20.919%) route 0.771ns (79.081%)) + Data Path Delay: 1.261ns (logic 0.175ns (13.873%) route 1.086ns (86.127%)) Logic Levels: 0 - Clock Path Skew: -0.115ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.508ns - Source Clock Delay (SCD): -0.393ns + Clock Path Skew: -0.247ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.607ns + Source Clock Delay (SCD): -0.360ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -32202,12 +18757,12 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_matmul_axi_slave/sys_clk - SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C + net (fo=35652, routed) 0.948 -0.360 u_matmul_axi_slave/sys_clk + SLICE_X41Y78 FDRE r u_matmul_axi_slave/done_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.204 -0.189 r u_matmul_axi_slave/done_reg/Q - net (fo=12, routed) 0.771 0.582 u_cpu/u_csr/interrupt[2] - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D + SLICE_X41Y78 FDRE (Prop_fdre_C_Q) 0.175 -0.185 r u_matmul_axi_slave/done_reg/Q + net (fo=11, routed) 1.086 0.901 u_cpu/u_csr/interrupt[2] + SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32218,22 +18773,174 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.755 -0.508 u_cpu/u_csr/cpu_clk - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.655 -0.607 u_cpu/u_csr/cpu_clk + SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C Slack: inf - Source: u_cdma_matmul_bridge/seq_done_flag_reg/C + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.123ns (logic 0.491ns (43.737%) route 0.632ns (56.263%)) + Logic Levels: 0 + Clock Path Skew: -0.169ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.506ns + Source Clock Delay (SCD): -0.337ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.154 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O + net (fo=1, routed) 0.632 0.785 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.100ns (logic 0.482ns (43.813%) route 0.618ns (56.187%)) + Logic Levels: 0 + Clock Path Skew: -0.164ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.501ns + Source Clock Delay (SCD): -0.337ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.145 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O + net (fo=1, routed) 0.618 0.763 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] + SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.762 -0.501 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C + +Slack: inf + Source: u_confreg/int_out_or_q2_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.608ns (logic 0.160ns (26.335%) route 0.448ns (73.665%)) + Logic Levels: 0 + Clock Path Skew: -0.240ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.500ns + Source Clock Delay (SCD): -0.260ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y47 FDRE (Prop_fdre_C_Q) 0.160 -0.100 r u_confreg/int_out_or_q2_reg/Q + net (fo=1, routed) 0.448 0.347 u_cpu/u_csr/interrupt[0] + SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.763 -0.500 u_cpu/u_csr/cpu_clk + SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C + +Slack: inf + Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_cpu/u_csr/csr_estat_reg[3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.752ns (logic 0.231ns (30.703%) route 0.521ns (69.297%)) + Data Path Delay: 0.663ns (logic 0.231ns (34.839%) route 0.432ns (65.161%)) Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.223ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.610ns - Source Clock Delay (SCD): -0.387ns + Clock Path Skew: -0.227ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.608ns + Source Clock Delay (SCD): -0.381ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -32252,14 +18959,14 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.921 -0.387 u_cdma_matmul_bridge/sys_clk - SLICE_X61Y63 FDRE r u_cdma_matmul_bridge/seq_done_flag_reg/C + net (fo=35652, routed) 0.927 -0.381 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X49Y58 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X61Y63 FDRE (Prop_fdre_C_Q) 0.175 -0.212 r u_cdma_matmul_bridge/seq_done_flag_reg/Q - net (fo=3, routed) 0.521 0.309 u_snix_axil_cdma_mux_8ch/cdma_matmul_seq_irq - SLICE_X57Y58 LUT5 (Prop_lut5_I4_O) 0.056 0.365 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O - net (fo=1, routed) 0.000 0.365 u_cpu/u_csr/interrupt[1] - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D + SLICE_X49Y58 FDRE (Prop_fdre_C_Q) 0.175 -0.206 r u_snix_axil_cdma_mux_8ch/ch_done_reg[3]/Q + net (fo=3, routed) 0.432 0.226 u_snix_axil_cdma_mux_8ch/ch_done_reg[3]_1 + SLICE_X49Y56 LUT5 (Prop_lut5_I1_O) 0.056 0.282 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O + net (fo=1, routed) 0.000 0.282 u_cpu/u_csr/interrupt[1] + SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32270,9 +18977,359 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.652 -0.610 u_cpu/u_csr/cpu_clk - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.654 -0.608 u_cpu/u_csr/cpu_clk + SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.500ns (logic 0.204ns (40.806%) route 0.296ns (59.194%)) + Logic Levels: 0 + Clock Path Skew: -0.235ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.497ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.296 0.238 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.491ns (logic 0.204ns (41.563%) route 0.287ns (58.437%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.496ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.287 0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.453ns (logic 0.175ns (38.668%) route 0.278ns (61.332%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.495ns + Source Clock Delay (SCD): -0.261ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.086 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.278 0.191 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.768 -0.495 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.408ns (logic 0.204ns (50.037%) route 0.204ns (49.963%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.496ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/bFifo/sys_clk + SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.204 0.146 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.406ns (logic 0.204ns (50.186%) route 0.202ns (49.814%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.496ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.204 -0.058 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.202 0.144 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.401ns (logic 0.184ns (45.856%) route 0.217ns (54.144%)) + Logic Levels: 0 + Clock Path Skew: -0.235ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.497ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.184 -0.078 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.217 0.139 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.386ns (logic 0.175ns (45.391%) route 0.211ns (54.609%)) + Logic Levels: 0 + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.495ns + Source Clock Delay (SCD): -0.261ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.086 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.211 0.124 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.768 -0.495 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C @@ -32281,11 +19338,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.576ns (logic 0.160ns (27.764%) route 0.416ns (72.236%)) + Data Path Delay: 0.356ns (logic 0.184ns (51.719%) route 0.172ns (48.281%)) Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns + Clock Path Skew: -0.234ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.496ns + Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -32304,12 +19361,12 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.160 -0.071 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.416 0.345 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.184 -0.078 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.172 0.094 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -32320,18 +19377,1923 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.539 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + + + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: cpu_clk + To Clock: sys_clk + +Max Delay 154 Endpoints +Min Delay 0 Endpoints +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.577ns (logic 0.175ns (30.321%) route 0.402ns (69.679%)) + Data Path Delay: 1.604ns (logic 0.612ns (38.148%) route 0.992ns (61.852%)) + Logic Levels: 0 + Clock Path Skew: -0.188ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.233 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O + net (fo=1, routed) 0.992 1.225 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.436ns (logic 0.612ns (42.623%) route 0.824ns (57.377%)) + Logic Levels: 0 + Clock Path Skew: -0.219ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.265 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O + net (fo=1, routed) 0.824 1.089 u_Axi_CDC/awFifo/_zz_ram_port10[18] + SLICE_X13Y51 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk + SLICE_X13Y51 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.360ns (logic 0.595ns (43.759%) route 0.765ns (56.241%)) + Logic Levels: 0 + Clock Path Skew: -0.187ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.216 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA_D1/O + net (fo=1, routed) 0.765 0.981 u_Axi_CDC/arFifo/_zz_ram_port10__1[19] + SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.179ns (logic 0.595ns (50.464%) route 0.584ns (49.536%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.266ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.042 -0.266 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK + SLICE_X14Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y36 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.329 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O + net (fo=1, routed) 0.584 0.913 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] + SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C + +Slack: inf + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 1.135ns (logic 0.231ns (20.356%) route 0.904ns (79.644%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.263ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.495ns + Source Clock Delay (SCD): -0.232ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.076 -0.232 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.057 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.406 0.349 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.056 0.405 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.497 0.903 u_Axi_CDC/awFifo/bufferCC_12/p_0_in + SLICE_X8Y43 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C + +Slack: inf + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR + (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Recovery (Max at Fast Process Corner) + Data Path Delay: 1.135ns (logic 0.231ns (20.356%) route 0.904ns (79.644%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: -0.263ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.495ns + Source Clock Delay (SCD): -0.232ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.076 -0.232 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.175 -0.057 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.406 0.349 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.056 0.405 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.497 0.903 u_Axi_CDC/awFifo/bufferCC_12/p_0_in + SLICE_X8Y43 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.243ns (logic 0.612ns (49.219%) route 0.631ns (50.781%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.346ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.266 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O + net (fo=1, routed) 0.631 0.897 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] + SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.245ns (logic 0.485ns (38.963%) route 0.760ns (61.037%)) + Logic Levels: 0 + Clock Path Skew: -0.219ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.568ns + Source Clock Delay (SCD): -0.349ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.959 -0.349 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X40Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y57 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.136 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/O + net (fo=1, routed) 0.760 0.896 u_Axi_CDC/awFifo/_zz_ram_port10[16] + SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk + SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.236ns (logic 0.595ns (48.144%) route 0.641ns (51.856%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.248 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O + net (fo=1, routed) 0.641 0.889 u_Axi_CDC/awFifo/_zz_ram_port10[19] + SLICE_X15Y53 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk + SLICE_X15Y53 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.218ns (logic 0.482ns (39.571%) route 0.736ns (60.429%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.346ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.136 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/O + net (fo=1, routed) 0.736 0.872 u_Axi_CDC/arFifo/_zz_ram_port10__1[27] + SLICE_X14Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.248ns (logic 0.485ns (38.854%) route 0.763ns (61.146%)) + Logic Levels: 0 + Clock Path Skew: -0.188ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.106 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/O + net (fo=1, routed) 0.763 0.869 u_Axi_CDC/arFifo/_zz_ram_port10__1[16] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.248ns (logic 0.480ns (38.477%) route 0.768ns (61.523%)) + Logic Levels: 0 + Clock Path Skew: -0.193ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.572ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.101 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O + net (fo=1, routed) 0.768 0.868 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] + SLICE_X27Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/arFifo/sys_clk + SLICE_X27Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.122ns (logic 0.612ns (54.563%) route 0.510ns (45.437%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.263ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X14Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y39 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.349 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 0.510 0.858 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] + SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.112ns (logic 0.595ns (53.517%) route 0.517ns (46.483%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.263ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X14Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y39 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.332 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 0.517 0.849 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] + SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.194ns (logic 0.595ns (49.818%) route 0.599ns (50.182%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.346ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.249 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O + net (fo=1, routed) 0.599 0.848 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] + SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.215ns (logic 0.485ns (39.902%) route 0.730ns (60.098%)) + Logic Levels: 0 + Clock Path Skew: -0.188ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.106 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O + net (fo=1, routed) 0.730 0.836 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.206ns (logic 0.482ns (39.963%) route 0.724ns (60.037%)) + Logic Levels: 0 + Clock Path Skew: -0.190ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.569ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.103 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/O + net (fo=1, routed) 0.724 0.827 u_Axi_CDC/arFifo/_zz_ram_port10__1[21] + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.693 -0.569 u_Axi_CDC/arFifo/sys_clk + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.174ns (logic 0.612ns (52.147%) route 0.562ns (47.853%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.573ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.265 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/O + net (fo=1, routed) 0.562 0.826 u_Axi_CDC/awFifo/_zz_ram_port10[24] + SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk + SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.175ns (logic 0.480ns (40.841%) route 0.695ns (59.159%)) + Logic Levels: 0 + Clock Path Skew: -0.219ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.568ns + Source Clock Delay (SCD): -0.349ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.959 -0.349 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X40Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X40Y57 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.131 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/O + net (fo=1, routed) 0.695 0.826 u_Axi_CDC/awFifo/_zz_ram_port10[17] + SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk + SLICE_X10Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[17]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.200ns (logic 0.491ns (40.927%) route 0.709ns (59.073%)) + Logic Levels: 0 + Clock Path Skew: -0.187ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK + SLICE_X42Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X42Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.112 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB/O + net (fo=1, routed) 0.709 0.821 u_Axi_CDC/arFifo/_zz_ram_port10__1[20] + SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y52 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.158ns (logic 0.480ns (41.467%) route 0.678ns (58.533%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.346ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.134 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/O + net (fo=1, routed) 0.678 0.811 u_Axi_CDC/arFifo/_zz_ram_port10__1[29] + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.158ns (logic 0.595ns (51.367%) route 0.563ns (48.633%)) + Logic Levels: 0 + Clock Path Skew: -0.226ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.573ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.248 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA_D1/O + net (fo=1, routed) 0.563 0.811 u_Axi_CDC/awFifo/_zz_ram_port10[25] + SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk + SLICE_X27Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[25]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.150ns (logic 0.491ns (42.682%) route 0.659ns (57.318%)) + Logic Levels: 0 + Clock Path Skew: -0.221ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.346ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.145 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/O + net (fo=1, routed) 0.659 0.804 u_Axi_CDC/arFifo/_zz_ram_port10__1[26] + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[26]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.139ns (logic 0.485ns (42.577%) route 0.654ns (57.423%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.346ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y51 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.139 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/O + net (fo=1, routed) 0.654 0.793 u_Axi_CDC/arFifo/_zz_ram_port10__1[28] + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.033ns (logic 0.595ns (57.586%) route 0.438ns (42.414%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y41 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.333 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 0.438 0.771 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] + SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.102ns (logic 0.485ns (44.015%) route 0.617ns (55.985%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.138 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC/O + net (fo=1, routed) 0.617 0.755 u_Axi_CDC/awFifo/_zz_ram_port10[22] + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.017ns (logic 0.485ns (47.694%) route 0.532ns (52.306%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.264ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.044 -0.264 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X16Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y39 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.221 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.532 0.753 u_Axi_CDC/wFifo/_zz_ram_port10__0[22] + SLICE_X12Y48 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X12Y48 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.998ns (logic 0.612ns (61.341%) route 0.386ns (38.659%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y41 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.350 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 0.386 0.736 u_Axi_CDC/wFifo/_zz_ram_port10__0[30] + SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.976ns (logic 0.491ns (50.313%) route 0.485ns (49.687%)) + Logic Levels: 0 + Clock Path Skew: -0.231ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.263ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK + SLICE_X14Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y39 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.228 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 0.485 0.713 u_Axi_CDC/wFifo/_zz_ram_port10__0[14] + SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X14Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.966ns (logic 0.612ns (63.335%) route 0.354ns (36.665%)) + Logic Levels: 0 + Clock Path Skew: -0.228ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.495ns + Source Clock Delay (SCD): -0.267ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.041 -0.267 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X16Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y36 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.345 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.354 0.699 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] + SLICE_X12Y45 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/wFifo/sys_clk + SLICE_X12Y45 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.045ns (logic 0.485ns (46.426%) route 0.560ns (53.574%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.138 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC/O + net (fo=1, routed) 0.560 0.697 u_Axi_CDC/awFifo/_zz_ram_port10[28] + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.073ns (logic 0.480ns (44.722%) route 0.593ns (55.278%)) + Logic Levels: 0 + Clock Path Skew: -0.188ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.379ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.929 -0.379 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.101 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/O + net (fo=1, routed) 0.593 0.694 u_Axi_CDC/arFifo/_zz_ram_port10__1[17] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[17]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.025ns (logic 0.482ns (47.041%) route 0.543ns (52.959%)) + Logic Levels: 0 + Clock Path Skew: -0.219ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.135 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB_D1/O + net (fo=1, routed) 0.543 0.677 u_Axi_CDC/awFifo/_zz_ram_port10[21] + SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk + SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 1.018ns (logic 0.491ns (48.227%) route 0.527ns (51.773%)) + Logic Levels: 0 + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.144 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMB/O + net (fo=1, routed) 0.527 0.671 u_Axi_CDC/awFifo/_zz_ram_port10[20] + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.923ns (logic 0.612ns (66.307%) route 0.311ns (33.693%)) + Logic Levels: 0 + Clock Path Skew: -0.305ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.261ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y49 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.351 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.311 0.662 u_Axi_CDC/awFifo/_zz_ram_port10[6] + SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk + SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.920ns (logic 0.612ns (66.542%) route 0.308ns (33.458%)) + Logic Levels: 0 + Clock Path Skew: -0.233ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.261ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X14Y45 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y45 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.351 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.308 0.659 u_Axi_CDC/awFifo/_zz_ram_port10[0] + SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/awFifo/sys_clk + SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.907ns (logic 0.595ns (65.606%) route 0.312ns (34.394%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X14Y40 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y40 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.333 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 0.312 0.645 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] + SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X13Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.978ns (logic 0.491ns (50.222%) route 0.487ns (49.778%)) Logic Levels: 0 Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): -0.574ns @@ -32345,1028 +21307,48 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.175 -0.172 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.402 0.230 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.688 -0.574 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.550ns (logic 0.160ns (29.072%) route 0.390ns (70.928%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK + SLICE_X36Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/CLK ------------------------------------------------------------------- ------------------- + SLICE_X36Y56 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.144 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB/O + net (fo=1, routed) 0.487 0.630 u_Axi_CDC/awFifo/_zz_ram_port10[38] + SLICE_X28Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/D + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.160 -0.186 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.390 0.204 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.549ns (logic 0.175ns (31.853%) route 0.374ns (68.147%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.374 0.203 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk + SLICE_X28Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[38]/C Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.482ns (logic 0.175ns (36.304%) route 0.307ns (63.696%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.307 0.136 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.363ns (logic 0.175ns (48.223%) route 0.188ns (51.777%)) - Logic Levels: 0 - Clock Path Skew: -0.234ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.465ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.188 0.132 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.446ns (logic 0.160ns (35.900%) route 0.286ns (64.100%)) - Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.553ns - Source Clock Delay (SCD): -0.321ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.987 -0.321 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.160 -0.161 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.286 0.125 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.316ns (logic 0.175ns (55.416%) route 0.141ns (44.584%)) - Logic Levels: 0 - Clock Path Skew: -0.234ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.465ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.141 0.085 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: cpu_clk - To Clock: sys_clk - -Max Delay 162 Endpoints -Min Delay 0 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.565ns (logic 0.595ns (38.011%) route 0.970ns (61.989%)) - Logic Levels: 0 - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 0.970 1.333 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.442ns (logic 0.612ns (42.441%) route 0.830ns (57.559%)) - Logic Levels: 0 - Clock Path Skew: -0.317ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.548ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK - SLICE_X6Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O - net (fo=1, routed) 0.830 1.211 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] - SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.714 -0.548 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.394ns (logic 0.485ns (34.784%) route 0.909ns (65.216%)) - Logic Levels: 0 - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.909 1.162 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] - SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.251ns (logic 0.480ns (38.383%) route 0.771ns (61.617%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.771 1.021 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Fast Process Corner) - Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.541ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - -Slack: inf - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Fast Process Corner) - Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.541ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.183ns (logic 0.485ns (41.003%) route 0.698ns (58.997%)) - Logic Levels: 0 - Clock Path Skew: -0.316ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.545ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.698 0.954 u_Axi_CDC/wFifo/_zz_ram_port10__0[22] - SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.717 -0.545 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.172ns (logic 0.595ns (50.766%) route 0.577ns (49.234%)) - Logic Levels: 0 - Clock Path Skew: -0.313ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.364 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.577 0.941 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.160ns (logic 0.485ns (41.821%) route 0.675ns (58.179%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 0.675 0.931 u_Axi_CDC/wFifo/_zz_ram_port10__0[10] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.146ns (logic 0.612ns (53.398%) route 0.534ns (46.602%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.534 0.915 u_Axi_CDC/wFifo/_zz_ram_port10__0[30] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.116ns (logic 0.595ns (53.305%) route 0.521ns (46.695%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 0.521 0.884 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.107ns (logic 0.480ns (43.345%) route 0.627ns (56.655%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.627 0.878 u_Axi_CDC/wFifo/_zz_ram_port10__0[29] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.202ns (logic 0.612ns (50.922%) route 0.590ns (49.078%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O - net (fo=1, routed) 0.590 0.850 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.188ns (logic 0.595ns (50.069%) route 0.593ns (49.931%)) + Data Path Delay: 0.890ns (logic 0.482ns (54.149%) route 0.408ns (45.851%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -33384,14 +21366,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK - SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK + SLICE_X14Y45 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O - net (fo=1, routed) 0.593 0.847 u_Axi_CDC/awFifo/_zz_ram_port10[19] - SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D + SLICE_X14Y45 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.221 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.408 0.629 u_Axi_CDC/awFifo/_zz_ram_port10[3] + SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -33403,518 +21385,8 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.021ns (logic 0.595ns (58.252%) route 0.426ns (41.748%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 0.426 0.792 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.128ns (logic 0.480ns (42.561%) route 0.648ns (57.439%)) - Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.571ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O - net (fo=1, routed) 0.648 0.776 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] - SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk - SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.005ns (logic 0.480ns (47.778%) route 0.525ns (52.222%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.249 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.525 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[35] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.002ns (logic 0.482ns (48.095%) route 0.520ns (51.905%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.520 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[21] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.001ns (logic 0.480ns (47.953%) route 0.521ns (52.047%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.521 0.769 u_Axi_CDC/wFifo/_zz_ram_port10__0[17] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.109ns (logic 0.612ns (55.196%) route 0.497ns (44.804%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.340ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK - SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.272 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O - net (fo=1, routed) 0.497 0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] - SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.116ns (logic 0.485ns (43.457%) route 0.631ns (56.543%)) - Logic Levels: 0 - Clock Path Skew: -0.224ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O - net (fo=1, routed) 0.631 0.764 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.987ns (logic 0.612ns (62.028%) route 0.375ns (37.972%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.375 0.757 u_Axi_CDC/wFifo/_zz_ram_port10__0[6] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.973ns (logic 0.612ns (62.874%) route 0.361ns (37.126%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 0.361 0.741 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.966ns (logic 0.491ns (50.838%) route 0.475ns (49.162%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 0.475 0.734 u_Axi_CDC/wFifo/_zz_ram_port10__0[14] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/awFifo/sys_clk + SLICE_X14Y48 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK @@ -33923,11 +21395,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.960ns (logic 0.595ns (62.000%) route 0.365ns (38.000%)) + Data Path Delay: 0.887ns (logic 0.595ns (67.046%) route 0.292ns (32.954%)) Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns + Clock Path Skew: -0.229ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.496ns + Source Clock Delay (SCD): -0.267ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -33945,14 +21417,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.041 -0.267 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X16Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.365 0.730 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D + SLICE_X16Y36 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.328 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 0.292 0.620 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] + SLICE_X15Y40 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -33964,212 +21436,8 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.949ns (logic 0.485ns (51.100%) route 0.464ns (48.900%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.254 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.464 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[34] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.047ns (logic 0.595ns (56.827%) route 0.452ns (43.173%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.571ns - Source Clock Delay (SCD): -0.340ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK - SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.255 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O - net (fo=1, routed) 0.452 0.707 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] - SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.928ns (logic 0.482ns (51.961%) route 0.446ns (48.039%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.536ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.446 0.698 u_Axi_CDC/wFifo/_zz_ram_port10__0[9] - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.040ns (logic 0.485ns (46.647%) route 0.555ns (53.353%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.345ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.140 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O - net (fo=1, routed) 0.555 0.695 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C + net (fo=35652, routed) 0.767 -0.496 u_Axi_CDC/wFifo/sys_clk + SLICE_X15Y40 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK @@ -34178,113 +21446,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.920ns (logic 0.612ns (66.545%) route 0.308ns (33.455%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 0.308 0.687 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.025ns (logic 0.612ns (59.711%) route 0.413ns (40.289%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.342ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X22Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.270 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.413 0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] - SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk - SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.021ns (logic 0.612ns (59.936%) route 0.409ns (40.064%)) + Data Path Delay: 0.880ns (logic 0.612ns (69.512%) route 0.268ns (30.488%)) Logic Levels: 0 Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns + Destination Clock Delay (DCD): -0.495ns + Source Clock Delay (SCD): -0.262ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -34302,14 +21468,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK - SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X14Y40 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O - net (fo=1, routed) 0.409 0.680 u_Axi_CDC/awFifo/_zz_ram_port10[18] - SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D + SLICE_X14Y40 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.350 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.268 0.618 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] + SLICE_X14Y44 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34321,21 +21487,21 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/wFifo/sys_clk + SLICE_X14Y44 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.026ns (logic 0.482ns (46.999%) route 0.544ns (53.001%)) + Data Path Delay: 0.965ns (logic 0.482ns (49.970%) route 0.483ns (50.030%)) Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.352ns + Clock Path Skew: -0.220ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.347ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -34353,14 +21519,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/O - net (fo=1, routed) 0.544 0.673 u_Axi_CDC/arFifo/_zz_ram_port10__1[21] - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D + SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.482 0.135 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMB_D1/O + net (fo=1, routed) 0.483 0.617 u_Axi_CDC/awFifo/_zz_ram_port10[27] + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34372,467 +21538,8 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.019ns (logic 0.595ns (58.363%) route 0.424ns (41.637%)) - Logic Levels: 0 - Clock Path Skew: -0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.247 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O - net (fo=1, routed) 0.424 0.671 u_Axi_CDC/awFifo/_zz_ram_port10[31] - SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.898ns (logic 0.612ns (68.152%) route 0.286ns (31.848%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.537ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.286 0.669 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.896ns (logic 0.595ns (66.419%) route 0.301ns (33.581%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.301 0.667 u_Axi_CDC/wFifo/_zz_ram_port10__0[19] - SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.012ns (logic 0.485ns (47.912%) route 0.527ns (52.088%)) - Logic Levels: 0 - Clock Path Skew: -0.264ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.612ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.137 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.527 0.664 u_Axi_CDC/arFifo/_zz_ram_port10__1[4] - SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.650 -0.612 u_Axi_CDC/arFifo/sys_clk - SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.892ns (logic 0.480ns (53.815%) route 0.412ns (46.185%)) - Logic Levels: 0 - Clock Path Skew: -0.306ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.412 0.660 u_Axi_CDC/wFifo/_zz_ram_port10__0[5] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.880ns (logic 0.612ns (69.559%) route 0.268ns (30.441%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.536ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.268 0.651 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.879ns (logic 0.482ns (54.834%) route 0.397ns (45.166%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.397 0.650 u_Axi_CDC/wFifo/_zz_ram_port10__0[27] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.990ns (logic 0.612ns (61.797%) route 0.378ns (38.203%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X22Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.378 0.649 u_Axi_CDC/awFifo/_zz_ram_port10[12] - SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.981ns (logic 0.612ns (62.415%) route 0.369ns (37.585%)) - Logic Levels: 0 - Clock Path Skew: -0.229ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.570ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK - SLICE_X22Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/O - net (fo=1, routed) 0.369 0.639 u_Axi_CDC/awFifo/_zz_ram_port10[24] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/C + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y54 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[27]/C Slack: inf Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK @@ -34841,113 +21548,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.866ns (logic 0.485ns (56.026%) route 0.381ns (43.974%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.381 0.636 u_Axi_CDC/wFifo/_zz_ram_port10__0[28] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.867ns (logic 0.491ns (56.612%) route 0.376ns (43.388%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 0.376 0.635 u_Axi_CDC/wFifo/_zz_ram_port10__0[2] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.955ns (logic 0.612ns (64.074%) route 0.343ns (35.926%)) + Data Path Delay: 0.881ns (logic 0.485ns (55.040%) route 0.396ns (44.960%)) Logic Levels: 0 Clock Path Skew: -0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.338ns + Destination Clock Delay (DCD): -0.497ns + Source Clock Delay (SCD): -0.267ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -34965,14 +21570,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.041 -0.267 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK + SLICE_X16Y36 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.274 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 0.343 0.617 u_Axi_CDC/awFifo/_zz_ram_port10[6] - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D + SLICE_X16Y36 RAMD32 (Prop_ramd32_CLK_O) + 0.485 0.218 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.396 0.614 u_Axi_CDC/wFifo/_zz_ram_port10__0[28] + SLICE_X15Y39 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -34984,161 +21589,8 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.947ns (logic 0.595ns (62.805%) route 0.352ns (37.195%)) - Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/O - net (fo=1, routed) 0.352 0.606 u_Axi_CDC/awFifo/_zz_ram_port10[43] - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.953ns (logic 0.612ns (64.216%) route 0.341ns (35.784%)) - Logic Levels: 0 - Clock Path Skew: -0.229ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.577ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.264 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 0.341 0.605 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/arFifo/sys_clk - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.833ns (logic 0.491ns (58.937%) route 0.342ns (41.063%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.537ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.262 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.342 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[8] - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/C + net (fo=35652, routed) 0.766 -0.497 u_Axi_CDC/wFifo/sys_clk + SLICE_X15Y39 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/C Slack: inf Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK @@ -35147,11 +21599,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.937ns (logic 0.595ns (63.501%) route 0.342ns (36.499%)) + Data Path Delay: 0.860ns (logic 0.595ns (69.192%) route 0.265ns (30.808%)) Logic Levels: 0 - Clock Path Skew: -0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.338ns + Clock Path Skew: -0.305ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.566ns + Source Clock Delay (SCD): -0.261ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -35169,14 +21621,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.257 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 0.342 0.599 u_Axi_CDC/awFifo/_zz_ram_port10[7] - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D + SLICE_X16Y49 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.334 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.265 0.599 u_Axi_CDC/awFifo/_zz_ram_port10[7] + SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -35188,21 +21640,21 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C + net (fo=35652, routed) 0.696 -0.566 u_Axi_CDC/awFifo/sys_clk + SLICE_X17Y50 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.914ns (logic 0.612ns (66.980%) route 0.302ns (33.020%)) + Data Path Delay: 0.932ns (logic 0.612ns (65.656%) route 0.320ns (34.344%)) Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.341ns + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.567ns + Source Clock Delay (SCD): -0.337ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -35220,14 +21672,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.971 -0.337 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.302 0.573 u_Axi_CDC/awFifo/_zz_ram_port10[42] - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) + 0.612 0.275 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA/O + net (fo=1, routed) 0.320 0.595 u_Axi_CDC/awFifo/_zz_ram_port10[30] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -35239,8 +21691,263 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C + net (fo=35652, routed) 0.695 -0.567 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[30]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.942ns (logic 0.480ns (50.982%) route 0.462ns (49.018%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.571ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK + SLICE_X36Y53 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y53 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.133 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMC_D1/O + net (fo=1, routed) 0.462 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[23] + SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/awFifo/sys_clk + SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.941ns (logic 0.480ns (51.024%) route 0.461ns (48.976%)) + Logic Levels: 0 + Clock Path Skew: -0.224ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.571ns + Source Clock Delay (SCD): -0.347ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK + SLICE_X36Y54 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y54 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.133 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMC_D1/O + net (fo=1, routed) 0.461 0.594 u_Axi_CDC/awFifo/_zz_ram_port10[29] + SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/awFifo/sys_clk + SLICE_X22Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.854ns (logic 0.480ns (56.183%) route 0.374ns (43.817%)) + Logic Levels: 0 + Clock Path Skew: -0.230ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.264ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.044 -0.264 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK + SLICE_X16Y39 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y39 RAMD32 (Prop_ramd32_CLK_O) + 0.480 0.216 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 0.374 0.590 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] + SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X15Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.848ns (logic 0.491ns (57.928%) route 0.357ns (42.072%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.494ns + Source Clock Delay (SCD): -0.262ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK + SLICE_X14Y40 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y40 RAMD32 (Prop_ramd32_CLK_O) + 0.491 0.229 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.357 0.585 u_Axi_CDC/wFifo/_zz_ram_port10__0[2] + SLICE_X12Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.769 -0.494 u_Axi_CDC/wFifo/sys_clk + SLICE_X12Y47 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Fast Process Corner) + Data Path Delay: 0.930ns (logic 0.595ns (63.955%) route 0.335ns (36.045%)) + Logic Levels: 0 + Clock Path Skew: -0.232ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -0.578ns + Source Clock Delay (SCD): -0.346ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK + SLICE_X36Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y52 RAMD32 (Prop_ramd32_CLK_O) + 0.595 0.249 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O + net (fo=1, routed) 0.335 0.584 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] + SLICE_X39Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.684 -0.578 u_Axi_CDC/arFifo/sys_clk + SLICE_X39Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C @@ -35283,7 +21990,7 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll - BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- @@ -35304,6 +22011,180 @@ Min Delay 0 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- +Slack: inf + Source: u_axi_dvi/DVI_RECT_DIR_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.253ns (logic 6.148ns (40.303%) route 9.106ns (59.697%)) + Logic Levels: 10 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk + SLICE_X3Y75 FDRE r u_axi_dvi/DVI_RECT_DIR_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y75 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/DVI_RECT_DIR_reg[1]/Q + net (fo=5, routed) 1.288 -0.591 u_axi_dvi/DVI_RECT_DIR_reg_n_0_[1] + SLICE_X2Y75 LUT2 (Prop_lut2_I0_O) 0.124 -0.467 r u_axi_dvi/video_red_OBUF[2]_inst_i_285/O + net (fo=1, routed) 0.000 -0.467 u_axi_dvi/video_red_OBUF[2]_inst_i_285_n_0 + SLICE_X2Y75 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 0.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_274/CO[3] + net (fo=1, routed) 0.000 0.066 u_axi_dvi/video_red_OBUF[2]_inst_i_274_n_0 + SLICE_X2Y76 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.183 r u_axi_dvi/video_red_OBUF[2]_inst_i_256/CO[3] + net (fo=1, routed) 0.000 0.183 u_axi_dvi/video_red_OBUF[2]_inst_i_256_n_0 + SLICE_X2Y77 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 0.498 r u_axi_dvi/video_red_OBUF[2]_inst_i_220/O[3] + net (fo=1, routed) 0.957 1.455 u_axi_dvi/video_red_OBUF[2]_inst_i_220_n_4 + SLICE_X1Y77 LUT2 (Prop_lut2_I1_O) 0.307 1.762 r u_axi_dvi/video_red_OBUF[2]_inst_i_156/O + net (fo=1, routed) 0.000 1.762 u_axi_dvi/video_red_OBUF[2]_inst_i_156_n_0 + SLICE_X1Y77 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 2.163 r u_axi_dvi/video_red_OBUF[2]_inst_i_86/CO[3] + net (fo=1, routed) 0.000 2.163 u_axi_dvi/video_red_OBUF[2]_inst_i_86_n_0 + SLICE_X1Y78 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.277 f u_axi_dvi/video_red_OBUF[2]_inst_i_34/CO[3] + net (fo=1, routed) 1.331 3.608 u_axi_dvi/video_red_OBUF[2]_inst_i_34_n_0 + SLICE_X6Y74 LUT4 (Prop_lut4_I3_O) 0.124 3.732 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O + net (fo=1, routed) 0.282 4.014 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 + SLICE_X6Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.138 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.248 9.386 video_red_OBUF[0] + K23 OBUF (Prop_obuf_I_O) 3.533 12.919 r video_red_OBUF[0]_inst/O + net (fo=0) 0.000 12.919 video_red[0] + K23 r video_red[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_RECT_DIR_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 15.140ns (logic 6.175ns (40.788%) route 8.964ns (59.212%)) + Logic Levels: 10 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk + SLICE_X3Y75 FDRE r u_axi_dvi/DVI_RECT_DIR_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y75 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/DVI_RECT_DIR_reg[1]/Q + net (fo=5, routed) 1.288 -0.591 u_axi_dvi/DVI_RECT_DIR_reg_n_0_[1] + SLICE_X2Y75 LUT2 (Prop_lut2_I0_O) 0.124 -0.467 r u_axi_dvi/video_red_OBUF[2]_inst_i_285/O + net (fo=1, routed) 0.000 -0.467 u_axi_dvi/video_red_OBUF[2]_inst_i_285_n_0 + SLICE_X2Y75 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 0.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_274/CO[3] + net (fo=1, routed) 0.000 0.066 u_axi_dvi/video_red_OBUF[2]_inst_i_274_n_0 + SLICE_X2Y76 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.183 r u_axi_dvi/video_red_OBUF[2]_inst_i_256/CO[3] + net (fo=1, routed) 0.000 0.183 u_axi_dvi/video_red_OBUF[2]_inst_i_256_n_0 + SLICE_X2Y77 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 0.498 r u_axi_dvi/video_red_OBUF[2]_inst_i_220/O[3] + net (fo=1, routed) 0.957 1.455 u_axi_dvi/video_red_OBUF[2]_inst_i_220_n_4 + SLICE_X1Y77 LUT2 (Prop_lut2_I1_O) 0.307 1.762 r u_axi_dvi/video_red_OBUF[2]_inst_i_156/O + net (fo=1, routed) 0.000 1.762 u_axi_dvi/video_red_OBUF[2]_inst_i_156_n_0 + SLICE_X1Y77 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 2.163 r u_axi_dvi/video_red_OBUF[2]_inst_i_86/CO[3] + net (fo=1, routed) 0.000 2.163 u_axi_dvi/video_red_OBUF[2]_inst_i_86_n_0 + SLICE_X1Y78 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.277 f u_axi_dvi/video_red_OBUF[2]_inst_i_34/CO[3] + net (fo=1, routed) 1.331 3.608 u_axi_dvi/video_red_OBUF[2]_inst_i_34_n_0 + SLICE_X6Y74 LUT4 (Prop_lut4_I3_O) 0.124 3.732 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O + net (fo=1, routed) 0.282 4.014 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 + SLICE_X6Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.138 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 5.106 9.245 video_red_OBUF[0] + F24 OBUF (Prop_obuf_I_O) 3.560 12.805 r video_red_OBUF[1]_inst/O + net (fo=0) 0.000 12.805 video_red[1] + F24 r video_red[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/DVI_RECT_DIR_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 14.873ns (logic 6.202ns (41.697%) route 8.671ns (58.303%)) + Logic Levels: 10 (CARRY4=5 LUT2=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk + SLICE_X3Y75 FDRE r u_axi_dvi/DVI_RECT_DIR_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X3Y75 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/DVI_RECT_DIR_reg[1]/Q + net (fo=5, routed) 1.288 -0.591 u_axi_dvi/DVI_RECT_DIR_reg_n_0_[1] + SLICE_X2Y75 LUT2 (Prop_lut2_I0_O) 0.124 -0.467 r u_axi_dvi/video_red_OBUF[2]_inst_i_285/O + net (fo=1, routed) 0.000 -0.467 u_axi_dvi/video_red_OBUF[2]_inst_i_285_n_0 + SLICE_X2Y75 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.533 0.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_274/CO[3] + net (fo=1, routed) 0.000 0.066 u_axi_dvi/video_red_OBUF[2]_inst_i_274_n_0 + SLICE_X2Y76 CARRY4 (Prop_carry4_CI_CO[3]) + 0.117 0.183 r u_axi_dvi/video_red_OBUF[2]_inst_i_256/CO[3] + net (fo=1, routed) 0.000 0.183 u_axi_dvi/video_red_OBUF[2]_inst_i_256_n_0 + SLICE_X2Y77 CARRY4 (Prop_carry4_CI_O[3]) + 0.315 0.498 r u_axi_dvi/video_red_OBUF[2]_inst_i_220/O[3] + net (fo=1, routed) 0.957 1.455 u_axi_dvi/video_red_OBUF[2]_inst_i_220_n_4 + SLICE_X1Y77 LUT2 (Prop_lut2_I1_O) 0.307 1.762 r u_axi_dvi/video_red_OBUF[2]_inst_i_156/O + net (fo=1, routed) 0.000 1.762 u_axi_dvi/video_red_OBUF[2]_inst_i_156_n_0 + SLICE_X1Y77 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.401 2.163 r u_axi_dvi/video_red_OBUF[2]_inst_i_86/CO[3] + net (fo=1, routed) 0.000 2.163 u_axi_dvi/video_red_OBUF[2]_inst_i_86_n_0 + SLICE_X1Y78 CARRY4 (Prop_carry4_CI_CO[3]) + 0.114 2.277 f u_axi_dvi/video_red_OBUF[2]_inst_i_34/CO[3] + net (fo=1, routed) 1.331 3.608 u_axi_dvi/video_red_OBUF[2]_inst_i_34_n_0 + SLICE_X6Y74 LUT4 (Prop_lut4_I3_O) 0.124 3.732 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O + net (fo=1, routed) 0.282 4.014 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 + SLICE_X6Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.138 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 4.813 8.952 video_red_OBUF[0] + E26 OBUF (Prop_obuf_I_O) 3.587 12.538 r video_red_OBUF[2]_inst/O + net (fo=0) 0.000 12.538 video_red[2] + E26 r video_red[2] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -35330,21 +22211,21 @@ Slack: inf -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 3.123 8.781 video_clk_OBUF + net (fo=35652, routed) 3.123 8.781 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O net (fo=0) 0.000 12.314 video_clk H22 f video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[0] + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[5] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 14.637ns (logic 5.878ns (40.155%) route 8.759ns (59.845%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) + Data Path Delay: 14.229ns (logic 3.990ns (28.040%) route 10.239ns (71.960%)) + Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns @@ -35361,236 +22242,24 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.844 8.704 video_red_OBUF[0] - K23 OBUF (Prop_obuf_I_O) 3.533 12.236 r video_red_OBUF[0]_inst/O - net (fo=0) 0.000 12.236 video_red[0] - K23 r video_red[0] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q + net (fo=1, routed) 10.239 8.380 dpy1_OBUF[5] + G16 OBUF (Prop_obuf_I_O) 3.534 11.914 r dpy1_OBUF[5]_inst/O + net (fo=0) 0.000 11.914 dpy1[5] + G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.524ns (logic 5.905ns (40.660%) route 8.618ns (59.340%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.703 8.563 video_red_OBUF[0] - F24 OBUF (Prop_obuf_I_O) 3.560 12.123 r video_red_OBUF[1]_inst/O - net (fo=0) 0.000 12.123 video_red[1] - F24 r video_red[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.257ns (logic 5.932ns (41.605%) route 8.325ns (58.395%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.410 8.270 video_red_OBUF[0] - E26 OBUF (Prop_obuf_I_O) 3.587 11.856 r video_red_OBUF[2]_inst/O - net (fo=0) 0.000 11.856 video_red[2] - E26 r video_red[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/vdata_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_vsync - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 12.474ns (logic 4.441ns (35.600%) route 8.033ns (64.400%)) - Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk - SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 r u_axi_dvi/vdata_reg[3]/Q - net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] - SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 f u_axi_dvi/vdata[11]_i_4/O - net (fo=3, routed) 0.682 0.535 u_axi_dvi/vdata[11]_i_4_n_0 - SLICE_X18Y86 LUT6 (Prop_lut6_I5_O) 0.124 0.659 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O - net (fo=1, routed) 0.789 1.448 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 - SLICE_X17Y86 LUT4 (Prop_lut4_I0_O) 0.124 1.572 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O - net (fo=1, routed) 4.943 6.515 video_vsync_OBUF - H24 OBUF (Prop_obuf_I_O) 3.551 10.066 r video_vsync_OBUF_inst/O - net (fo=0) 0.000 10.066 video_vsync - H24 r video_vsync (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/vdata_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_de - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 12.135ns (logic 4.451ns (36.677%) route 7.684ns (63.323%)) - Logic Levels: 4 (LUT2=1 LUT6=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk - SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 f u_axi_dvi/vdata_reg[3]/Q - net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] - SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 r u_axi_dvi/vdata[11]_i_4/O - net (fo=3, routed) 0.305 0.158 u_axi_dvi/vdata[11]_i_4_n_0 - SLICE_X17Y86 LUT6 (Prop_lut6_I2_O) 0.124 0.282 r u_axi_dvi/video_de_OBUF_inst_i_2/O - net (fo=1, routed) 1.030 1.313 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 - SLICE_X14Y86 LUT6 (Prop_lut6_I0_O) 0.124 1.437 r u_axi_dvi/video_de_OBUF_inst_i_1/O - net (fo=1, routed) 4.730 6.166 video_de_OBUF - G24 OBUF (Prop_obuf_I_O) 3.561 9.727 r video_de_OBUF_inst/O - net (fo=0) 0.000 9.727 video_de - G24 r video_de (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[3]/C + Source: u_axi_dvi/hdata_reg[5]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_hsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.932ns (logic 4.311ns (36.128%) route 7.621ns (63.872%)) + Data Path Delay: 12.666ns (logic 4.311ns (34.035%) route 8.355ns (65.965%)) Logic Levels: 3 (LUT5=2 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -35608,28 +22277,67 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.936 -2.406 u_axi_dvi/sys_clk - SLICE_X12Y81 FDRE r u_axi_dvi/hdata_reg[3]/C + net (fo=35652, routed) 2.011 -2.331 u_axi_dvi/sys_clk + SLICE_X6Y71 FDRE r u_axi_dvi/hdata_reg[5]/C ------------------------------------------------------------------- ------------------- - SLICE_X12Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.888 r u_axi_dvi/hdata_reg[3]/Q - net (fo=11, routed) 1.940 0.053 u_axi_dvi/hdata_reg_n_0_[3] - SLICE_X8Y82 LUT5 (Prop_lut5_I2_O) 0.124 0.177 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O - net (fo=1, routed) 0.953 1.130 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 - SLICE_X9Y86 LUT5 (Prop_lut5_I4_O) 0.124 1.254 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O - net (fo=1, routed) 4.728 5.982 video_hsync_OBUF - J24 OBUF (Prop_obuf_I_O) 3.545 9.527 r video_hsync_OBUF_inst/O - net (fo=0) 0.000 9.527 video_hsync + SLICE_X6Y71 FDRE (Prop_fdre_C_Q) 0.518 -1.813 r u_axi_dvi/hdata_reg[5]/Q + net (fo=12, routed) 1.535 -0.278 u_axi_dvi/hdata_reg_n_0_[5] + SLICE_X0Y70 LUT5 (Prop_lut5_I1_O) 0.124 -0.154 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O + net (fo=1, routed) 1.000 0.847 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 + SLICE_X0Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.971 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O + net (fo=1, routed) 5.820 6.791 video_hsync_OBUF + J24 OBUF (Prop_obuf_I_O) 3.545 10.336 r video_hsync_OBUF_inst/O + net (fo=0) 0.000 10.336 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[8]_lopt_replica/C + Source: u_axi_dvi/hdata_reg[5]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[8] + Destination: video_de (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.822ns (logic 4.079ns (34.503%) route 7.743ns (65.497%)) + Data Path Delay: 12.471ns (logic 4.553ns (36.506%) route 7.918ns (63.494%)) + Logic Levels: 3 (LUT5=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.011 -2.331 u_axi_dvi/sys_clk + SLICE_X6Y71 FDRE r u_axi_dvi/hdata_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X6Y71 FDRE (Prop_fdre_C_Q) 0.518 -1.813 f u_axi_dvi/hdata_reg[5]/Q + net (fo=12, routed) 1.755 -0.058 u_axi_dvi/hdata_reg_n_0_[5] + SLICE_X2Y72 LUT5 (Prop_lut5_I4_O) 0.146 0.088 f u_axi_dvi/video_de_OBUF_inst_i_3/O + net (fo=1, routed) 0.950 1.038 u_axi_dvi/video_de_OBUF_inst_i_3_n_0 + SLICE_X1Y74 LUT6 (Prop_lut6_I5_O) 0.328 1.366 r u_axi_dvi/video_de_OBUF_inst_i_1/O + net (fo=1, routed) 5.214 6.580 video_de_OBUF + G24 OBUF (Prop_obuf_I_O) 3.561 10.141 r video_de_OBUF_inst/O + net (fo=0) 0.000 10.141 video_de + G24 r video_de (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[1]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 11.831ns (logic 4.135ns (34.951%) route 7.696ns (65.049%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -35647,24 +22355,24 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.016 -2.326 u_confreg/sys_clk - SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.808 r u_confreg/led_data_reg[8]_lopt_replica/Q - net (fo=1, routed) 7.743 5.935 lopt_14 - C23 OBUF (Prop_obuf_I_O) 3.561 9.496 r leds_OBUF[8]_inst/O - net (fo=0) 0.000 9.496 leds[8] - C23 r leds[8] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[1]_lopt_replica/Q + net (fo=1, routed) 7.696 5.797 lopt_7 + E21 OBUF (Prop_obuf_I_O) 3.716 9.513 r leds_OBUF[1]_inst/O + net (fo=0) 0.000 9.513 leds[1] + E21 r leds[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[15]_lopt_replica/C + Source: u_confreg/led_data_reg[13]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[15] + Destination: leds[13] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.646ns (logic 4.019ns (34.509%) route 7.627ns (65.491%)) + Data Path Delay: 11.808ns (logic 4.027ns (34.101%) route 7.781ns (65.899%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -35682,59 +22390,24 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[15]_lopt_replica/Q - net (fo=1, routed) 7.627 5.768 lopt_6 - B20 OBUF (Prop_obuf_I_O) 3.563 9.331 r leds_OBUF[15]_inst/O - net (fo=0) 0.000 9.331 leds[15] - B20 r leds[15] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[13]_lopt_replica/Q + net (fo=1, routed) 7.781 5.920 lopt_4 + A22 OBUF (Prop_obuf_I_O) 3.571 9.490 r leds_OBUF[13]_inst/O + net (fo=0) 0.000 9.490 leds[13] + A22 r leds[13] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.447ns (logic 4.018ns (35.101%) route 7.429ns (64.899%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[4]_lopt_replica/Q - net (fo=1, routed) 7.429 5.569 lopt_10 - C22 OBUF (Prop_obuf_I_O) 3.562 9.131 r leds_OBUF[4]_inst/O - net (fo=0) 0.000 9.131 leds[4] - C22 r leds[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[4] + Destination: dpy1[7] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.583ns (logic 3.995ns (34.493%) route 7.588ns (65.507%)) + Data Path Delay: 11.797ns (logic 3.976ns (33.704%) route 7.821ns (66.296%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -35752,25 +22425,25 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q - net (fo=1, routed) 7.588 5.556 dpy0_OBUF[4] - E18 OBUF (Prop_obuf_I_O) 3.539 9.095 r dpy0_OBUF[4]_inst/O - net (fo=0) 0.000 9.095 dpy0[4] - E18 r dpy0[4] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q + net (fo=1, routed) 7.821 5.961 dpy1_OBUF[7] + G17 OBUF (Prop_obuf_I_O) 3.520 9.482 r dpy1_OBUF[7]_inst/O + net (fo=0) 0.000 9.482 dpy1[7] + G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[5]_lopt_replica/C + Source: u_axi_dvi/vdata_reg[3]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[5] + Destination: video_vsync (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.360ns (logic 4.147ns (36.509%) route 7.213ns (63.491%)) - Logic Levels: 1 (OBUF=1) + Data Path Delay: 11.798ns (logic 4.379ns (37.113%) route 7.419ns (62.887%)) + Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns @@ -35787,14 +22460,20 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C + net (fo=35652, routed) 2.007 -2.335 u_axi_dvi/sys_clk + SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[5]_lopt_replica/Q - net (fo=1, routed) 7.213 5.317 lopt_11 - C21 OBUF (Prop_obuf_I_O) 3.728 9.045 r leds_OBUF[5]_inst/O - net (fo=0) 0.000 9.045 leds[5] - C21 r leds[5] (OUT) + SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.456 -1.879 r u_axi_dvi/vdata_reg[3]/Q + net (fo=11, routed) 1.199 -0.680 u_axi_dvi/vdata_reg_n_0_[3] + SLICE_X1Y80 LUT2 (Prop_lut2_I0_O) 0.124 -0.556 f u_axi_dvi/vdata[11]_i_4/O + net (fo=3, routed) 0.670 0.114 u_axi_dvi/vdata[11]_i_4_n_0 + SLICE_X1Y79 LUT6 (Prop_lut6_I5_O) 0.124 0.238 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O + net (fo=1, routed) 0.571 0.810 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 + SLICE_X1Y80 LUT4 (Prop_lut4_I0_O) 0.124 0.934 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O + net (fo=1, routed) 4.979 5.913 video_vsync_OBUF + H24 OBUF (Prop_obuf_I_O) 3.551 9.463 r video_vsync_OBUF_inst/O + net (fo=0) 0.000 9.463 video_vsync + H24 r video_vsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -35804,7 +22483,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.061ns (logic 4.038ns (36.509%) route 7.023ns (63.491%)) + Data Path Delay: 11.407ns (logic 4.038ns (35.402%) route 7.369ns (64.598%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -35822,61 +22501,24 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C + net (fo=35652, routed) 2.020 -2.322 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[9]_lopt_replica/Q - net (fo=1, routed) 7.023 5.159 lopt_15 - A23 OBUF (Prop_obuf_I_O) 3.582 8.741 r leds_OBUF[9]_inst/O - net (fo=0) 0.000 8.741 leds[9] + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.456 -1.866 r u_confreg/led_data_reg[9]_lopt_replica/Q + net (fo=1, routed) 7.369 5.503 lopt_15 + A23 OBUF (Prop_obuf_I_O) 3.582 9.085 r leds_OBUF[9]_inst/O + net (fo=0) 0.000 9.085 leds[9] A23 r leds[9] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_uart_controller/uart0/regs/mcr_reg[4]/C + Source: u_confreg/led_data_reg[8]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_TX + Destination: leds[8] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 11.130ns (logic 4.308ns (38.708%) route 6.822ns (61.292%)) - Logic Levels: 2 (LUT4=1 OBUFT=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X8Y66 FDRE r u_axi_uart_controller/uart0/regs/mcr_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X8Y66 FDRE (Prop_fdre_C_Q) 0.478 -1.925 r u_axi_uart_controller/uart0/regs/mcr_reg[4]/Q - net (fo=8, routed) 1.213 -0.712 u_axi_uart_controller/uart0/regs/transmitter/counter_b_reg[7]_0[0] - SLICE_X1Y60 LUT4 (Prop_lut4_I3_O) 0.301 -0.411 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O - net (fo=1, routed) 5.609 5.198 UART_TX_IOBUF_inst/I - H18 OBUFT (Prop_obuft_I_O) 3.529 8.727 r UART_TX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 8.727 UART_TX - H18 r UART_TX (INOUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.508ns (logic 3.970ns (37.784%) route 6.537ns (62.216%)) + Data Path Delay: 11.228ns (logic 4.155ns (37.007%) route 7.073ns (62.993%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -35894,84 +22536,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q - net (fo=1, routed) 6.537 4.680 dpy1_OBUF[3] - F17 OBUF (Prop_obuf_I_O) 3.514 8.194 r dpy1_OBUF[3]_inst/O - net (fo=0) 0.000 8.194 dpy1[3] - F17 r dpy1[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.468ns (logic 4.014ns (38.349%) route 6.454ns (61.651%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q - net (fo=1, routed) 6.454 4.422 dpy0_OBUF[2] - B21 OBUF (Prop_obuf_I_O) 3.558 7.981 r dpy0_OBUF[2]_inst/O - net (fo=0) 0.000 7.981 dpy0[2] - B21 r dpy0[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.251ns (logic 4.018ns (39.198%) route 6.233ns (60.802%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[3]_lopt_replica/Q - net (fo=1, routed) 6.233 4.375 lopt_9 - D23 OBUF (Prop_obuf_I_O) 3.562 7.937 r leds_OBUF[3]_inst/O - net (fo=0) 0.000 7.937 leds[3] - D23 r leds[3] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[8]_lopt_replica/Q + net (fo=1, routed) 7.073 5.174 lopt_14 + C23 OBUF (Prop_obuf_I_O) 3.736 8.910 r leds_OBUF[8]_inst/O + net (fo=0) 0.000 8.910 leds[8] + C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -35981,7 +22553,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 10.239ns (logic 4.043ns (39.483%) route 6.196ns (60.517%)) + Data Path Delay: 11.173ns (logic 4.043ns (36.183%) route 7.130ns (63.817%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -35999,25 +22571,25 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C + net (fo=35652, routed) 2.020 -2.322 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[2]_lopt_replica/Q - net (fo=1, routed) 6.196 4.339 lopt_8 - A24 OBUF (Prop_obuf_I_O) 3.587 7.926 r leds_OBUF[2]_inst/O - net (fo=0) 0.000 7.926 leds[2] + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.456 -1.866 r u_confreg/led_data_reg[2]_lopt_replica/Q + net (fo=1, routed) 7.130 5.265 lopt_8 + A24 OBUF (Prop_obuf_I_O) 3.587 8.852 r leds_OBUF[2]_inst/O + net (fo=0) 0.000 8.852 leds[2] A24 r leds[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[11]_lopt_replica/C + Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[11] + Destination: UART_TX (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 9.633ns (logic 4.023ns (41.758%) route 5.611ns (58.242%)) - Logic Levels: 1 (OBUF=1) + Data Path Delay: 10.783ns (logic 4.124ns (38.250%) route 6.658ns (61.750%)) + Logic Levels: 2 (LUT3=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns @@ -36034,119 +22606,17 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + net (fo=35652, routed) 2.210 -2.132 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X3Y39 FDRE r u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[11]_lopt_replica/Q - net (fo=1, routed) 5.611 3.752 lopt_2 - A18 OBUF (Prop_obuf_I_O) 3.567 7.319 r leds_OBUF[11]_inst/O - net (fo=0) 0.000 7.319 leds[11] - A18 r leds[11] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.588ns (logic 3.993ns (41.645%) route 5.595ns (58.355%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q - net (fo=1, routed) 5.595 3.738 dpy1_OBUF[6] - F15 OBUF (Prop_obuf_I_O) 3.537 7.275 r dpy1_OBUF[6]_inst/O - net (fo=0) 0.000 7.275 dpy1[6] - F15 r dpy1[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[6]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.545ns (logic 4.133ns (43.294%) route 5.413ns (56.706%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[6]_lopt_replica/Q - net (fo=1, routed) 5.413 3.517 lopt_12 - E20 OBUF (Prop_obuf_I_O) 3.714 7.231 r leds_OBUF[6]_inst/O - net (fo=0) 0.000 7.231 leds[6] - E20 r leds[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.552ns (logic 4.002ns (41.895%) route 5.550ns (58.105%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q - net (fo=1, routed) 5.550 3.519 dpy0_OBUF[5] - C19 OBUF (Prop_obuf_I_O) 3.546 7.065 r dpy0_OBUF[5]_inst/O - net (fo=0) 0.000 7.065 dpy0[5] - C19 r dpy0[5] (OUT) + SLICE_X3Y39 FDRE (Prop_fdre_C_Q) 0.456 -1.676 f u_axi_uart_controller/uart0/regs/mode_reg_reg[2]/Q + net (fo=13, routed) 1.623 -0.052 u_axi_uart_controller/uart0/regs/transmitter/tf_pop_reg_0[1] + SLICE_X0Y42 LUT3 (Prop_lut3_I1_O) 0.124 0.072 f u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O + net (fo=1, routed) 5.035 5.107 UART_TX_IOBUF_inst/T + H18 OBUFT (TriStatE_obuft_T_O) + 3.544 8.651 r UART_TX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 8.651 UART_TX + H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -36156,7 +22626,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 9.354ns (logic 3.998ns (42.735%) route 5.357ns (57.265%)) + Data Path Delay: 10.945ns (logic 3.998ns (36.523%) route 6.948ns (63.477%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36174,16 +22644,156 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q - net (fo=1, routed) 5.357 3.499 dpy1_OBUF[2] - E17 OBUF (Prop_obuf_I_O) 3.542 7.041 r dpy1_OBUF[2]_inst/O - net (fo=0) 0.000 7.041 dpy1[2] + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q + net (fo=1, routed) 6.948 5.088 dpy1_OBUF[2] + E17 OBUF (Prop_obuf_I_O) 3.542 8.630 r dpy1_OBUF[2]_inst/O + net (fo=0) 0.000 8.630 dpy1[2] E17 r dpy1[2] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[7] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.860ns (logic 4.001ns (36.837%) route 6.860ns (63.163%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q + net (fo=1, routed) 6.860 5.001 dpy0_OBUF[7] + C17 OBUF (Prop_obuf_I_O) 3.545 8.546 r dpy0_OBUF[7]_inst/O + net (fo=0) 0.000 8.546 dpy0[7] + C17 r dpy0[7] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.784ns (logic 3.995ns (37.049%) route 6.788ns (62.951%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q + net (fo=1, routed) 6.788 4.930 dpy0_OBUF[4] + E18 OBUF (Prop_obuf_I_O) 3.539 8.469 r dpy0_OBUF[4]_inst/O + net (fo=0) 0.000 8.469 dpy0[4] + E18 r dpy0[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.693ns (logic 4.012ns (37.523%) route 6.681ns (62.477%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q + net (fo=1, routed) 6.681 4.822 dpy0_OBUF[6] + B17 OBUF (Prop_obuf_I_O) 3.556 8.379 r dpy0_OBUF[6]_inst/O + net (fo=0) 0.000 8.379 dpy0[6] + B17 r dpy0[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 10.507ns (logic 4.021ns (38.273%) route 6.486ns (61.727%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q + net (fo=1, routed) 6.486 4.626 dpy1_OBUF[0] + A17 OBUF (Prop_obuf_I_O) 3.565 8.192 r dpy1_OBUF[0]_inst/O + net (fo=0) 0.000 8.192 dpy1[0] + A17 r dpy1[0] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: u_axi_uart_controller/uart0/regs/sclk_reg_reg/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36191,7 +22801,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 9.365ns (logic 4.162ns (44.443%) route 5.203ns (55.557%)) + Data Path Delay: 9.779ns (logic 4.299ns (43.966%) route 5.479ns (56.034%)) Logic Levels: 2 (LUT2=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36209,26 +22819,26 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.944 -2.398 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X10Y64 FDRE r u_axi_uart_controller/uart0/regs/sclk_reg_reg/C + net (fo=35652, routed) 2.209 -2.133 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X6Y42 FDRE r u_axi_uart_controller/uart0/regs/sclk_reg_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X10Y64 FDRE (Prop_fdre_C_Q) 0.518 -1.880 r u_axi_uart_controller/uart0/regs/sclk_reg_reg/Q - net (fo=2, routed) 0.521 -1.358 u_axi_uart_controller/uart0/regs/sclk_reg_reg_n_0 - SLICE_X10Y64 LUT2 (Prop_lut2_I0_O) 0.124 -1.234 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O - net (fo=1, routed) 4.682 3.448 UART_RX_IOBUF_inst/I - J20 OBUFT (Prop_obuft_I_O) 3.520 6.968 r UART_RX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 6.968 UART_RX + SLICE_X6Y42 FDRE (Prop_fdre_C_Q) 0.478 -1.655 r u_axi_uart_controller/uart0/regs/sclk_reg_reg/Q + net (fo=2, routed) 0.825 -0.829 u_axi_uart_controller/uart0/regs/sclk_reg_reg_n_0 + SLICE_X6Y41 LUT2 (Prop_lut2_I0_O) 0.301 -0.528 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O + net (fo=1, routed) 4.654 4.126 UART_RX_IOBUF_inst/I + J20 OBUFT (Prop_obuft_I_O) 3.520 7.646 r UART_RX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 7.646 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[1] + Destination: dpy1[3] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 9.190ns (logic 4.001ns (43.538%) route 5.189ns (56.462%)) + Data Path Delay: 9.847ns (logic 3.970ns (40.320%) route 5.877ns (59.680%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36246,294 +22856,14 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q - net (fo=1, routed) 5.189 3.157 dpy0_OBUF[1] - D19 OBUF (Prop_obuf_I_O) 3.545 6.703 r dpy0_OBUF[1]_inst/O - net (fo=0) 0.000 6.703 dpy0[1] - D19 r dpy0[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.973ns (logic 3.998ns (44.549%) route 4.976ns (55.451%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q - net (fo=1, routed) 4.976 3.118 dpy1_OBUF[4] - E16 OBUF (Prop_obuf_I_O) 3.542 6.660 r dpy1_OBUF[4]_inst/O - net (fo=0) 0.000 6.660 dpy1[4] - E16 r dpy1[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.071ns (logic 4.029ns (44.418%) route 5.042ns (55.582%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q - net (fo=1, routed) 5.042 3.010 dpy0_OBUF[3] - A19 OBUF (Prop_obuf_I_O) 3.573 6.583 r dpy0_OBUF[3]_inst/O - net (fo=0) 0.000 6.583 dpy0[3] - A19 r dpy0[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.824ns (logic 4.005ns (45.390%) route 4.819ns (54.610%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q - net (fo=1, routed) 4.819 2.961 dpy1_OBUF[1] - D16 OBUF (Prop_obuf_I_O) 3.549 6.510 r dpy1_OBUF[1]_inst/O - net (fo=0) 0.000 6.510 dpy1[1] - D16 r dpy1[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[12]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[12] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.826ns (logic 3.998ns (45.302%) route 4.828ns (54.698%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[12]_lopt_replica/Q - net (fo=1, routed) 4.828 2.967 lopt_3 - D20 OBUF (Prop_obuf_I_O) 3.542 6.510 r leds_OBUF[12]_inst/O - net (fo=0) 0.000 6.510 leds[12] - D20 r leds[12] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.940ns (logic 4.016ns (44.923%) route 4.924ns (55.077%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q - net (fo=1, routed) 4.924 2.892 dpy0_OBUF[0] - B19 OBUF (Prop_obuf_I_O) 3.560 6.452 r dpy0_OBUF[0]_inst/O - net (fo=0) 0.000 6.452 dpy0[0] - B19 r dpy0[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.755ns (logic 3.990ns (45.576%) route 4.765ns (54.424%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q - net (fo=1, routed) 4.765 2.907 dpy1_OBUF[5] - G16 OBUF (Prop_obuf_I_O) 3.534 6.441 r dpy1_OBUF[5]_inst/O - net (fo=0) 0.000 6.441 dpy1[5] - G16 r dpy1[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.735ns (logic 4.021ns (46.039%) route 4.713ns (53.961%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q - net (fo=1, routed) 4.713 2.856 dpy1_OBUF[0] - A17 OBUF (Prop_obuf_I_O) 3.565 6.421 r dpy1_OBUF[0]_inst/O - net (fo=0) 0.000 6.421 dpy1[0] - A17 r dpy1[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[7] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.710ns (logic 3.976ns (45.648%) route 4.734ns (54.352%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q - net (fo=1, routed) 4.734 2.877 dpy1_OBUF[7] - G17 OBUF (Prop_obuf_I_O) 3.520 6.397 r dpy1_OBUF[7]_inst/O - net (fo=0) 0.000 6.397 dpy1[7] - G17 r dpy1[7] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q + net (fo=1, routed) 5.877 4.017 dpy1_OBUF[3] + F17 OBUF (Prop_obuf_I_O) 3.514 7.531 r dpy1_OBUF[3]_inst/O + net (fo=0) 0.000 7.531 dpy1[3] + F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -36543,7 +22873,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.585ns (logic 4.019ns (46.814%) route 4.566ns (53.186%)) + Data Path Delay: 9.844ns (logic 4.019ns (40.824%) route 5.826ns (59.176%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36561,24 +22891,24 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[14]_lopt_replica/Q - net (fo=1, routed) 4.566 2.707 lopt_5 - A20 OBUF (Prop_obuf_I_O) 3.563 6.270 r leds_OBUF[14]_inst/O - net (fo=0) 0.000 6.270 leds[14] + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[14]_lopt_replica/Q + net (fo=1, routed) 5.826 3.964 lopt_5 + A20 OBUF (Prop_obuf_I_O) 3.563 7.527 r leds_OBUF[14]_inst/O + net (fo=0) 0.000 7.527 leds[14] A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[6] + Destination: dpy1[4] (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.741ns (logic 4.012ns (45.901%) route 4.729ns (54.099%)) + Data Path Delay: 9.776ns (logic 3.998ns (40.890%) route 5.779ns (59.110%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36596,14 +22926,469 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q - net (fo=1, routed) 4.729 2.697 dpy0_OBUF[6] - B17 OBUF (Prop_obuf_I_O) 3.556 6.254 r dpy0_OBUF[6]_inst/O - net (fo=0) 0.000 6.254 dpy0[6] - B17 r dpy0[6] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q + net (fo=1, routed) 5.779 3.919 dpy1_OBUF[4] + E16 OBUF (Prop_obuf_I_O) 3.542 7.461 r dpy1_OBUF[4]_inst/O + net (fo=0) 0.000 7.461 dpy1[4] + E16 r dpy1[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.751ns (logic 4.001ns (41.036%) route 5.749ns (58.964%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q + net (fo=1, routed) 5.749 3.891 dpy0_OBUF[1] + D19 OBUF (Prop_obuf_I_O) 3.545 7.436 r dpy0_OBUF[1]_inst/O + net (fo=0) 0.000 7.436 dpy0[1] + D19 r dpy0[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[1] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.624ns (logic 4.005ns (41.615%) route 5.619ns (58.385%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q + net (fo=1, routed) 5.619 3.759 dpy1_OBUF[1] + D16 OBUF (Prop_obuf_I_O) 3.549 7.308 r dpy1_OBUF[1]_inst/O + net (fo=0) 0.000 7.308 dpy1[1] + D16 r dpy1[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.616ns (logic 3.993ns (41.526%) route 5.623ns (58.474%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.026 -2.316 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.456 -1.860 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q + net (fo=1, routed) 5.623 3.763 dpy1_OBUF[6] + F15 OBUF (Prop_obuf_I_O) 3.537 7.300 r dpy1_OBUF[6]_inst/O + net (fo=0) 0.000 7.300 dpy1[6] + F15 r dpy1[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[0] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.497ns (logic 4.016ns (42.289%) route 5.481ns (57.711%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q + net (fo=1, routed) 5.481 3.622 dpy0_OBUF[0] + B19 OBUF (Prop_obuf_I_O) 3.560 7.182 r dpy0_OBUF[0]_inst/O + net (fo=0) 0.000 7.182 dpy0[0] + B19 r dpy0[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.492ns (logic 4.029ns (42.447%) route 5.463ns (57.553%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q + net (fo=1, routed) 5.463 3.605 dpy0_OBUF[3] + A19 OBUF (Prop_obuf_I_O) 3.573 7.178 r dpy0_OBUF[3]_inst/O + net (fo=0) 0.000 7.178 dpy0[3] + A19 r dpy0[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[2] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.459ns (logic 4.014ns (42.440%) route 5.445ns (57.560%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q + net (fo=1, routed) 5.445 3.586 dpy0_OBUF[2] + B21 OBUF (Prop_obuf_I_O) 3.558 7.144 r dpy0_OBUF[2]_inst/O + net (fo=0) 0.000 7.144 dpy0[2] + B21 r dpy0[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.304ns (logic 4.002ns (43.014%) route 5.302ns (56.986%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.027 -2.315 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.456 -1.859 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q + net (fo=1, routed) 5.302 3.443 dpy0_OBUF[5] + C19 OBUF (Prop_obuf_I_O) 3.546 6.989 r dpy0_OBUF[5]_inst/O + net (fo=0) 0.000 6.989 dpy0[5] + C19 r dpy0[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[3] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.295ns (logic 4.153ns (44.682%) route 5.142ns (55.318%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[3]_lopt_replica/Q + net (fo=1, routed) 5.142 3.243 lopt_9 + D23 OBUF (Prop_obuf_I_O) 3.734 6.977 r leds_OBUF[3]_inst/O + net (fo=0) 0.000 6.977 leds[3] + D23 r leds[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[5] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.093ns (logic 4.145ns (45.587%) route 4.948ns (54.413%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.419 -1.899 r u_confreg/led_data_reg[5]_lopt_replica/Q + net (fo=1, routed) 4.948 3.049 lopt_11 + C21 OBUF (Prop_obuf_I_O) 3.726 6.776 r leds_OBUF[5]_inst/O + net (fo=0) 0.000 6.776 leds[5] + C21 r leds[5] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[6] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 9.051ns (logic 3.998ns (44.165%) route 5.054ns (55.835%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.013 -2.329 u_confreg/sys_clk + SLICE_X0Y78 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.456 -1.873 r u_confreg/led_data_reg[6]_lopt_replica/Q + net (fo=1, routed) 5.054 3.181 lopt_12 + E20 OBUF (Prop_obuf_I_O) 3.542 6.723 r leds_OBUF[6]_inst/O + net (fo=0) 0.000 6.723 leds[6] + E20 r leds[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[11] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.964ns (logic 4.023ns (44.875%) route 4.942ns (55.125%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[11]_lopt_replica/Q + net (fo=1, routed) 4.942 3.080 lopt_2 + A18 OBUF (Prop_obuf_I_O) 3.567 6.647 r leds_OBUF[11]_inst/O + net (fo=0) 0.000 6.647 leds[11] + A18 r leds[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[4]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[4] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.824ns (logic 4.018ns (45.536%) route 4.806ns (54.464%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.013 -2.329 u_confreg/sys_clk + SLICE_X0Y78 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.456 -1.873 r u_confreg/led_data_reg[4]_lopt_replica/Q + net (fo=1, routed) 4.806 2.933 lopt_10 + C22 OBUF (Prop_obuf_I_O) 3.562 6.496 r leds_OBUF[4]_inst/O + net (fo=0) 0.000 6.496 leds[4] + C22 r leds[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[12]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[12] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.644ns (logic 3.998ns (46.258%) route 4.645ns (53.742%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.022 -2.320 u_confreg/sys_clk + SLICE_X0Y85 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y85 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[12]_lopt_replica/Q + net (fo=1, routed) 4.645 2.782 lopt_3 + D20 OBUF (Prop_obuf_I_O) 3.542 6.324 r leds_OBUF[12]_inst/O + net (fo=0) 0.000 6.324 leds[12] + D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -36613,7 +23398,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.566ns (logic 4.003ns (46.730%) route 4.563ns (53.270%)) + Data Path Delay: 8.623ns (logic 4.003ns (46.423%) route 4.620ns (53.577%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36631,51 +23416,16 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C + net (fo=35652, routed) 2.016 -2.326 u_confreg/sys_clk + SLICE_X1Y81 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[10]_lopt_replica/Q - net (fo=1, routed) 4.563 2.700 lopt_1 - D21 OBUF (Prop_obuf_I_O) 3.547 6.247 r leds_OBUF[10]_inst/O - net (fo=0) 0.000 6.247 leds[10] + SLICE_X1Y81 FDRE (Prop_fdre_C_Q) 0.456 -1.870 r u_confreg/led_data_reg[10]_lopt_replica/Q + net (fo=1, routed) 4.620 2.750 lopt_1 + D21 OBUF (Prop_obuf_I_O) 3.547 6.297 r leds_OBUF[10]_inst/O + net (fo=0) 0.000 6.297 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[7] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.730ns (logic 4.001ns (45.828%) route 4.729ns (54.172%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q - net (fo=1, routed) 4.729 2.697 dpy0_OBUF[7] - C17 OBUF (Prop_obuf_I_O) 3.545 6.242 r dpy0_OBUF[7]_inst/O - net (fo=0) 0.000 6.242 dpy0[7] - C17 r dpy0[7] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: u_confreg/led_data_reg[7]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36683,7 +23433,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.548ns (logic 4.164ns (48.712%) route 4.384ns (51.288%)) + Data Path Delay: 8.622ns (logic 4.028ns (46.720%) route 4.594ns (53.280%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36701,86 +23451,16 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C + net (fo=35652, routed) 2.016 -2.326 u_confreg/sys_clk + SLICE_X0Y81 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[7]_lopt_replica/Q - net (fo=1, routed) 4.384 2.489 lopt_13 - B22 OBUF (Prop_obuf_I_O) 3.745 6.234 r leds_OBUF[7]_inst/O - net (fo=0) 0.000 6.234 leds[7] + SLICE_X0Y81 FDRE (Prop_fdre_C_Q) 0.456 -1.870 r u_confreg/led_data_reg[7]_lopt_replica/Q + net (fo=1, routed) 4.594 2.724 lopt_13 + B22 OBUF (Prop_obuf_I_O) 3.572 6.296 r leds_OBUF[7]_inst/O + net (fo=0) 0.000 6.296 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- -Slack: inf - Source: u_confreg/led_data_reg[13]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[13] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.473ns (logic 4.027ns (47.524%) route 4.446ns (52.476%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[13]_lopt_replica/Q - net (fo=1, routed) 4.446 2.588 lopt_4 - A22 OBUF (Prop_obuf_I_O) 3.571 6.159 r leds_OBUF[13]_inst/O - net (fo=0) 0.000 6.159 leds[13] - A22 r leds[13] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[1]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.398ns (logic 3.997ns (47.597%) route 4.401ns (52.403%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[1]_lopt_replica/Q - net (fo=1, routed) 4.401 2.543 lopt_7 - E21 OBUF (Prop_obuf_I_O) 3.541 6.084 r leds_OBUF[1]_inst/O - net (fo=0) 0.000 6.084 leds[1] - E21 r leds[1] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -36788,7 +23468,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Max at Slow Process Corner - Data Path Delay: 8.138ns (logic 4.031ns (49.529%) route 4.108ns (50.471%)) + Data Path Delay: 8.609ns (logic 4.031ns (46.822%) route 4.578ns (53.178%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -36806,16 +23486,51 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C + net (fo=35652, routed) 2.024 -2.318 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[0]_lopt_replica/Q - net (fo=1, routed) 4.108 2.249 lopt - B24 OBUF (Prop_obuf_I_O) 3.575 5.824 r leds_OBUF[0]_inst/O - net (fo=0) 0.000 5.824 leds[0] + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.456 -1.862 r u_confreg/led_data_reg[0]_lopt_replica/Q + net (fo=1, routed) 4.578 2.716 lopt + B24 OBUF (Prop_obuf_I_O) 3.575 6.291 r leds_OBUF[0]_inst/O + net (fo=0) 0.000 6.291 leds[0] B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/led_data_reg[15]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[15] + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.459ns (logic 4.019ns (47.509%) route 4.440ns (52.491%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.020 -2.322 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.456 -1.866 r u_confreg/led_data_reg[15]_lopt_replica/Q + net (fo=1, routed) 4.440 2.575 lopt_6 + B20 OBUF (Prop_obuf_I_O) 3.563 6.138 r leds_OBUF[15]_inst/O + net (fo=0) 0.000 6.138 leds[15] + B20 r leds[15] (OUT) + ------------------------------------------------------------------- ------------------- + @@ -36832,201 +23547,6 @@ Min Delay 0 Endpoints Max Delay Paths -------------------------------------------------------------------------------------- -Slack: inf - Source: dip_sw[8] - (input port) - Destination: u_confreg/s_rdata_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.851ns (logic 1.724ns (14.546%) route 10.127ns (85.454%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.940ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M6 0.000 0.000 r dip_sw[8] (IN) - net (fo=0) 0.000 0.000 dip_sw[8] - M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O - net (fo=1, routed) 9.460 10.936 u_confreg/dip_sw_IBUF[8] - SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.124 11.060 r u_confreg/s_rdata[8]_i_4/O - net (fo=1, routed) 0.667 11.727 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 11.851 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O - net (fo=1, routed) 0.000 11.851 u_confreg/u_int_ctrl_n_23 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C - -Slack: inf - Source: dip_sw[20] - (input port) - Destination: u_confreg/s_rdata_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.647ns (logic 1.723ns (14.794%) route 9.924ns (85.206%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M4 0.000 0.000 r dip_sw[20] (IN) - net (fo=0) 0.000 0.000 dip_sw[20] - M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O - net (fo=1, routed) 9.163 10.638 u_confreg/dip_sw_IBUF[20] - SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.762 r u_confreg/s_rdata[20]_i_4/O - net (fo=1, routed) 0.761 11.523 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 11.647 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O - net (fo=1, routed) 0.000 11.647 u_confreg/u_int_ctrl_n_11 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C - -Slack: inf - Source: dip_sw[13] - (input port) - Destination: u_confreg/s_rdata_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.183ns (logic 1.734ns (15.504%) route 9.449ns (84.496%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K3 0.000 0.000 r dip_sw[13] (IN) - net (fo=0) 0.000 0.000 dip_sw[13] - K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O - net (fo=1, routed) 8.863 10.349 u_confreg/dip_sw_IBUF[13] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.473 r u_confreg/s_rdata[13]_i_4/O - net (fo=1, routed) 0.586 11.059 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 11.183 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O - net (fo=1, routed) 0.000 11.183 u_confreg/u_int_ctrl_n_18 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C - -Slack: inf - Source: dip_sw[1] - (input port) - Destination: u_confreg/s_rdata_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.155ns (logic 1.746ns (15.651%) route 9.409ns (84.349%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J3 0.000 0.000 r dip_sw[1] (IN) - net (fo=0) 0.000 0.000 dip_sw[1] - J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O - net (fo=1, routed) 8.467 9.965 u_confreg/dip_sw_IBUF[1] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.089 r u_confreg/s_rdata[1]_i_4/O - net (fo=1, routed) 0.942 11.031 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 11.155 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O - net (fo=1, routed) 0.000 11.155 u_confreg/u_int_ctrl_n_30 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C - -Slack: inf - Source: dip_sw[11] - (input port) - Destination: u_confreg/s_rdata_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.052ns (logic 1.719ns (15.556%) route 9.333ns (84.444%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.937ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.937ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L7 0.000 0.000 r dip_sw[11] (IN) - net (fo=0) 0.000 0.000 dip_sw[11] - L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O - net (fo=1, routed) 8.677 10.148 u_confreg/dip_sw_IBUF[11] - SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.124 10.272 r u_confreg/s_rdata[11]_i_4/O - net (fo=1, routed) 0.656 10.928 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 11.052 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O - net (fo=1, routed) 0.000 11.052 u_confreg/u_int_ctrl_n_20 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C - Slack: inf Source: dip_sw[25] (input port) @@ -37034,10 +23554,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.711ns (logic 1.737ns (16.220%) route 8.974ns (83.780%)) + Data Path Delay: 12.140ns (logic 1.737ns (14.310%) route 10.403ns (85.690%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns + Clock Path Skew: -1.930ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -37046,12 +23566,12 @@ Slack: inf R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O - net (fo=1, routed) 8.245 9.734 u_confreg/dip_sw_IBUF[25] - SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.124 9.858 r u_confreg/s_rdata[25]_i_4/O - net (fo=1, routed) 0.729 10.587 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 10.711 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O - net (fo=1, routed) 0.000 10.711 u_confreg/u_int_ctrl_n_6 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D + net (fo=1, routed) 9.452 10.941 u_confreg/dip_sw_IBUF[25] + SLICE_X1Y60 LUT5 (Prop_lut5_I4_O) 0.124 11.065 r u_confreg/s_rdata[25]_i_4/O + net (fo=1, routed) 0.951 12.016 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 + SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.124 12.140 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O + net (fo=1, routed) 0.000 12.140 u_confreg/u_int_ctrl_n_6 + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -37063,971 +23583,8 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C - -Slack: inf - Source: dip_sw[19] - (input port) - Destination: u_confreg/s_rdata_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.426ns (logic 1.726ns (16.557%) route 8.700ns (83.443%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.934ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.934ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L4 0.000 0.000 r dip_sw[19] (IN) - net (fo=0) 0.000 0.000 dip_sw[19] - L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O - net (fo=1, routed) 8.546 10.024 u_confreg/dip_sw_IBUF[19] - SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.124 10.148 r u_confreg/s_rdata[19]_i_4/O - net (fo=1, routed) 0.154 10.302 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 - SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.124 10.426 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O - net (fo=1, routed) 0.000 10.426 u_confreg/u_int_ctrl_n_12 - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C - -Slack: inf - Source: touch_btn[2] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.138ns (logic 1.487ns (14.666%) route 8.651ns (85.334%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P3 0.000 0.000 r touch_btn[2] (IN) - net (fo=0) 0.000 0.000 touch_btn[2] - P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O - net (fo=1, routed) 8.651 10.138 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/u_int_ctrl/sys_clk - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C - -Slack: inf - Source: dip_sw[9] - (input port) - Destination: u_confreg/s_rdata_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.432ns (logic 1.718ns (20.372%) route 6.714ns (79.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.938ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.938ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N7 0.000 0.000 r dip_sw[9] (IN) - net (fo=0) 0.000 0.000 dip_sw[9] - N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O - net (fo=1, routed) 6.067 7.537 u_confreg/dip_sw_IBUF[9] - SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.661 r u_confreg/s_rdata[9]_i_4/O - net (fo=1, routed) 0.647 8.308 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 - SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.124 8.432 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O - net (fo=1, routed) 0.000 8.432 u_confreg/u_int_ctrl_n_22 - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.890 -1.938 u_confreg/sys_clk - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C - -Slack: inf - Source: dip_sw[4] - (input port) - Destination: u_confreg/s_rdata_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.408ns (logic 1.736ns (20.649%) route 6.672ns (79.351%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.934ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.934ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P4 0.000 0.000 r dip_sw[4] (IN) - net (fo=0) 0.000 0.000 dip_sw[4] - P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O - net (fo=1, routed) 6.006 7.495 u_confreg/dip_sw_IBUF[4] - SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.124 7.619 r u_confreg/s_rdata[4]_i_4/O - net (fo=1, routed) 0.666 8.284 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 - SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.408 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O - net (fo=1, routed) 0.000 8.408 u_confreg/u_int_ctrl_n_27 - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C - -Slack: inf - Source: dip_sw[10] - (input port) - Destination: u_confreg/s_rdata_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.284ns (logic 1.720ns (20.765%) route 6.564ns (79.235%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M7 0.000 0.000 r dip_sw[10] (IN) - net (fo=0) 0.000 0.000 dip_sw[10] - M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O - net (fo=1, routed) 6.100 7.572 u_confreg/dip_sw_IBUF[10] - SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.696 r u_confreg/s_rdata[10]_i_4/O - net (fo=1, routed) 0.464 8.160 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.284 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O - net (fo=1, routed) 0.000 8.284 u_confreg/u_int_ctrl_n_21 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C - -Slack: inf - Source: dip_sw[23] - (input port) - Destination: u_confreg/s_rdata_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.265ns (logic 1.766ns (21.372%) route 6.499ns (78.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N1 0.000 0.000 r dip_sw[23] (IN) - net (fo=0) 0.000 0.000 dip_sw[23] - N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O - net (fo=1, routed) 5.411 6.929 u_confreg/dip_sw_IBUF[23] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 7.053 r u_confreg/s_rdata[23]_i_4/O - net (fo=1, routed) 1.088 8.141 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 8.265 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O - net (fo=1, routed) 0.000 8.265 u_confreg/u_int_ctrl_n_8 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C - -Slack: inf - Source: dip_sw[5] - (input port) - Destination: u_confreg/s_rdata_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.233ns (logic 1.718ns (20.872%) route 6.515ns (79.128%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L5 0.000 0.000 r dip_sw[5] (IN) - net (fo=0) 0.000 0.000 dip_sw[5] - L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O - net (fo=1, routed) 5.514 6.985 u_confreg/dip_sw_IBUF[5] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.109 r u_confreg/s_rdata[5]_i_4/O - net (fo=1, routed) 1.000 8.109 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.233 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O - net (fo=1, routed) 0.000 8.233 u_confreg/u_int_ctrl_n_26 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C - -Slack: inf - Source: dip_sw[26] - (input port) - Destination: u_confreg/s_rdata_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.161ns (logic 1.757ns (21.535%) route 6.403ns (78.465%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.011ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T4 0.000 0.000 r dip_sw[26] (IN) - net (fo=0) 0.000 0.000 dip_sw[26] - T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O - net (fo=1, routed) 5.313 6.823 u_confreg/dip_sw_IBUF[26] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.947 r u_confreg/s_rdata[26]_i_4/O - net (fo=1, routed) 1.090 8.037 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 8.161 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O - net (fo=1, routed) 0.000 8.161 u_confreg/u_int_ctrl_n_5 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C - -Slack: inf - Source: dip_sw[17] - (input port) - Destination: u_confreg/s_rdata_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.117ns (logic 1.752ns (21.585%) route 6.365ns (78.415%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K1 0.000 0.000 r dip_sw[17] (IN) - net (fo=0) 0.000 0.000 dip_sw[17] - K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O - net (fo=1, routed) 5.516 7.020 u_confreg/dip_sw_IBUF[17] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.144 r u_confreg/s_rdata[17]_i_4/O - net (fo=1, routed) 0.849 7.993 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.117 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O - net (fo=1, routed) 0.000 8.117 u_confreg/u_int_ctrl_n_14 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C - -Slack: inf - Source: dip_sw[2] - (input port) - Destination: u_confreg/s_rdata_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.080ns (logic 1.743ns (21.573%) route 6.337ns (78.427%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M2 0.000 0.000 r dip_sw[2] (IN) - net (fo=0) 0.000 0.000 dip_sw[2] - M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O - net (fo=1, routed) 5.346 6.841 u_confreg/dip_sw_IBUF[2] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.965 r u_confreg/s_rdata[2]_i_4/O - net (fo=1, routed) 0.991 7.956 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.080 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O - net (fo=1, routed) 0.000 8.080 u_confreg/u_int_ctrl_n_29 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C - -Slack: inf - Source: dip_sw[6] - (input port) - Destination: u_confreg/s_rdata_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.077ns (logic 1.736ns (21.494%) route 6.341ns (78.506%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L3 0.000 0.000 r dip_sw[6] (IN) - net (fo=0) 0.000 0.000 dip_sw[6] - L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O - net (fo=1, routed) 5.394 6.882 u_confreg/dip_sw_IBUF[6] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.006 r u_confreg/s_rdata[6]_i_4/O - net (fo=1, routed) 0.947 7.953 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.077 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O - net (fo=1, routed) 0.000 8.077 u_confreg/u_int_ctrl_n_25 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C - -Slack: inf - Source: dip_sw[14] - (input port) - Destination: u_confreg/s_rdata_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.038ns (logic 1.763ns (21.934%) route 6.275ns (78.066%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J1 0.000 0.000 r dip_sw[14] (IN) - net (fo=0) 0.000 0.000 dip_sw[14] - J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O - net (fo=1, routed) 5.331 6.846 u_confreg/dip_sw_IBUF[14] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.970 r u_confreg/s_rdata[14]_i_4/O - net (fo=1, routed) 0.944 7.914 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.038 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O - net (fo=1, routed) 0.000 8.038 u_confreg/u_int_ctrl_n_17 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C - -Slack: inf - Source: dip_sw[15] - (input port) - Destination: u_confreg/s_rdata_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.951ns (logic 1.742ns (21.911%) route 6.209ns (78.089%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L2 0.000 0.000 r dip_sw[15] (IN) - net (fo=0) 0.000 0.000 dip_sw[15] - L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O - net (fo=1, routed) 5.453 6.948 u_confreg/dip_sw_IBUF[15] - SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.124 7.072 r u_confreg/s_rdata[15]_i_4/O - net (fo=1, routed) 0.755 7.827 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.951 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O - net (fo=1, routed) 0.000 7.951 u_confreg/u_int_ctrl_n_16 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C - -Slack: inf - Source: dip_sw[0] - (input port) - Destination: u_confreg/s_rdata_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.807ns (logic 1.743ns (22.326%) route 6.064ns (77.674%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.937ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.937ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T3 0.000 0.000 r dip_sw[0] (IN) - net (fo=0) 0.000 0.000 dip_sw[0] - T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O - net (fo=1, routed) 5.166 6.661 u_confreg/dip_sw_IBUF[0] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.785 r u_confreg/s_rdata[0]_i_4/O - net (fo=1, routed) 0.898 7.683 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 7.807 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O - net (fo=1, routed) 0.000 7.807 u_confreg/u_int_ctrl_n_31 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C - -Slack: inf - Source: dip_sw[3] - (input port) - Destination: u_confreg/s_rdata_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.770ns (logic 1.752ns (22.553%) route 6.018ns (77.447%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.940ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P1 0.000 0.000 r dip_sw[3] (IN) - net (fo=0) 0.000 0.000 dip_sw[3] - P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O - net (fo=1, routed) 5.171 6.676 u_confreg/dip_sw_IBUF[3] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.800 r u_confreg/s_rdata[3]_i_4/O - net (fo=1, routed) 0.846 7.646 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 7.770 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O - net (fo=1, routed) 0.000 7.770 u_confreg/u_int_ctrl_n_28 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C - -Slack: inf - Source: dip_sw[21] - (input port) - Destination: u_confreg/s_rdata_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.691ns (logic 1.736ns (22.574%) route 5.955ns (77.426%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N2 0.000 0.000 r dip_sw[21] (IN) - net (fo=0) 0.000 0.000 dip_sw[21] - N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O - net (fo=1, routed) 5.069 6.557 u_confreg/dip_sw_IBUF[21] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.681 r u_confreg/s_rdata[21]_i_4/O - net (fo=1, routed) 0.886 7.567 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.691 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O - net (fo=1, routed) 0.000 7.691 u_confreg/u_int_ctrl_n_10 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C - -Slack: inf - Source: dip_sw[16] - (input port) - Destination: u_confreg/s_rdata_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.536ns (logic 1.748ns (23.196%) route 5.788ns (76.804%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K2 0.000 0.000 r dip_sw[16] (IN) - net (fo=0) 0.000 0.000 dip_sw[16] - K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O - net (fo=1, routed) 5.492 6.993 u_confreg/dip_sw_IBUF[16] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.117 r u_confreg/s_rdata[16]_i_4/O - net (fo=1, routed) 0.296 7.412 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.536 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O - net (fo=1, routed) 0.000 7.536 u_confreg/u_int_ctrl_n_15 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C - -Slack: inf - Source: dip_sw[24] - (input port) - Destination: u_confreg/s_rdata_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.500ns (logic 1.714ns (22.860%) route 5.785ns (77.140%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P5 0.000 0.000 r dip_sw[24] (IN) - net (fo=0) 0.000 0.000 dip_sw[24] - P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O - net (fo=1, routed) 4.979 6.445 u_confreg/dip_sw_IBUF[24] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.569 r u_confreg/s_rdata[24]_i_4/O - net (fo=1, routed) 0.806 7.376 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.500 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O - net (fo=1, routed) 0.000 7.500 u_confreg/u_int_ctrl_n_7 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C - -Slack: inf - Source: dip_sw[18] - (input port) - Destination: u_confreg/s_rdata_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.469ns (logic 1.737ns (23.257%) route 5.732ns (76.743%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.011ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N3 0.000 0.000 r dip_sw[18] (IN) - net (fo=0) 0.000 0.000 dip_sw[18] - N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O - net (fo=1, routed) 5.052 6.541 u_confreg/dip_sw_IBUF[18] - SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.124 6.665 r u_confreg/s_rdata[18]_i_4/O - net (fo=1, routed) 0.680 7.345 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 7.469 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O - net (fo=1, routed) 0.000 7.469 u_confreg/u_int_ctrl_n_13 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C - -Slack: inf - Source: dip_sw[7] - (input port) - Destination: u_confreg/s_rdata_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.415ns (logic 1.719ns (23.186%) route 5.696ns (76.814%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.933ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.933ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N6 0.000 0.000 r dip_sw[7] (IN) - net (fo=0) 0.000 0.000 dip_sw[7] - N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O - net (fo=1, routed) 5.542 7.013 u_confreg/dip_sw_IBUF[7] - SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.124 7.137 r u_confreg/s_rdata[7]_i_4/O - net (fo=1, routed) 0.154 7.291 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 - SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.124 7.415 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O - net (fo=1, routed) 0.000 7.415 u_confreg/u_int_ctrl_n_24 - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.895 -1.933 u_confreg/sys_clk - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C - -Slack: inf - Source: dip_sw[12] - (input port) - Destination: u_confreg/s_rdata_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.331ns (logic 1.717ns (23.423%) route 5.614ns (76.577%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M5 0.000 0.000 r dip_sw[12] (IN) - net (fo=0) 0.000 0.000 dip_sw[12] - M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O - net (fo=1, routed) 5.177 6.646 u_confreg/dip_sw_IBUF[12] - SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.124 6.770 r u_confreg/s_rdata[12]_i_4/O - net (fo=1, routed) 0.437 7.207 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 7.331 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O - net (fo=1, routed) 0.000 7.331 u_confreg/u_int_ctrl_n_19 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C - -Slack: inf - Source: dip_sw[30] - (input port) - Destination: u_confreg/s_rdata_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.316ns (logic 1.707ns (23.334%) route 5.609ns (76.666%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R6 0.000 0.000 r dip_sw[30] (IN) - net (fo=0) 0.000 0.000 dip_sw[30] - R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O - net (fo=1, routed) 4.515 5.975 u_confreg/dip_sw_IBUF[30] - SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.099 r u_confreg/s_rdata[30]_i_4/O - net (fo=1, routed) 1.093 7.192 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.316 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O - net (fo=1, routed) 0.000 7.316 u_confreg/u_int_ctrl_n_1 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C - -Slack: inf - Source: dip_sw[29] - (input port) - Destination: u_confreg/s_rdata_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.273ns (logic 1.726ns (23.732%) route 5.547ns (76.268%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T5 0.000 0.000 r dip_sw[29] (IN) - net (fo=0) 0.000 0.000 dip_sw[29] - T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O - net (fo=1, routed) 4.537 6.015 u_confreg/dip_sw_IBUF[29] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.139 r u_confreg/s_rdata[29]_i_4/O - net (fo=1, routed) 1.010 7.149 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.273 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O - net (fo=1, routed) 0.000 7.273 u_confreg/u_int_ctrl_n_2 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C - -Slack: inf - Source: touch_btn[3] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.267ns (logic 1.513ns (20.816%) route 5.755ns (79.184%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -1.938ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.938ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - U2 0.000 0.000 r touch_btn[3] (IN) - net (fo=0) 0.000 0.000 touch_btn[3] - U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O - net (fo=1, routed) 5.755 7.267 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.890 -1.938 u_confreg/u_int_ctrl/sys_clk - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C - -Slack: inf - Source: touch_btn[1] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.239ns (logic 1.515ns (20.930%) route 5.724ns (79.070%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -2.009ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M1 0.000 0.000 r touch_btn[1] (IN) - net (fo=0) 0.000 0.000 touch_btn[1] - M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O - net (fo=1, routed) 5.724 7.239 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C + net (fo=35652, routed) 1.898 -1.930 u_confreg/sys_clk + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/C Slack: inf Source: dip_sw[28] @@ -38036,10 +23593,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.116ns (logic 1.716ns (24.110%) route 5.400ns (75.890%)) + Data Path Delay: 11.642ns (logic 1.716ns (14.736%) route 9.927ns (85.264%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns + Clock Path Skew: -1.928ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38048,12 +23605,12 @@ Slack: inf R5 0.000 0.000 r dip_sw[28] (IN) net (fo=0) 0.000 0.000 dip_sw[28] R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O - net (fo=1, routed) 4.960 6.427 u_confreg/dip_sw_IBUF[28] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.551 r u_confreg/s_rdata[28]_i_4/O - net (fo=1, routed) 0.440 6.992 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.116 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O - net (fo=1, routed) 0.000 7.116 u_confreg/u_int_ctrl_n_3 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D + net (fo=1, routed) 8.694 10.162 u_confreg/dip_sw_IBUF[28] + SLICE_X12Y58 LUT5 (Prop_lut5_I4_O) 0.124 10.286 r u_confreg/s_rdata[28]_i_4/O + net (fo=1, routed) 1.232 11.518 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 + SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.124 11.642 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O + net (fo=1, routed) 0.000 11.642 u_confreg/u_int_ctrl_n_3 + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38065,86 +23622,8 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C - -Slack: inf - Source: dip_sw[22] - (input port) - Destination: u_confreg/s_rdata_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.094ns (logic 1.710ns (24.108%) route 5.384ns (75.892%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P6 0.000 0.000 r dip_sw[22] (IN) - net (fo=0) 0.000 0.000 dip_sw[22] - P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O - net (fo=1, routed) 4.542 6.004 u_confreg/dip_sw_IBUF[22] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.128 r u_confreg/s_rdata[22]_i_4/O - net (fo=1, routed) 0.842 6.970 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 - SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.094 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O - net (fo=1, routed) 0.000 7.094 u_confreg/u_int_ctrl_n_9 - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.945ns (logic 1.963ns (28.269%) route 4.982ns (71.731%)) - Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) - Clock Path Skew: -1.929ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.929ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.683 6.191 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.372 6.563 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O - net (fo=1, routed) 0.382 6.945 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C + net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: dip_sw[27] @@ -38153,10 +23632,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.892ns (logic 1.753ns (25.432%) route 5.139ns (74.568%)) + Data Path Delay: 11.213ns (logic 1.753ns (15.632%) route 9.460ns (84.368%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns + Clock Path Skew: -1.930ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.930ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38165,12 +23644,12 @@ Slack: inf R1 0.000 0.000 r dip_sw[27] (IN) net (fo=0) 0.000 0.000 dip_sw[27] R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O - net (fo=1, routed) 4.238 5.743 u_confreg/dip_sw_IBUF[27] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 5.867 r u_confreg/s_rdata[27]_i_4/O - net (fo=1, routed) 0.902 6.768 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.892 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O - net (fo=1, routed) 0.000 6.892 u_confreg/u_int_ctrl_n_4 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D + net (fo=1, routed) 8.793 10.298 u_confreg/dip_sw_IBUF[27] + SLICE_X5Y58 LUT5 (Prop_lut5_I4_O) 0.124 10.422 r u_confreg/s_rdata[27]_i_4/O + net (fo=1, routed) 0.667 11.089 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 + SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.124 11.213 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O + net (fo=1, routed) 0.000 11.213 u_confreg/u_int_ctrl_n_4 + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38182,8 +23661,242 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C + net (fo=35652, routed) 1.898 -1.930 u_confreg/sys_clk + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/C + +Slack: inf + Source: dip_sw[7] + (input port) + Destination: u_confreg/s_rdata_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 11.208ns (logic 1.719ns (15.340%) route 9.489ns (84.660%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.927ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.927ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N6 0.000 0.000 r dip_sw[7] (IN) + net (fo=0) 0.000 0.000 dip_sw[7] + N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O + net (fo=1, routed) 8.842 10.313 u_confreg/dip_sw_IBUF[7] + SLICE_X3Y56 LUT5 (Prop_lut5_I4_O) 0.124 10.437 r u_confreg/s_rdata[7]_i_4/O + net (fo=1, routed) 0.647 11.084 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 + SLICE_X3Y56 LUT6 (Prop_lut6_I4_O) 0.124 11.208 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O + net (fo=1, routed) 0.000 11.208 u_confreg/u_int_ctrl_n_24 + SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk + SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/C + +Slack: inf + Source: dip_sw[4] + (input port) + Destination: u_confreg/s_rdata_reg[4]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 11.066ns (logic 1.736ns (15.690%) route 9.330ns (84.310%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.927ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.927ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P4 0.000 0.000 r dip_sw[4] (IN) + net (fo=0) 0.000 0.000 dip_sw[4] + P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O + net (fo=1, routed) 8.159 9.647 u_confreg/dip_sw_IBUF[4] + SLICE_X0Y59 LUT5 (Prop_lut5_I4_O) 0.124 9.771 r u_confreg/s_rdata[4]_i_4/O + net (fo=1, routed) 1.171 10.942 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 + SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.124 11.066 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O + net (fo=1, routed) 0.000 11.066 u_confreg/u_int_ctrl_n_27 + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/C + +Slack: inf + Source: dip_sw[22] + (input port) + Destination: u_confreg/s_rdata_reg[22]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 10.666ns (logic 1.710ns (16.036%) route 8.955ns (83.964%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.009ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.009ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P6 0.000 0.000 r dip_sw[22] (IN) + net (fo=0) 0.000 0.000 dip_sw[22] + P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O + net (fo=1, routed) 8.551 10.013 u_confreg/dip_sw_IBUF[22] + SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.124 10.137 r u_confreg/s_rdata[22]_i_4/O + net (fo=1, routed) 0.405 10.542 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 10.666 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O + net (fo=1, routed) 0.000 10.666 u_confreg/u_int_ctrl_n_9 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/C + +Slack: inf + Source: dip_sw[30] + (input port) + Destination: u_confreg/s_rdata_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 10.527ns (logic 1.707ns (16.216%) route 8.820ns (83.784%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.009ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.009ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + R6 0.000 0.000 r dip_sw[30] (IN) + net (fo=0) 0.000 0.000 dip_sw[30] + R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O + net (fo=1, routed) 8.530 9.989 u_confreg/dip_sw_IBUF[30] + SLICE_X9Y60 LUT5 (Prop_lut5_I4_O) 0.124 10.113 r u_confreg/s_rdata[30]_i_4/O + net (fo=1, routed) 0.290 10.403 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 10.527 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O + net (fo=1, routed) 0.000 10.527 u_confreg/u_int_ctrl_n_1 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/C + +Slack: inf + Source: dip_sw[18] + (input port) + Destination: u_confreg/s_rdata_reg[18]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 10.249ns (logic 1.737ns (16.949%) route 8.512ns (83.051%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.007ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.007ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N3 0.000 0.000 r dip_sw[18] (IN) + net (fo=0) 0.000 0.000 dip_sw[18] + N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O + net (fo=1, routed) 7.712 9.201 u_confreg/dip_sw_IBUF[18] + SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.124 9.325 r u_confreg/s_rdata[18]_i_4/O + net (fo=1, routed) 0.800 10.125 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 + SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.124 10.249 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O + net (fo=1, routed) 0.000 10.249 u_confreg/u_int_ctrl_n_13 + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/C + +Slack: inf + Source: dip_sw[21] + (input port) + Destination: u_confreg/s_rdata_reg[21]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 10.165ns (logic 1.736ns (17.081%) route 8.428ns (82.919%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.007ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.007ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N2 0.000 0.000 r dip_sw[21] (IN) + net (fo=0) 0.000 0.000 dip_sw[21] + N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O + net (fo=1, routed) 8.090 9.578 u_confreg/dip_sw_IBUF[21] + SLICE_X12Y56 LUT5 (Prop_lut5_I4_O) 0.124 9.702 r u_confreg/s_rdata[21]_i_4/O + net (fo=1, routed) 0.339 10.041 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 + SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.124 10.165 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O + net (fo=1, routed) 0.000 10.165 u_confreg/u_int_ctrl_n_10 + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf Source: dip_sw[31] @@ -38192,10 +23905,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.857ns (logic 1.742ns (25.399%) route 5.116ns (74.601%)) + Data Path Delay: 10.112ns (logic 1.742ns (17.224%) route 8.370ns (82.776%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns + Clock Path Skew: -2.009ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.009ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38204,12 +23917,12 @@ Slack: inf R2 0.000 0.000 r dip_sw[31] (IN) net (fo=0) 0.000 0.000 dip_sw[31] R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O - net (fo=1, routed) 4.636 6.130 u_confreg/dip_sw_IBUF[31] - SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.254 r u_confreg/s_rdata[31]_i_6/O - net (fo=1, routed) 0.480 6.733 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.857 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O - net (fo=1, routed) 0.000 6.857 u_confreg/u_int_ctrl_n_0 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D + net (fo=1, routed) 8.072 9.566 u_confreg/dip_sw_IBUF[31] + SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.124 9.690 r u_confreg/s_rdata[31]_i_6/O + net (fo=1, routed) 0.298 9.988 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 10.112 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O + net (fo=1, routed) 0.000 10.112 u_confreg/u_int_ctrl_n_0 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38221,84 +23934,8 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.182ns (logic 1.939ns (31.371%) route 4.243ns (68.629%)) - Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.326 5.834 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.348 6.182 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O - net (fo=1, routed) 0.000 6.182 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.135ns (logic 1.598ns (26.054%) route 4.537ns (73.946%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -1.929ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.929ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 r UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.124 5.515 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O - net (fo=1, routed) 0.620 6.135 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf Source: touch_btn[0] @@ -38307,10 +23944,10 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.929ns (logic 1.499ns (25.283%) route 4.430ns (74.717%)) + Data Path Delay: 9.728ns (logic 1.499ns (15.408%) route 8.229ns (84.592%)) Logic Levels: 1 (IBUF=1) - Clock Path Skew: -2.009ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns + Clock Path Skew: -2.008ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.008ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns @@ -38319,8 +23956,8 @@ Slack: inf T2 0.000 0.000 r touch_btn[0] (IN) net (fo=0) 0.000 0.000 touch_btn[0] T2 IBUF (Prop_ibuf_I_O) 1.499 1.499 r touch_btn_IBUF[0]_inst/O - net (fo=1, routed) 4.430 5.929 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + net (fo=1, routed) 8.229 9.728 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] + SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38332,69 +23969,34 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + net (fo=35652, routed) 1.820 -2.008 u_confreg/u_int_ctrl/sys_clk + SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C Slack: inf - Source: UART_RX + Source: dip_sw[26] (input port) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.784ns (logic 1.590ns (27.483%) route 4.194ns (72.517%)) - Logic Levels: 2 (IBUF=1 LUT4=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J20 0.000 0.000 r UART_RX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_RX_IOBUF_inst/IO - J20 IBUF (Prop_ibuf_I_O) 1.466 1.466 r UART_RX_IOBUF_inst/IBUF/O - net (fo=1, routed) 4.194 5.660 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF - SLICE_X1Y61 LUT4 (Prop_lut4_I3_O) 0.124 5.784 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O - net (fo=1, routed) 0.000 5.784 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + Destination: u_confreg/s_rdata_reg[26]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.395ns (logic 1.598ns (29.628%) route 3.796ns (70.372%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns + Data Path Delay: 9.706ns (logic 1.757ns (18.105%) route 7.949ns (81.895%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.928ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.796 5.271 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF - SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.124 5.395 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O - net (fo=1, routed) 0.000 5.395 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + T4 0.000 0.000 r dip_sw[26] (IN) + net (fo=0) 0.000 0.000 dip_sw[26] + T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O + net (fo=1, routed) 7.304 8.813 u_confreg/dip_sw_IBUF[26] + SLICE_X1Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.937 r u_confreg/s_rdata[26]_i_4/O + net (fo=1, routed) 0.645 9.582 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 + SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.706 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O + net (fo=1, routed) 0.000 9.706 u_confreg/u_int_ctrl_n_5 + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38406,8 +24008,546 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C + net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/C + +Slack: inf + Source: dip_sw[1] + (input port) + Destination: u_confreg/s_rdata_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.635ns (logic 1.746ns (18.119%) route 7.890ns (81.881%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.928ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J3 0.000 0.000 r dip_sw[1] (IN) + net (fo=0) 0.000 0.000 dip_sw[1] + J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O + net (fo=1, routed) 7.101 8.599 u_confreg/dip_sw_IBUF[1] + SLICE_X5Y51 LUT5 (Prop_lut5_I4_O) 0.124 8.723 r u_confreg/s_rdata[1]_i_4/O + net (fo=1, routed) 0.789 9.511 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 + SLICE_X5Y50 LUT6 (Prop_lut6_I4_O) 0.124 9.635 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O + net (fo=1, routed) 0.000 9.635 u_confreg/u_int_ctrl_n_30 + SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk + SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/C + +Slack: inf + Source: touch_btn[3] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.625ns (logic 1.513ns (15.717%) route 8.112ns (84.283%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -2.009ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.009ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + U2 0.000 0.000 r touch_btn[3] (IN) + net (fo=0) 0.000 0.000 touch_btn[3] + U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O + net (fo=1, routed) 8.112 9.625 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] + SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk + SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C + +Slack: inf + Source: dip_sw[3] + (input port) + Destination: u_confreg/s_rdata_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.596ns (logic 1.752ns (18.262%) route 7.843ns (81.738%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.928ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P1 0.000 0.000 r dip_sw[3] (IN) + net (fo=0) 0.000 0.000 dip_sw[3] + P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O + net (fo=1, routed) 7.682 9.186 u_confreg/dip_sw_IBUF[3] + SLICE_X4Y51 LUT5 (Prop_lut5_I4_O) 0.124 9.310 r u_confreg/s_rdata[3]_i_4/O + net (fo=1, routed) 0.162 9.472 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 + SLICE_X4Y51 LUT6 (Prop_lut6_I4_O) 0.124 9.596 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O + net (fo=1, routed) 0.000 9.596 u_confreg/u_int_ctrl_n_28 + SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk + SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/C + +Slack: inf + Source: dip_sw[12] + (input port) + Destination: u_confreg/s_rdata_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.409ns (logic 1.717ns (18.250%) route 7.692ns (81.750%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.007ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.007ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M5 0.000 0.000 r dip_sw[12] (IN) + net (fo=0) 0.000 0.000 dip_sw[12] + M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O + net (fo=1, routed) 6.895 8.364 u_confreg/dip_sw_IBUF[12] + SLICE_X14Y57 LUT5 (Prop_lut5_I4_O) 0.124 8.488 r u_confreg/s_rdata[12]_i_4/O + net (fo=1, routed) 0.797 9.285 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 + SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.124 9.409 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O + net (fo=1, routed) 0.000 9.409 u_confreg/u_int_ctrl_n_19 + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/C + +Slack: inf + Source: dip_sw[20] + (input port) + Destination: u_confreg/s_rdata_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.377ns (logic 1.723ns (18.375%) route 7.654ns (81.625%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.928ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M4 0.000 0.000 r dip_sw[20] (IN) + net (fo=0) 0.000 0.000 dip_sw[20] + M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O + net (fo=1, routed) 7.206 8.681 u_confreg/dip_sw_IBUF[20] + SLICE_X1Y61 LUT5 (Prop_lut5_I4_O) 0.124 8.805 r u_confreg/s_rdata[20]_i_4/O + net (fo=1, routed) 0.448 9.253 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 + SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.377 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O + net (fo=1, routed) 0.000 9.377 u_confreg/u_int_ctrl_n_11 + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/C + +Slack: inf + Source: touch_btn[1] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.363ns (logic 1.515ns (16.181%) route 7.848ns (83.819%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -2.010ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.010ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M1 0.000 0.000 r touch_btn[1] (IN) + net (fo=0) 0.000 0.000 touch_btn[1] + M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O + net (fo=1, routed) 7.848 9.363 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] + SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.818 -2.010 u_confreg/u_int_ctrl/sys_clk + SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C + +Slack: inf + Source: dip_sw[8] + (input port) + Destination: u_confreg/s_rdata_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.225ns (logic 1.724ns (18.686%) route 7.501ns (81.314%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.005ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.005ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M6 0.000 0.000 r dip_sw[8] (IN) + net (fo=0) 0.000 0.000 dip_sw[8] + M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O + net (fo=1, routed) 6.702 8.178 u_confreg/dip_sw_IBUF[8] + SLICE_X11Y54 LUT5 (Prop_lut5_I4_O) 0.124 8.302 r u_confreg/s_rdata[8]_i_4/O + net (fo=1, routed) 0.799 9.101 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 + SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.124 9.225 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O + net (fo=1, routed) 0.000 9.225 u_confreg/u_int_ctrl_n_23 + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.823 -2.005 u_confreg/sys_clk + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/C + +Slack: inf + Source: dip_sw[17] + (input port) + Destination: u_confreg/s_rdata_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.190ns (logic 1.752ns (19.066%) route 7.438ns (80.934%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.928ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.928ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K1 0.000 0.000 r dip_sw[17] (IN) + net (fo=0) 0.000 0.000 dip_sw[17] + K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O + net (fo=1, routed) 6.773 8.277 u_confreg/dip_sw_IBUF[17] + SLICE_X3Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.401 r u_confreg/s_rdata[17]_i_4/O + net (fo=1, routed) 0.665 9.066 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 + SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.190 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O + net (fo=1, routed) 0.000 9.190 u_confreg/u_int_ctrl_n_14 + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.900 -1.928 u_confreg/sys_clk + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/C + +Slack: inf + Source: dip_sw[23] + (input port) + Destination: u_confreg/s_rdata_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.174ns (logic 1.766ns (19.255%) route 7.407ns (80.745%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.009ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.009ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N1 0.000 0.000 r dip_sw[23] (IN) + net (fo=0) 0.000 0.000 dip_sw[23] + N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O + net (fo=1, routed) 6.395 7.913 u_confreg/dip_sw_IBUF[23] + SLICE_X15Y60 LUT5 (Prop_lut5_I4_O) 0.124 8.037 r u_confreg/s_rdata[23]_i_4/O + net (fo=1, routed) 1.013 9.050 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.124 9.174 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O + net (fo=1, routed) 0.000 9.174 u_confreg/u_int_ctrl_n_8 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.819 -2.009 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/C + +Slack: inf + Source: dip_sw[2] + (input port) + Destination: u_confreg/s_rdata_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.173ns (logic 1.743ns (19.002%) route 7.430ns (80.998%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.927ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.927ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M2 0.000 0.000 r dip_sw[2] (IN) + net (fo=0) 0.000 0.000 dip_sw[2] + M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O + net (fo=1, routed) 6.469 7.964 u_confreg/dip_sw_IBUF[2] + SLICE_X2Y56 LUT5 (Prop_lut5_I4_O) 0.124 8.088 r u_confreg/s_rdata[2]_i_4/O + net (fo=1, routed) 0.961 9.049 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 + SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.124 9.173 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O + net (fo=1, routed) 0.000 9.173 u_confreg/u_int_ctrl_n_29 + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/C + +Slack: inf + Source: dip_sw[9] + (input port) + Destination: u_confreg/s_rdata_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.158ns (logic 1.718ns (18.757%) route 7.440ns (81.243%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.007ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.007ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N7 0.000 0.000 r dip_sw[9] (IN) + net (fo=0) 0.000 0.000 dip_sw[9] + N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O + net (fo=1, routed) 6.889 8.359 u_confreg/dip_sw_IBUF[9] + SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.124 8.483 r u_confreg/s_rdata[9]_i_4/O + net (fo=1, routed) 0.551 9.034 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 + SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.124 9.158 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O + net (fo=1, routed) 0.000 9.158 u_confreg/u_int_ctrl_n_22 + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/C + +Slack: inf + Source: dip_sw[24] + (input port) + Destination: u_confreg/s_rdata_reg[24]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.072ns (logic 1.714ns (18.898%) route 7.358ns (81.102%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.008ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.008ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P5 0.000 0.000 r dip_sw[24] (IN) + net (fo=0) 0.000 0.000 dip_sw[24] + P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O + net (fo=1, routed) 6.951 8.417 u_confreg/dip_sw_IBUF[24] + SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.541 r u_confreg/s_rdata[24]_i_4/O + net (fo=1, routed) 0.407 8.948 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 + SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.124 9.072 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O + net (fo=1, routed) 0.000 9.072 u_confreg/u_int_ctrl_n_7 + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.820 -2.008 u_confreg/sys_clk + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/C + +Slack: inf + Source: dip_sw[5] + (input port) + Destination: u_confreg/s_rdata_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.066ns (logic 1.718ns (18.955%) route 7.347ns (81.045%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.926ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.926ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L5 0.000 0.000 r dip_sw[5] (IN) + net (fo=0) 0.000 0.000 dip_sw[5] + L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O + net (fo=1, routed) 7.193 8.663 u_confreg/dip_sw_IBUF[5] + SLICE_X3Y52 LUT5 (Prop_lut5_I4_O) 0.124 8.787 r u_confreg/s_rdata[5]_i_4/O + net (fo=1, routed) 0.154 8.942 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 + SLICE_X3Y52 LUT6 (Prop_lut6_I4_O) 0.124 9.066 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O + net (fo=1, routed) 0.000 9.066 u_confreg/u_int_ctrl_n_26 + SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.902 -1.926 u_confreg/sys_clk + SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/C + +Slack: inf + Source: dip_sw[15] + (input port) + Destination: u_confreg/s_rdata_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.052ns (logic 1.742ns (19.246%) route 7.310ns (80.754%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.927ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.927ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L2 0.000 0.000 r dip_sw[15] (IN) + net (fo=0) 0.000 0.000 dip_sw[15] + L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O + net (fo=1, routed) 6.630 8.124 u_confreg/dip_sw_IBUF[15] + SLICE_X2Y53 LUT5 (Prop_lut5_I4_O) 0.124 8.248 r u_confreg/s_rdata[15]_i_4/O + net (fo=1, routed) 0.680 8.928 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 + SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.124 9.052 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O + net (fo=1, routed) 0.000 9.052 u_confreg/u_int_ctrl_n_16 + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED @@ -38416,7 +24556,7 @@ Slack: inf (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) + Data Path Delay: 9.038ns (logic 0.124ns (1.372%) route 8.914ns (98.628%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -38426,10 +24566,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR + net (fo=1, routed) 8.281 8.281 pll_clk.u_rst_sys/locked + SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.124 8.405 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.633 9.038 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38441,8 +24581,8 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C + net (fo=35652, routed) 1.720 -2.108 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C Slack: inf Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED @@ -38451,7 +24591,7 @@ Slack: inf (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) + Data Path Delay: 9.038ns (logic 0.124ns (1.372%) route 8.914ns (98.628%)) Logic Levels: 1 (LUT1=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -38461,10 +24601,10 @@ Slack: inf Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR + net (fo=1, routed) 8.281 8.281 pll_clk.u_rst_sys/locked + SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.124 8.405 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.633 9.038 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -38476,8 +24616,583 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.720 -2.108 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + +Slack: inf + Source: dip_sw[10] + (input port) + Destination: u_confreg/s_rdata_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 9.021ns (logic 1.720ns (19.069%) route 7.301ns (80.931%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.830ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.830ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M7 0.000 0.000 r dip_sw[10] (IN) + net (fo=0) 0.000 0.000 dip_sw[10] + M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O + net (fo=1, routed) 7.136 8.608 u_confreg/dip_sw_IBUF[10] + SLICE_X10Y49 LUT5 (Prop_lut5_I4_O) 0.124 8.732 r u_confreg/s_rdata[10]_i_4/O + net (fo=1, routed) 0.165 8.897 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 + SLICE_X10Y49 LUT6 (Prop_lut6_I4_O) 0.124 9.021 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O + net (fo=1, routed) 0.000 9.021 u_confreg/u_int_ctrl_n_21 + SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.999 -1.830 u_confreg/sys_clk + SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/C + +Slack: inf + Source: dip_sw[19] + (input port) + Destination: u_confreg/s_rdata_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.878ns (logic 1.726ns (19.444%) route 7.152ns (80.556%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.008ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.008ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L4 0.000 0.000 r dip_sw[19] (IN) + net (fo=0) 0.000 0.000 dip_sw[19] + L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O + net (fo=1, routed) 6.997 8.476 u_confreg/dip_sw_IBUF[19] + SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.124 8.600 r u_confreg/s_rdata[19]_i_4/O + net (fo=1, routed) 0.154 8.754 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 + SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.124 8.878 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O + net (fo=1, routed) 0.000 8.878 u_confreg/u_int_ctrl_n_12 + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.820 -2.008 u_confreg/sys_clk + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/C + +Slack: inf + Source: dip_sw[14] + (input port) + Destination: u_confreg/s_rdata_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.788ns (logic 1.763ns (20.063%) route 7.024ns (79.937%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.927ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.927ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J1 0.000 0.000 r dip_sw[14] (IN) + net (fo=0) 0.000 0.000 dip_sw[14] + J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O + net (fo=1, routed) 6.870 8.385 u_confreg/dip_sw_IBUF[14] + SLICE_X1Y53 LUT5 (Prop_lut5_I4_O) 0.124 8.509 r u_confreg/s_rdata[14]_i_4/O + net (fo=1, routed) 0.154 8.664 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 + SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.124 8.788 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O + net (fo=1, routed) 0.000 8.788 u_confreg/u_int_ctrl_n_17 + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/C + +Slack: inf + Source: dip_sw[6] + (input port) + Destination: u_confreg/s_rdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.778ns (logic 1.736ns (19.777%) route 7.042ns (80.223%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.007ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.007ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L3 0.000 0.000 r dip_sw[6] (IN) + net (fo=0) 0.000 0.000 dip_sw[6] + L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O + net (fo=1, routed) 6.227 7.715 u_confreg/dip_sw_IBUF[6] + SLICE_X8Y59 LUT5 (Prop_lut5_I4_O) 0.124 7.839 r u_confreg/s_rdata[6]_i_4/O + net (fo=1, routed) 0.815 8.654 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 + SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.124 8.778 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O + net (fo=1, routed) 0.000 8.778 u_confreg/u_int_ctrl_n_25 + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/C + +Slack: inf + Source: touch_btn[2] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.774ns (logic 1.487ns (16.947%) route 7.287ns (83.053%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -2.011ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.011ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P3 0.000 0.000 r touch_btn[2] (IN) + net (fo=0) 0.000 0.000 touch_btn[2] + P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O + net (fo=1, routed) 7.287 8.774 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] + SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.817 -2.011 u_confreg/u_int_ctrl/sys_clk + SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C + +Slack: inf + Source: dip_sw[0] + (input port) + Destination: u_confreg/s_rdata_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.755ns (logic 1.743ns (19.910%) route 7.012ns (80.090%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.007ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.007ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T3 0.000 0.000 r dip_sw[0] (IN) + net (fo=0) 0.000 0.000 dip_sw[0] + T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O + net (fo=1, routed) 6.342 7.837 u_confreg/dip_sw_IBUF[0] + SLICE_X8Y54 LUT5 (Prop_lut5_I4_O) 0.124 7.961 r u_confreg/s_rdata[0]_i_4/O + net (fo=1, routed) 0.669 8.631 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 + SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.124 8.755 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O + net (fo=1, routed) 0.000 8.755 u_confreg/u_int_ctrl_n_31 + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.821 -2.007 u_confreg/sys_clk + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/C + +Slack: inf + Source: dip_sw[11] + (input port) + Destination: u_confreg/s_rdata_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.713ns (logic 1.719ns (19.731%) route 6.994ns (80.269%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.006ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.006ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L7 0.000 0.000 r dip_sw[11] (IN) + net (fo=0) 0.000 0.000 dip_sw[11] + L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O + net (fo=1, routed) 6.840 8.311 u_confreg/dip_sw_IBUF[11] + SLICE_X9Y51 LUT5 (Prop_lut5_I4_O) 0.124 8.435 r u_confreg/s_rdata[11]_i_4/O + net (fo=1, routed) 0.154 8.589 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 + SLICE_X9Y51 LUT6 (Prop_lut6_I4_O) 0.124 8.713 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O + net (fo=1, routed) 0.000 8.713 u_confreg/u_int_ctrl_n_20 + SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.822 -2.006 u_confreg/sys_clk + SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/C + +Slack: inf + Source: dip_sw[13] + (input port) + Destination: u_confreg/s_rdata_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.663ns (logic 1.734ns (20.014%) route 6.929ns (79.986%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -2.005ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -2.005ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K3 0.000 0.000 r dip_sw[13] (IN) + net (fo=0) 0.000 0.000 dip_sw[13] + K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O + net (fo=1, routed) 6.526 8.012 u_confreg/dip_sw_IBUF[13] + SLICE_X10Y52 LUT5 (Prop_lut5_I4_O) 0.124 8.136 r u_confreg/s_rdata[13]_i_4/O + net (fo=1, routed) 0.403 8.539 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 + SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.124 8.663 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O + net (fo=1, routed) 0.000 8.663 u_confreg/u_int_ctrl_n_18 + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.823 -2.005 u_confreg/sys_clk + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/C + +Slack: inf + Source: dip_sw[16] + (input port) + Destination: u_confreg/s_rdata_reg[16]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 8.477ns (logic 1.748ns (20.621%) route 6.729ns (79.379%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.927ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.927ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K2 0.000 0.000 r dip_sw[16] (IN) + net (fo=0) 0.000 0.000 dip_sw[16] + K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O + net (fo=1, routed) 6.325 7.825 u_confreg/dip_sw_IBUF[16] + SLICE_X1Y56 LUT5 (Prop_lut5_I4_O) 0.124 7.949 r u_confreg/s_rdata[16]_i_4/O + net (fo=1, routed) 0.405 8.353 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 + SLICE_X1Y54 LUT6 (Prop_lut6_I4_O) 0.124 8.477 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O + net (fo=1, routed) 0.000 8.477 u_confreg/u_int_ctrl_n_15 + SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.901 -1.927 u_confreg/sys_clk + SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.372ns (logic 1.978ns (26.838%) route 5.393ns (73.162%)) + Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) + Clock Path Skew: -1.753ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.753ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 4.394 5.868 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.150 6.018 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.999 7.018 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X1Y39 LUT5 (Prop_lut5_I1_O) 0.354 7.372 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O + net (fo=1, routed) 0.000 7.372 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.076 -1.753 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C + +Slack: inf + Source: dip_sw[29] + (input port) + Destination: u_confreg/s_rdata_reg[29]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 7.370ns (logic 1.726ns (23.422%) route 5.644ns (76.578%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -1.931ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.931ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T5 0.000 0.000 r dip_sw[29] (IN) + net (fo=0) 0.000 0.000 dip_sw[29] + T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O + net (fo=1, routed) 5.492 6.970 u_confreg/dip_sw_IBUF[29] + SLICE_X5Y59 LUT5 (Prop_lut5_I4_O) 0.124 7.094 r u_confreg/s_rdata[29]_i_4/O + net (fo=1, routed) 0.151 7.246 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 + SLICE_X5Y59 LUT6 (Prop_lut6_I4_O) 0.124 7.370 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O + net (fo=1, routed) 0.000 7.370 u_confreg/u_int_ctrl_n_2 + SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.897 -1.931 u_confreg/sys_clk + SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.649ns (logic 1.950ns (29.333%) route 4.699ns (70.667%)) + Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) + Clock Path Skew: -1.753ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.753ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 4.394 5.868 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.150 6.018 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.305 6.323 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X1Y39 LUT6 (Prop_lut6_I2_O) 0.326 6.649 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O + net (fo=1, routed) 0.000 6.649 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.076 -1.753 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 6.111ns (logic 1.598ns (26.155%) route 4.513ns (73.845%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -1.753ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.753ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 4.513 5.987 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF + SLICE_X1Y39 LUT5 (Prop_lut5_I2_O) 0.124 6.111 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O + net (fo=1, routed) 0.000 6.111 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.076 -1.753 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.992ns (logic 1.598ns (26.673%) route 4.394ns (73.327%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -1.754ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.754ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 r UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 4.394 5.868 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT5 (Prop_lut5_I0_O) 0.124 5.992 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O + net (fo=1, routed) 0.000 5.992 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 + SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.075 -1.754 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + +Slack: inf + Source: UART_RX + (input port) + Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Setup (Max at Slow Process Corner) + Data Path Delay: 5.968ns (logic 1.590ns (26.636%) route 4.378ns (73.364%)) + Logic Levels: 2 (IBUF=1 LUT4=1) + Clock Path Skew: -1.752ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): -1.752ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J20 0.000 0.000 r UART_RX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_RX_IOBUF_inst/IO + J20 IBUF (Prop_ibuf_I_O) 1.466 1.466 r UART_RX_IOBUF_inst/IBUF/O + net (fo=1, routed) 4.378 5.844 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF + SLICE_X0Y42 LUT4 (Prop_lut4_I3_O) 0.124 5.968 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O + net (fo=1, routed) 0.000 5.968 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i + SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.077 -1.752 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk + SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C diff --git a/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt b/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt index 288f9a5..55dae57 100644 --- a/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt +++ b/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:11 2026 +| Date : Fri Jul 10 04:14:53 2026 | Host : fedora running 64-bit unknown -| Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_hold_full.rpt +| Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/timing_summary_hold_full.rpt | Design : soc_top | Device : 7a200t-fbg676 | Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report @@ -208,7 +208,7 @@ video_vsync WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 0.032 0.000 0 115177 7.000 0.000 0 42610 + 0.040 0.000 0 113333 7.000 0.000 0 42143 All user specified timing constraints are met. @@ -219,13 +219,12 @@ All user specified timing constraints are met. | ------------- ------------------------------------------------------------------------------------------------ -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk {0.000 10.000} 20.000 50.000 - clkfbout_clk_pll {0.000 10.000} 20.000 50.000 - cpu_clk {0.000 15.161} 30.323 32.979 - mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 - sys_clk {0.000 10.000} 20.000 50.000 +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk {0.000 10.000} 20.000 50.000 + clkfbout_clk_pll {0.000 10.000} 20.000 50.000 + cpu_clk {0.000 15.161} 30.323 32.979 + sys_clk {0.000 10.000} 20.000 50.000 ------------------------------------------------------------------------------------------------ @@ -233,13 +232,12 @@ clk {0.000 10.000} 20.000 50.000 | ----------------- ------------------------------------------------------------------------------------------------ -Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk 7.000 0.000 0 1 - clkfbout_clk_pll 17.845 0.000 0 3 - cpu_clk 0.049 0.000 0 17197 13.911 0.000 0 6486 - mlkem_clk_clk_pll 0.058 0.000 0 48474 18.750 0.000 0 26131 - sys_clk 0.079 0.000 0 22818 8.750 0.000 0 9989 +Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk 7.000 0.000 0 1 + clkfbout_clk_pll 17.845 0.000 0 3 + cpu_clk 0.049 0.000 0 17197 13.911 0.000 0 6486 + sys_clk 0.040 0.000 0 69558 8.750 0.000 0 35653 ------------------------------------------------------------------------------------------------ @@ -247,10 +245,8 @@ clk | ----------------- ------------------------------------------------------------------------------------------------ -From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- -sys_clk mlkem_clk_clk_pll 0.054 0.000 0 108 -mlkem_clk_clk_pll sys_clk 0.032 0.000 0 59 +From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ @@ -260,11 +256,8 @@ mlkem_clk_clk_pll sys_clk 0.032 0.000 Path Group From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- -**async_default** cpu_clk cpu_clk 0.651 0.000 0 67 -**async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 0.613 0.000 0 25694 -**async_default** sys_clk mlkem_clk_clk_pll 2.861 0.000 0 4 -**async_default** mlkem_clk_clk_pll sys_clk 2.991 0.000 0 2 -**async_default** sys_clk sys_clk 0.479 0.000 0 886 +**async_default** cpu_clk cpu_clk 0.727 0.000 0 67 +**async_default** sys_clk sys_clk 0.761 0.000 0 26511 ------------------------------------------------------------------------------------------------ @@ -341,7 +334,7 @@ Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkf_buf/I Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN @@ -369,66 +362,12 @@ Slack (MET) : 0.049ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/CLK - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 - ------------------------------------------------------------------- - slack 0.049 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.612ns + Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -440,13 +379,13 @@ Slack (MET) : 0.052ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.650 -0.612 u_cpu/u_csr/cpu_clk + SLICE_X97Y50 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C ------------------------------------------------------------------- ------------------- - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I + SLICE_X97Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.471 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q + net (fo=4, routed) 0.068 -0.403 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 + SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -457,127 +396,19 @@ Slack (MET) : 0.052ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/CLK - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.925 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK + SLICE_X96Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/CLK + clock pessimism -0.216 -0.599 + SLICE_X96Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.452 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 + required time 0.452 + arrival time -0.403 ------------------------------------------------------------------- - slack 0.052 + slack 0.049 -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk - SLICE_X17Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[10]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.061ns (arrival time - required time) +Slack (MET) : 0.051ns (arrival time - required time) Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I @@ -585,11 +416,172 @@ Slack (MET) : 0.061ns (arrival time - required time) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) + Data Path Delay: 0.211ns (logic 0.141ns (66.741%) route 0.070ns (33.259%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.216ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.647 -0.615 u_cpu/u_csr/cpu_clk + SLICE_X67Y50 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + ------------------------------------------------------------------- ------------------- + SLICE_X67Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q + net (fo=4, routed) 0.070 -0.404 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.922 -0.386 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK + clock pessimism -0.216 -0.602 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.147 -0.455 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + ------------------------------------------------------------------- + required time 0.455 + arrival time -0.404 + ------------------------------------------------------------------- + slack 0.051 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.349ns (logic 0.164ns (46.999%) route 0.185ns (53.001%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_cpu/u_csr/cpu_clk + SLICE_X40Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[26]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.185 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.961 -0.347 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X39Y52 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2]/C + clock pessimism 0.037 -0.310 + SLICE_X39Y52 FDRE (Hold_fdre_C_D) 0.070 -0.240 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[30][2] + ------------------------------------------------------------------- + required time 0.240 + arrival time -0.157 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[5]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.339ns (logic 0.128ns (37.707%) route 0.211ns (62.293%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y47 FDRE r u_cpu/axi_bridge/araddr_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y47 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[5]/Q + net (fo=1, routed) 0.211 -0.196 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIC1 + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y51 RAMD32 (Hold_ramd32_CLK_I) + 0.061 -0.280 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1 + ------------------------------------------------------------------- + required time 0.280 + arrival time -0.196 + ------------------------------------------------------------------- + slack 0.084 + +Slack (MET) : 0.084ns (arrival time - required time) + Source: u_cpu/axi_bridge/wstrb_reg[2]/C + (rising edge-triggered cell FDSE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.187ns (logic 0.128ns (68.397%) route 0.059ns (31.603%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.496ns Clock Pessimism Removal (CPR): 0.221ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -602,13 +594,13 @@ Slack (MET) : 0.061ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.756 -0.507 u_cpu/u_csr/cpu_clk - SLICE_X37Y38 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk + SLICE_X15Y41 FDSE r u_cpu/axi_bridge/wstrb_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I + SLICE_X15Y41 FDSE (Prop_fdse_C_Q) 0.128 -0.368 r u_cpu/axi_bridge/wstrb_reg[2]/Q + net (fo=1, routed) 0.059 -0.309 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/DIC0 + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -619,85 +611,31 @@ Slack (MET) : 0.061ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.035 -0.273 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK + SLICE_X14Y41 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK + clock pessimism -0.221 -0.483 + SLICE_X14Y41 RAMD32 (Hold_ramd32_CLK_I) + 0.090 -0.393 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 + required time 0.393 + arrival time -0.309 ------------------------------------------------------------------- - slack 0.061 + slack 0.084 -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C +Slack (MET) : 0.086ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[27]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/CLK - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.688%) route 0.206ns (59.312%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.504ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -710,13 +648,13 @@ Slack (MET) : 0.085ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.759 -0.504 u_cpu/u_csr/cpu_clk + SLICE_X37Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[27]/C ------------------------------------------------------------------- ------------------- - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[27]/Q + net (fo=33, routed) 0.206 -0.157 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[8] + SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -727,85 +665,30 @@ Slack (MET) : 0.085ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X37Y50 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3]/C + clock pessimism 0.037 -0.309 + SLICE_X37Y50 FDRE (Hold_fdre_C_D) 0.066 -0.243 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[4][3] ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 + required time 0.243 + arrival time -0.157 ------------------------------------------------------------------- - slack 0.085 + slack 0.086 -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[14]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -818,13 +701,13 @@ Slack (MET) : 0.099ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[26]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -835,31 +718,895 @@ Slack (MET) : 0.099ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/CLK - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 + required time 0.213 + arrival time -0.126 ------------------------------------------------------------------- - slack 0.099 + slack 0.087 -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMD32 r u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.156%) route 0.272ns (65.844%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.272 -0.126 u_cpu/btb/ras_reg_0_7_24_29/ADDRD0 + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_24_29/WCLK + SLICE_X48Y11 RAMS32 r u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y11 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.213 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1 + ------------------------------------------------------------------- + required time 0.213 + arrival time -0.126 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.408ns (logic 0.141ns (34.561%) route 0.267ns (65.439%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[65]/Q + net (fo=194, routed) 0.267 -0.109 u_regfile/rf_reg_r2_0_31_30_31/ADDRD1 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.196 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.196 + arrival time -0.109 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo1_reg[22]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.252ns (logic 0.141ns (55.979%) route 0.111ns (44.021%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.386ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.213ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.647 -0.615 u_cpu/u_csr/cpu_clk + SLICE_X69Y50 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[22]/C + ------------------------------------------------------------------- ------------------- + SLICE_X69Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_cpu/u_csr/csr_tlbelo1_reg[22]/Q + net (fo=4, routed) 0.111 -0.363 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIB0 + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.922 -0.386 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK + SLICE_X66Y50 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB/CLK + clock pessimism -0.213 -0.599 + SLICE_X66Y50 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.453 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMB + ------------------------------------------------------------------- + required time 0.453 + arrival time -0.363 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.090ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[11]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.128ns (37.132%) route 0.217ns (62.868%)) Logic Levels: 0 Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -872,13 +1619,13 @@ Slack (MET) : 0.103ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X21Y48 FDRE r u_cpu/axi_bridge/awaddr_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[11]/Q + net (fo=1, routed) 0.217 -0.191 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -889,32 +1636,1111 @@ Slack (MET) : 0.103ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.060 -0.281 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1 ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 + required time 0.281 + arrival time -0.191 + ------------------------------------------------------------------- + slack 0.090 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[9]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.358ns (logic 0.128ns (35.706%) route 0.230ns (64.294%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[9]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.128 -0.408 r u_cpu/axi_bridge/araddr_reg[9]/Q + net (fo=1, routed) 0.230 -0.177 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIB1 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.071 -0.270 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1 + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.177 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.094ns (arrival time - required time) + Source: u_cpu/axi_bridge/awaddr_reg[10]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.251ns (logic 0.141ns (56.174%) route 0.110ns (43.826%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.496ns + Clock Pessimism Removal (CPR): 0.222ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk + SLICE_X17Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q + net (fo=1, routed) 0.110 -0.245 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK + SLICE_X16Y49 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK + clock pessimism -0.222 -0.483 + SLICE_X16Y49 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC + ------------------------------------------------------------------- + required time 0.339 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.094 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMA_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMB_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/WADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMD32 r u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMC_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.095ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[1]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.420ns (logic 0.141ns (33.538%) route 0.279ns (66.462%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): 0.217ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[1]/Q + net (fo=46, routed) 0.279 -0.118 u_cpu/btb/ras_reg_0_7_18_23/ADDRD1 + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/ADR1 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.002 -0.306 u_cpu/btb/ras_reg_0_7_18_23/WCLK + SLICE_X48Y10 RAMS32 r u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1/CLK + clock pessimism -0.217 -0.523 + SLICE_X48Y10 RAMS32 (Hold_rams32_CLK_ADR1) + 0.309 -0.214 u_cpu/btb/ras_reg_0_7_18_23/RAMD_D1 + ------------------------------------------------------------------- + required time 0.214 + arrival time -0.118 + ------------------------------------------------------------------- + slack 0.095 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[26]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.366ns (logic 0.164ns (44.815%) route 0.202ns (55.185%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.346ns + Source Clock Delay (SCD): -0.506ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.757 -0.506 u_cpu/u_csr/cpu_clk + SLICE_X40Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[26]/C + ------------------------------------------------------------------- ------------------- + SLICE_X40Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.342 r u_cpu/u_csr/csr_tlbidx_reg[26]/Q + net (fo=33, routed) 0.202 -0.140 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[7] + SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.962 -0.346 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X37Y51 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2]/C + clock pessimism 0.037 -0.309 + SLICE_X37Y51 FDRE (Hold_fdre_C_D) 0.070 -0.239 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[27][2] + ------------------------------------------------------------------- + required time 0.239 + arrival time -0.140 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMA_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMB_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/WADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMD32 r u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMD32 (Hold_ramd32_CLK_WADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMC_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.100ns (arrival time - required time) + Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + (rising edge-triggered cell RAMS32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.312ns (logic 0.141ns (45.241%) route 0.171ns (54.759%)) + Logic Levels: 0 + Clock Path Skew: 0.012ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.287ns + Source Clock Delay (SCD): -0.517ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.746 -0.517 u_cpu/wb_stage/cpu_clk + SLICE_X37Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.376 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[68]/Q + net (fo=162, routed) 0.171 -0.205 u_regfile/rf_reg_r2_0_31_30_31/ADDRD4 + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/ADR4 + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.021 -0.287 u_regfile/rf_reg_r2_0_31_30_31/WCLK + SLICE_X36Y25 RAMS32 r u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1/CLK + clock pessimism -0.218 -0.505 + SLICE_X36Y25 RAMS32 (Hold_rams32_CLK_ADR4) + 0.200 -0.305 u_regfile/rf_reg_r2_0_31_30_31/RAMD_D1 + ------------------------------------------------------------------- + required time 0.305 + arrival time -0.205 + ------------------------------------------------------------------- + slack 0.100 + +Slack (MET) : 0.103ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbelo0_reg[4]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.286ns (logic 0.141ns (49.244%) route 0.145ns (50.756%)) + Logic Levels: 0 + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.304ns + Source Clock Delay (SCD): -0.537ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.726 -0.537 u_cpu/u_csr/cpu_clk + SLICE_X50Y43 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X50Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_cpu/u_csr/csr_tlbelo0_reg[4]/Q + net (fo=7, routed) 0.145 -0.250 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/D + SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/I + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.004 -0.304 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/WCLK + SLICE_X48Y43 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP/CLK + clock pessimism -0.196 -0.500 + SLICE_X48Y43 RAMD32 (Hold_ramd32_CLK_I) + 0.146 -0.354 u_cpu/addr_trans/tlb_entry/tlb_mat0_reg_r2_0_31_0_0/SP + ------------------------------------------------------------------- + required time 0.354 + arrival time -0.250 ------------------------------------------------------------------- slack 0.103 -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_cpu/axi_bridge/araddr_reg[10]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I + Destination: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) + Data Path Delay: 0.442ns (logic 0.141ns (31.876%) route 0.301ns (68.124%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.536ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -926,13 +2752,13 @@ Slack (MET) : 0.106ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.727 -0.536 u_cpu/axi_bridge/cpu_clk + SLICE_X47Y49 FDRE r u_cpu/axi_bridge/araddr_reg[10]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I + SLICE_X47Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_cpu/axi_bridge/araddr_reg[10]/Q + net (fo=1, routed) 0.301 -0.093 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/DIC0 + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/I ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -943,1046 +2769,84 @@ Slack (MET) : 0.106ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.930 -0.378 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK + clock pessimism 0.037 -0.341 + SLICE_X44Y52 RAMD32 (Hold_ramd32_CLK_I) + 0.144 -0.197 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 + required time 0.197 + arrival time -0.093 ------------------------------------------------------------------- - slack 0.106 + slack 0.104 -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_cpu/u_csr/csr_tlbidx_reg[24]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I + Destination: u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: cpu_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.376ns (logic 0.141ns (37.453%) route 0.235ns (62.547%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.345ns + Source Clock Delay (SCD): -0.504ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.759 -0.504 u_cpu/u_csr/cpu_clk + SLICE_X37Y49 FDRE r u_cpu/u_csr/csr_tlbidx_reg[24]/C + ------------------------------------------------------------------- ------------------- + SLICE_X37Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/u_csr/csr_tlbidx_reg[24]/Q + net (fo=33, routed) 0.235 -0.127 u_cpu/addr_trans/tlb_entry/tlbw_r_tlbidx[5] + SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.963 -0.345 u_cpu/addr_trans/tlb_entry/cpu_clk + SLICE_X32Y53 FDRE r u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0]/C + clock pessimism 0.037 -0.308 + SLICE_X32Y53 FDRE (Hold_fdre_C_D) 0.070 -0.238 u_cpu/addr_trans/tlb_entry/tlb_ps_reg[31][0] + ------------------------------------------------------------------- + required time 0.238 + arrival time -0.127 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/CLK - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/CLK - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/CLK - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y47 FDRE r u_cpu/axi_bridge/wdata_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.753 -0.510 u_cpu/u_csr/cpu_clk - SLICE_X41Y37 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/WCLK - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1995,13 +2859,13 @@ Slack (MET) : 0.128ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2012,137 +2876,31 @@ Slack (MET) : 0.128ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 + required time 0.212 + arrival time -0.099 ------------------------------------------------------------------- - slack 0.128 + slack 0.113 -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2155,13 +2913,13 @@ Slack (MET) : 0.132ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.721 -0.542 u_cpu/u_csr/cpu_clk - SLICE_X43Y32 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[20]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2172,247 +2930,31 @@ Slack (MET) : 0.132ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/CLK - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMA_D1 ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 + required time 0.212 + arrival time -0.099 ------------------------------------------------------------------- - slack 0.132 + slack 0.113 -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk - SLICE_X28Y48 FDRE r u_cpu/axi_bridge/araddr_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB - ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2425,13 +2967,13 @@ Slack (MET) : 0.136ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk - SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[12]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2442,85 +2984,31 @@ Slack (MET) : 0.136ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/CLK - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 + required time 0.212 + arrival time -0.099 ------------------------------------------------------------------- - slack 0.136 + slack 0.113 -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C +Slack (MET) : 0.113ns (arrival time - required time) + Source: u_cpu/btb/ras_ptr_reg[0]/C (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I + Destination: u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: cpu_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) + Data Path Delay: 0.440ns (logic 0.141ns (32.054%) route 0.299ns (67.946%)) Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk - SLICE_X29Y48 FDRE r u_cpu/axi_bridge/araddr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.539ns Clock Pessimism Removal (CPR): 0.217ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -2533,13 +3021,13 @@ Slack (MET) : 0.137ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk - SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[11]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.724 -0.539 u_cpu/btb/cpu_clk + SLICE_X47Y10 FDRE r u_cpu/btb/ras_ptr_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I + SLICE_X47Y10 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_cpu/btb/ras_ptr_reg[0]/Q + net (fo=47, routed) 0.299 -0.099 u_cpu/btb/ras_reg_0_7_6_11/ADDRD0 + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -2550,499 +3038,17 @@ Slack (MET) : 0.137ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/CLK - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.003 -0.305 u_cpu/btb/ras_reg_0_7_6_11/WCLK + SLICE_X46Y8 RAMD32 r u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1/CLK + clock pessimism -0.217 -0.522 + SLICE_X46Y8 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.212 u_cpu/btb/ras_reg_0_7_6_11/RAMB_D1 ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 + required time 0.212 + arrival time -0.099 ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_cpu/axi_bridge/cpu_clk - SLICE_X3Y48 FDRE r u_cpu/axi_bridge/wdata_reg[28]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/icache/lfsr/cpu_clk - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_cpu/icache/lfsr/cpu_clk - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/C - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/WCLK - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/CLK - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.761 -0.502 u_cpu/wb_stage/cpu_clk - SLICE_X31Y41 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.040 -0.268 u_cpu/u_csr/cpu_clk - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/C - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns - Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.759 -0.504 u_cpu/wb_stage/cpu_clk - SLICE_X32Y40 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.039 -0.269 u_cpu/u_csr/cpu_clk - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/C - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.750 -0.513 u_cpu/mem_stage/cpu_clk - SLICE_X27Y26 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.026 -0.282 u_cpu/wb_stage/cpu_clk - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/C - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 + slack 0.113 @@ -3056,3223 +3062,157 @@ Period(ns): 30.323 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y4 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y3 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y5 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y0 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y1 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y2 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y4 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y6 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y7 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y5 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y8 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y20 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y18 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y20 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X3Y21 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK +Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout1_buf/I Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y1 u_cpu/btb/btb_add_entry_index_r_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y3 u_cpu/btb/btb_add_entry_index_r_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X47Y0 u_cpu/btb/btb_add_entry_index_r_reg[2]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[3]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X43Y6 u_cpu/btb/btb_add_entry_index_r_reg[4]/C +Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X41Y6 u_cpu/btb/btb_add_entry_r_reg/C +Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[0]/C +Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X5Y45 pll_clk.u_rst_cpu/delay_reg[1]/C Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.058ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.568 -0.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y144 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/C - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/C - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.591 -0.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X138Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - ------------------------------------------------------------------- ------------------- - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.869 -0.439 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/C - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.580 -0.683 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X73Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.844 -0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/C - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/C - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.829 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/C - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.111ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.510ns (logic 0.256ns (50.190%) route 0.254ns (49.810%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q - net (fo=7, routed) 0.254 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10] - SLICE_X84Y157 LUT4 (Prop_lut4_I3_O) 0.045 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_9/O - net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave_n_123 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.192 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[4] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.192 - ------------------------------------------------------------------- - slack 0.111 - -Slack (MET) : 0.114ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.557ns (logic 0.234ns (42.015%) route 0.323ns (57.985%)) - Logic Levels: 2 (LUT3=1 LUT6=1) - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.398ns - Source Clock Delay (SCD): -0.694ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X79Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C - ------------------------------------------------------------------- ------------------- - SLICE_X79Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/Q - net (fo=2, routed) 0.169 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data18[13] - SLICE_X81Y99 LUT6 (Prop_lut6_I0_O) 0.045 -0.339 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[445]_i_2/O - net (fo=1, routed) 0.154 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[185] - SLICE_X81Y99 LUT3 (Prop_lut3_I1_O) 0.048 -0.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[445]_i_1/O - net (fo=1, routed) 0.000 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[445] - SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.910 -0.398 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/C - clock pessimism 0.040 -0.358 - SLICE_X81Y99 FDCE (Hold_fdce_C_D) 0.107 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445] - ------------------------------------------------------------------- - required time 0.251 - arrival time -0.137 - ------------------------------------------------------------------- - slack 0.114 - -Slack (MET) : 0.115ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.518ns (logic 0.186ns (35.884%) route 0.332ns (64.116%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.282ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.456ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/Q - net (fo=234, routed) 0.332 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] - SLICE_X92Y145 LUT6 (Prop_lut6_I3_O) 0.045 -0.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1/O - net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1_n_0 - SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/C - clock pessimism 0.045 -0.411 - SLICE_X92Y145 FDCE (Hold_fdce_C_D) 0.121 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4] - ------------------------------------------------------------------- - required time 0.290 - arrival time -0.175 - ------------------------------------------------------------------- - slack 0.115 - -Slack (MET) : 0.116ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.474ns (logic 0.226ns (47.682%) route 0.248ns (52.318%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.704ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.559 -0.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X81Y162 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X81Y162 FDCE (Prop_fdce_C_Q) 0.128 -0.576 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/Q - net (fo=4, routed) 0.248 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg_n_0_[6] - SLICE_X87Y160 LUT3 (Prop_lut3_I0_O) 0.098 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0/O - net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0_n_0 - SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/C - clock pessimism 0.040 -0.438 - SLICE_X87Y160 FDCE (Hold_fdce_C_D) 0.092 -0.346 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6] - ------------------------------------------------------------------- - required time 0.346 - arrival time -0.230 - ------------------------------------------------------------------- - slack 0.116 - -Slack (MET) : 0.120ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.519ns (logic 0.252ns (48.552%) route 0.267ns (51.448%)) - Logic Levels: 2 (CARRY4=1 LUT5=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q - net (fo=7, routed) 0.267 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10] - SLICE_X84Y157 LUT5 (Prop_lut5_I0_O) 0.045 -0.249 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_8/O - net (fo=1, routed) 0.000 -0.249 u_fft_mlkem_axi_slave_n_122 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[1]_O[1]) - 0.066 -0.183 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[1] - net (fo=1, routed) 0.000 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[5] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.183 - ------------------------------------------------------------------- - slack 0.120 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.076 -0.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.505 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.228 -0.581 - SLICE_X25Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.226 -0.615 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.540 - arrival time -0.418 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.614ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.226 -0.614 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.075 -0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.539 - arrival time -0.417 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.521ns (logic 0.273ns (52.394%) route 0.248ns (47.606%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X80Y155 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/Q - net (fo=6, routed) 0.248 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[3] - SLICE_X84Y156 LUT4 (Prop_lut4_I1_O) 0.045 -0.244 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11]_i_5/O - net (fo=1, routed) 0.000 -0.244 u_fft_mlkem_axi_slave_n_417 - SLICE_X84Y156 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.064 -0.180 r u_bf/u_barrett/qprod_s4_reg[11]_i_1/O[3] - net (fo=1, routed) 0.000 -0.180 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[3] - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y156 FDCE (Hold_fdce_C_D) 0.134 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.180 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/Q - net (fo=1, routed) 0.222 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.269 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2/O - net (fo=1, routed) 0.000 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[3] - net (fo=1, routed) 0.000 -0.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[11] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.206 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[15] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[19] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[23] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[23] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.071 -0.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.510 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.071 -0.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.511 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.226 -0.615 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.071 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.544 - arrival time -0.418 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.614ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.226 -0.614 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.071 -0.543 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.543 - arrival time -0.417 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.527ns (logic 0.251ns (47.592%) route 0.276ns (52.408%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y157 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/Q - net (fo=7, routed) 0.276 -0.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[5] - SLICE_X84Y157 LUT4 (Prop_lut4_I0_O) 0.045 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_7/O - net (fo=1, routed) 0.000 -0.240 u_fft_mlkem_axi_slave_n_121 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.065 -0.175 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[6] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.175 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.129ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.526ns (logic 0.185ns (35.176%) route 0.341ns (64.824%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X83Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/Q - net (fo=4, routed) 0.341 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[1] - SLICE_X84Y154 LUT3 (Prop_lut3_I0_O) 0.044 -0.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1/O - net (fo=1, routed) 0.000 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1_n_0 - SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y154 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.176 - ------------------------------------------------------------------- - slack 0.129 - -Slack (MET) : 0.130ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.499ns (logic 0.292ns (58.570%) route 0.207ns (41.430%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.106 -0.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[1] - net (fo=1, routed) 0.000 -0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[1] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.202 - ------------------------------------------------------------------- - slack 0.130 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.531ns (logic 0.186ns (35.046%) route 0.345ns (64.954%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.337ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns - Source Clock Delay (SCD): -0.612ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.651 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X161Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C - ------------------------------------------------------------------- ------------------- - SLICE_X161Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/Q - net (fo=1, routed) 0.156 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[352] - SLICE_X161Y100 LUT2 (Prop_lut2_I0_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/r_r[96]_i_1/O - net (fo=2, routed) 0.189 -0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_hash[352] - SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.993 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/C - clock pessimism 0.040 -0.275 - SLICE_X158Y99 FDCE (Hold_fdce_C_D) 0.063 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96] - ------------------------------------------------------------------- - required time 0.212 - arrival time -0.081 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.164ns (34.335%) route 0.314ns (65.665%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.694ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X80Y149 FDCE (Prop_fdce_C_Q) 0.164 -0.530 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/Q - net (fo=1, routed) 0.314 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3[5] - SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.832 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/C - clock pessimism 0.045 -0.430 - SLICE_X80Y154 FDCE (Hold_fdce_C_D) 0.083 -0.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5] - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.216 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.454ns (logic 0.141ns (31.069%) route 0.313ns (68.931%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y159 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/Q - net (fo=1, routed) 0.313 -0.248 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[0] - SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/C - clock pessimism 0.040 -0.438 - SLICE_X82Y159 FDCE (Hold_fdce_C_D) 0.059 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0] - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.504ns (logic 0.249ns (49.413%) route 0.255ns (50.587%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y155 FDCE (Prop_fdce_C_Q) 0.148 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/Q - net (fo=4, routed) 0.255 -0.298 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg_n_0_[5] - SLICE_X82Y151 LUT3 (Prop_lut3_I0_O) 0.101 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1/O - net (fo=1, routed) 0.000 -0.197 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1_n_0 - SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.832 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/C - clock pessimism 0.040 -0.436 - SLICE_X82Y151 FDCE (Hold_fdce_C_D) 0.107 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5] - ------------------------------------------------------------------- - required time 0.329 - arrival time -0.197 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.503ns (logic 0.285ns (56.653%) route 0.218ns (43.347%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[3]) - 0.099 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[3] - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[3] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/C - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.480ns (logic 0.141ns (29.345%) route 0.339ns (70.655%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.481ns - Source Clock Delay (SCD): -0.705ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.558 -0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X87Y164 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X87Y164 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/Q - net (fo=1, routed) 0.339 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[20] - SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.826 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/C - clock pessimism 0.040 -0.441 - SLICE_X80Y165 FDCE (Hold_fdce_C_D) 0.084 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20] - ------------------------------------------------------------------- - required time 0.357 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.240ns (logic 0.186ns (77.515%) route 0.054ns (22.485%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.456ns - Source Clock Delay (SCD): -0.681ns - Clock Pessimism Removal (CPR): 0.212ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.582 -0.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk - SLICE_X58Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X58Y137 FDCE (Prop_fdce_C_Q) 0.141 -0.540 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/Q - net (fo=1, routed) 0.054 -0.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5[11] - SLICE_X59Y137 LUT5 (Prop_lut5_I0_O) 0.045 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1/O - net (fo=1, routed) 0.000 -0.441 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1_n_0 - SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk - SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/C - clock pessimism -0.212 -0.668 - SLICE_X59Y137 FDCE (Hold_fdce_C_D) 0.091 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11] - ------------------------------------------------------------------- - required time 0.577 - arrival time -0.441 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.536ns (logic 0.250ns (46.632%) route 0.286ns (53.368%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/Q - net (fo=8, routed) 0.286 -0.275 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3[11] - SLICE_X84Y158 LUT4 (Prop_lut4_I3_O) 0.045 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19]_i_6/O - net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave_n_135 - SLICE_X84Y158 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.064 -0.166 r u_bf/u_barrett/qprod_s4_reg[19]_i_1/O[3] - net (fo=1, routed) 0.000 -0.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[11] - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y158 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.166 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.498ns (logic 0.186ns (37.319%) route 0.312ns (62.681%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.269ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/Q - net (fo=234, routed) 0.312 -0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] - SLICE_X86Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1/O - net (fo=1, routed) 0.000 -0.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1_n_0 - SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/C - clock pessimism 0.045 -0.424 - SLICE_X86Y149 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.194 - ------------------------------------------------------------------- - slack 0.138 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: mlkem_clk_clk_pll -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I -Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C -Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y54 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y51 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y54 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y52 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y57 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y55 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X18Y57 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X48Y6 u_cpu/btb/btb_target_reg_0_31_0_1/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y39 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X16Y39 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X14Y36 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X46Y3 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X44Y8 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK @@ -6281,26 +3221,79 @@ From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.079ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.040ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.040ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_b_reg[1][23]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) + Data Path Delay: 0.443ns (logic 0.141ns (31.835%) route 0.302ns (68.165%)) Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns + Clock Path Skew: 0.333ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.381ns + Source Clock Delay (SCD): -0.674ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.589 -0.674 u_matmul_axi_slave/sys_clk + SLICE_X47Y102 FDRE r u_matmul_axi_slave/m_in_b_reg[1][23]/C + ------------------------------------------------------------------- ------------------- + SLICE_X47Y102 FDRE (Prop_fdre_C_Q) 0.141 -0.533 r u_matmul_axi_slave/m_in_b_reg[1][23]/Q + net (fo=1, routed) 0.302 -0.231 u_matmul_axi_slave/mult_inst[1].u_mult/Q[23] + SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.927 -0.381 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk + SLICE_X59Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23]/C + clock pessimism 0.040 -0.341 + SLICE_X59Y98 FDRE (Hold_fdre_C_D) 0.070 -0.271 u_matmul_axi_slave/mult_inst[1].u_mult/b_r_reg[23] + ------------------------------------------------------------------- + required time 0.271 + arrival time -0.231 + ------------------------------------------------------------------- + slack 0.040 + +Slack (MET) : 0.042ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.412ns (logic 0.187ns (45.442%) route 0.225ns (54.558%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.413ns + Source Clock Delay (SCD): -0.639ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6314,13 +3307,14 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.696 -0.566 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X18Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK + net (fo=35652, routed) 0.623 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X82Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D + SLICE_X82Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.498 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg[11]/Q + net (fo=3, routed) 0.225 -0.274 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_reg_n_0_[11] + SLICE_X85Y77 LUT3 (Prop_lut3_I2_O) 0.046 -0.228 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1/O + net (fo=1, routed) 0.000 -0.228 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l[11]_i_1_n_0 + SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6332,31 +3326,30 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.048 -0.260 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/CLK - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 + net (fo=35652, routed) 0.895 -0.413 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X85Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/C + clock pessimism 0.037 -0.376 + SLICE_X85Y77 FDCE (Hold_fdce_C_D) 0.107 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 + required time 0.269 + arrival time -0.228 ------------------------------------------------------------------- - slack 0.079 + slack 0.042 -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.049ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) + Data Path Delay: 0.382ns (logic 0.141ns (36.898%) route 0.241ns (63.102%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.263ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.487ns + Source Clock Delay (SCD): -0.710ns + Clock Pessimism Removal (CPR): -0.040ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -6369,12 +3362,12 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk - SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C + net (fo=35652, routed) 0.553 -0.710 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X85Y170 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/C ------------------------------------------------------------------- ------------------- - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I + SLICE_X85Y170 FDCE (Prop_fdce_C_Q) 0.141 -0.569 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[9]/Q + net (fo=14, routed) 0.241 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[9] + SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6386,191 +3379,29 @@ Slack (MET) : 0.079ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk - SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA + net (fo=35652, routed) 0.821 -0.487 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X81Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9]/C + clock pessimism 0.040 -0.447 + SLICE_X81Y171 FDCE (Hold_fdce_C_D) 0.070 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[9] ------------------------------------------------------------------- required time 0.377 - arrival time -0.298 + arrival time -0.328 ------------------------------------------------------------------- - slack 0.080 + slack 0.049 -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C +Slack (MET) : 0.056ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.636 -0.626 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk - SLICE_X62Y75 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns + Data Path Delay: 0.508ns (logic 0.213ns (41.922%) route 0.295ns (58.078%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -6584,13 +3415,14 @@ Slack (MET) : 0.096ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X20Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK + net (fo=35652, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk + SLICE_X112Y55 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/C ------------------------------------------------------------------- ------------------- - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D + SLICE_X112Y55 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][8]__0/Q + net (fo=5, routed) 0.295 -0.143 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[8] + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.049 -0.094 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[8]_i_1__0/O + net (fo=1, routed) 0.000 -0.094 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[8] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -6602,675 +3434,30 @@ Slack (MET) : 0.096ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.046 -0.262 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/CLK - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 + net (fo=35652, routed) 1.014 -0.294 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8]/C + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[8] ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 + required time 0.150 + arrival time -0.094 ------------------------------------------------------------------- - slack 0.096 + slack 0.056 -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C +Slack (MET) : 0.061ns (arrival time - required time) + Source: u_confreg/confreg_int_set_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/C - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/C - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[11]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns + Data Path Delay: 0.376ns (logic 0.246ns (65.365%) route 0.130ns (34.635%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): -0.494ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7283,12 +3470,14 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + net (fo=35652, routed) 0.769 -0.494 u_confreg/sys_clk + SLICE_X8Y49 FDRE r u_confreg/confreg_int_set_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 + SLICE_X8Y49 FDRE (Prop_fdre_C_Q) 0.148 -0.346 r u_confreg/confreg_int_set_reg[11]/Q + net (fo=2, routed) 0.130 -0.215 u_confreg/u_int_ctrl/edge_int_state_reg[31]_0[11] + SLICE_X8Y51 LUT4 (Prop_lut4_I2_O) 0.098 -0.117 r u_confreg/u_int_ctrl/edge_int_state[11]_i_1/O + net (fo=1, routed) 0.000 -0.117 u_confreg/u_int_ctrl/edge_int_state[11]_i_1_n_0 + SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7300,31 +3489,30 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + net (fo=35652, routed) 0.973 -0.335 u_confreg/u_int_ctrl/sys_clk + SLICE_X8Y51 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[11]/C + clock pessimism 0.037 -0.298 + SLICE_X8Y51 FDCE (Hold_fdce_C_D) 0.120 -0.178 u_confreg/u_int_ctrl/edge_int_state_reg[11] ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 + required time 0.178 + arrival time -0.117 ------------------------------------------------------------------- - slack 0.117 + slack 0.061 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) +Slack (MET) : 0.074ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns + Data Path Delay: 0.526ns (logic 0.210ns (39.912%) route 0.316ns (60.088%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.345ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.294ns + Source Clock Delay (SCD): -0.602ns + Clock Pessimism Removal (CPR): -0.037ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7337,12 +3525,14 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + net (fo=35652, routed) 0.660 -0.602 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk + SLICE_X112Y53 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 + SLICE_X112Y53 FDRE (Prop_fdre_C_Q) 0.164 -0.438 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][10]__0/Q + net (fo=5, routed) 0.316 -0.122 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[10] + SLICE_X114Y49 LUT3 (Prop_lut3_I2_O) 0.046 -0.076 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[10]_i_1__0/O + net (fo=1, routed) 0.000 -0.076 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[10] + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7354,18 +3544,17 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + net (fo=35652, routed) 1.014 -0.294 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk + SLICE_X114Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10]/C + clock pessimism 0.037 -0.257 + SLICE_X114Y49 FDRE (Hold_fdre_C_D) 0.107 -0.150 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[10] ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 + required time 0.150 + arrival time -0.076 ------------------------------------------------------------------- - slack 0.117 + slack 0.074 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 @@ -7373,11 +3562,11 @@ Slack (MET) : 0.117ns (arrival time - required time) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7391,12 +3580,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + net (fo=35652, routed) 0.716 -0.546 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X4Y67 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7408,18 +3597,18 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP + net (fo=35652, routed) 0.995 -0.313 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 + required time 0.196 + arrival time -0.120 ------------------------------------------------------------------- - slack 0.117 + slack 0.076 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.076ns (arrival time - required time) Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 @@ -7427,11 +3616,11 @@ Slack (MET) : 0.117ns (arrival time - required time) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) + Data Path Delay: 0.426ns (logic 0.141ns (33.085%) route 0.285ns (66.915%)) Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.313ns + Source Clock Delay (SCD): -0.546ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -7445,12 +3634,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C + net (fo=35652, routed) 0.716 -0.546 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X4Y67 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 + SLICE_X4Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.405 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q + net (fo=7, routed) 0.285 -0.120 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7462,31 +3651,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP + net (fo=35652, routed) 0.995 -0.313 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X2Y66 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK + clock pessimism -0.192 -0.505 + SLICE_X2Y66 RAMD32 (Hold_ramd32_CLK_WADR1) + 0.309 -0.196 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 + required time 0.196 + arrival time -0.120 ------------------------------------------------------------------- - slack 0.117 + slack 0.076 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7499,12 +3688,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.693 -0.569 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X15Y61 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7516,31 +3705,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA + net (fo=35652, routed) 0.969 -0.339 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.221 + arrival time -0.135 ------------------------------------------------------------------- - slack 0.117 + slack 0.087 -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.435ns (logic 0.141ns (32.439%) route 0.294ns (67.561%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.339ns + Source Clock Delay (SCD): -0.569ns + Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7553,12 +3742,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.693 -0.569 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/sys_clk + SLICE_X15Y61 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 + SLICE_X15Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q + net (fo=9, routed) 0.294 -0.135 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7570,31 +3759,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 + net (fo=35652, routed) 0.969 -0.339 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK + SLICE_X16Y61 RAMD32 r axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK + clock pessimism -0.192 -0.531 + SLICE_X16Y61 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.221 axi4WriteOnlyArbiter_5/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.221 + arrival time -0.135 ------------------------------------------------------------------- - slack 0.117 + slack 0.087 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7607,12 +3796,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7624,31 +3813,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.117 + slack 0.087 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7661,12 +3850,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7678,31 +3867,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMA_D1 ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.117 + slack 0.087 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7715,12 +3904,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7732,31 +3921,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.117 + slack 0.087 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7769,12 +3958,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7786,31 +3975,139 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMB_D1 ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.117 + slack 0.087 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) + Logic Levels: 0 + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMC_D1 + ------------------------------------------------------------------- + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.087ns (arrival time - required time) + Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7823,12 +4120,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7840,31 +4137,31 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.140 + arrival time -0.053 ------------------------------------------------------------------- - slack 0.117 + slack 0.087 -Slack (MET) : 0.117ns (arrival time - required time) +Slack (MET) : 0.087ns (arrival time - required time) Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) + Data Path Delay: 0.413ns (logic 0.141ns (34.155%) route 0.272ns (65.845%)) Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.230ns + Source Clock Delay (SCD): -0.466ns + Clock Pessimism Removal (CPR): 0.220ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7877,12 +4174,12 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C + net (fo=35652, routed) 0.797 -0.466 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk + SLICE_X1Y45 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 + SLICE_X1Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.325 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q + net (fo=20, routed) 0.272 -0.053 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/ADDRD0 + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7894,31 +4191,1596 @@ Slack (MET) : 0.117ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 + net (fo=35652, routed) 1.078 -0.230 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/WCLK + SLICE_X2Y46 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1/CLK + clock pessimism -0.220 -0.450 + SLICE_X2Y46 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 -0.140 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_6_7/RAMD_D1 ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 + required time 0.140 + arrival time -0.053 + ------------------------------------------------------------------- + slack 0.087 + +Slack (MET) : 0.089ns (arrival time - required time) + Source: u_confreg/int_out_or_q1_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/int_out_or_q2_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.480ns (logic 0.141ns (29.360%) route 0.339ns (70.640%)) + Logic Levels: 0 + Clock Path Skew: 0.316ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): -0.539ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X4Y50 FDRE r u_confreg/int_out_or_q1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X4Y50 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/int_out_or_q1_reg/Q + net (fo=1, routed) 0.339 -0.059 u_confreg/int_out_or_q1 + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C + clock pessimism 0.037 -0.223 + SLICE_X9Y47 FDRE (Hold_fdre_C_D) 0.075 -0.148 u_confreg/int_out_or_q2_reg + ------------------------------------------------------------------- + required time 0.148 + arrival time -0.059 + ------------------------------------------------------------------- + slack 0.089 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X103Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[2] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/sys_clk + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.333ns (logic 0.141ns (42.362%) route 0.192ns (57.638%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X103Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X103Y68 FDRE (Prop_fdre_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[2]/Q + net (fo=7, routed) 0.192 -0.283 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[2] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[6] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/sys_clk + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[6]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.097ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.443ns (logic 0.141ns (31.804%) route 0.302ns (68.196%)) + Logic Levels: 0 + Clock Path Skew: 0.276ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.388ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y150 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/C + ------------------------------------------------------------------- ------------------- + SLICE_X157Y150 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[13]/Q + net (fo=14, routed) 0.302 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[13] + SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y138 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13]/C + clock pessimism 0.045 -0.343 + SLICE_X159Y138 FDCE (Hold_fdce_C_D) 0.070 -0.273 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[13] + ------------------------------------------------------------------- + required time 0.273 + arrival time -0.176 + ------------------------------------------------------------------- + slack 0.097 + +Slack (MET) : 0.098ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X83Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][4]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4]/C + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.092 -0.343 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][4] + ------------------------------------------------------------------- + required time 0.343 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.098 + +Slack (MET) : 0.099ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.456ns (logic 0.186ns (40.793%) route 0.270ns (59.207%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.266ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.475ns + Source Clock Delay (SCD): -0.701ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X83Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9/Q + net (fo=114, routed) 0.270 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[2]_rep__9_n_0 + SLICE_X87Y152 LUT5 (Prop_lut5_I3_O) 0.045 -0.245 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1/O + net (fo=1, routed) 0.000 -0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B[165][3]_i_1_n_0 + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X87Y152 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3]/C + clock pessimism 0.040 -0.435 + SLICE_X87Y152 FDCE (Hold_fdce_C_D) 0.091 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_B_reg[165][3] + ------------------------------------------------------------------- + required time 0.344 + arrival time -0.245 + ------------------------------------------------------------------- + slack 0.099 + +Slack (MET) : 0.101ns (arrival time - required time) + Source: u_matmul_axi_slave/m_in_a_reg[1][28]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.496ns (logic 0.164ns (33.088%) route 0.332ns (66.911%)) + Logic Levels: 0 + Clock Path Skew: 0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.675ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.588 -0.675 u_matmul_axi_slave/sys_clk + SLICE_X44Y105 FDRE r u_matmul_axi_slave/m_in_a_reg[1][28]/C + ------------------------------------------------------------------- ------------------- + SLICE_X44Y105 FDRE (Prop_fdre_C_Q) 0.164 -0.511 r u_matmul_axi_slave/m_in_a_reg[1][28]/Q + net (fo=1, routed) 0.332 -0.179 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[31]_0[28] + SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.929 -0.379 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk + SLICE_X56Y98 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28]/C + clock pessimism 0.040 -0.339 + SLICE_X56Y98 FDRE (Hold_fdre_C_D) 0.059 -0.280 u_matmul_axi_slave/mult_inst[1].u_mult/a_r_reg[28] + ------------------------------------------------------------------- + required time 0.280 + arrival time -0.179 + ------------------------------------------------------------------- + slack 0.101 + +Slack (MET) : 0.104ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.451ns (logic 0.141ns (31.244%) route 0.310ns (68.756%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/C + ------------------------------------------------------------------- ------------------- + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[18]/Q + net (fo=15, routed) 0.310 -0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[18] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18]/C + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.070 -0.272 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[18] + ------------------------------------------------------------------- + required time 0.272 + arrival time -0.168 + ------------------------------------------------------------------- + slack 0.104 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X102Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/Q[4] + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/sys_clk + RAMB18_X6Y27 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y27 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.345ns (logic 0.164ns (47.501%) route 0.181ns (52.499%)) + Logic Levels: 0 + Clock Path Skew: 0.056ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.347ns + Source Clock Delay (SCD): -0.615ns + Clock Pessimism Removal (CPR): 0.212ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_fft_controller/sys_clk + SLICE_X102Y68 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X102Y68 FDRE (Prop_fdre_C_Q) 0.164 -0.451 r u_fft_mlkem_axi_slave/u_fft_controller/out_cnt_reg[4]/Q + net (fo=9, routed) 0.181 -0.270 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/Q[4] + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/ADDRARDADDR[8] + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.961 -0.347 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/sys_clk + RAMB18_X6Y26 RAMB18E1 r u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK + clock pessimism -0.212 -0.559 + RAMB18_X6Y26 RAMB18E1 (Hold_ramb18e1_CLKARDCLK_ADDRARDADDR[8]) + 0.183 -0.376 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg + ------------------------------------------------------------------- + required time 0.376 + arrival time -0.270 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.106ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.449ns (logic 0.141ns (31.381%) route 0.308ns (68.619%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/C + ------------------------------------------------------------------- ------------------- + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[17]/Q + net (fo=15, routed) 0.308 -0.170 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[17] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17]/C + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.066 -0.276 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[17] + ------------------------------------------------------------------- + required time 0.276 + arrival time -0.170 + ------------------------------------------------------------------- + slack 0.106 + +Slack (MET) : 0.108ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/buf_addr_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.425ns (logic 0.186ns (43.780%) route 0.239ns (56.220%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/sys_clk + SLICE_X13Y45 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/Q + net (fo=13, routed) 0.239 -0.115 u_Axi_CDC/arFifo/_zz_ram_port1[2] + SLICE_X16Y51 LUT5 (Prop_lut5_I1_O) 0.045 -0.070 r u_Axi_CDC/arFifo/buf_addr[2]_i_1/O + net (fo=1, routed) 0.000 -0.070 u_confreg/buf_addr_reg[15]_0[2] + SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk + SLICE_X16Y51 FDRE r u_confreg/buf_addr_reg[2]/C + clock pessimism 0.037 -0.299 + SLICE_X16Y51 FDRE (Hold_fdre_C_D) 0.121 -0.178 u_confreg/buf_addr_reg[2] + ------------------------------------------------------------------- + required time 0.178 + arrival time -0.070 + ------------------------------------------------------------------- + slack 0.108 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_confreg/digital_data_reg[1]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.353ns (logic 0.141ns (39.954%) route 0.212ns (60.046%)) + Logic Levels: 0 + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.798 -0.465 u_confreg/sys_clk + SLICE_X0Y49 FDRE r u_confreg/digital_data_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.324 r u_confreg/digital_data_reg[1]/Q + net (fo=2, routed) 0.212 -0.112 u_confreg/u_digitaltube_controller/dpy1_data_reg[3]_0[1] + SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y54 FDRE r u_confreg/u_digitaltube_controller/dpy0_data_reg[1]/C + clock pessimism 0.037 -0.269 + SLICE_X0Y54 FDRE (Hold_fdre_C_D) 0.047 -0.222 u_confreg/u_digitaltube_controller/dpy0_data_reg[1] + ------------------------------------------------------------------- + required time 0.222 + arrival time -0.112 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.111ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.410ns (logic 0.209ns (50.949%) route 0.201ns (49.051%)) + Logic Levels: 1 (LUT3=1) + Clock Path Skew: 0.192ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.371ns + Source Clock Delay (SCD): -0.527ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.736 -0.527 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/sys_clk + SLICE_X116Y49 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X116Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.363 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/DB2/buf_re_reg[63][3]__0/Q + net (fo=5, routed) 0.201 -0.162 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re_reg[3] + SLICE_X118Y50 LUT3 (Prop_lut3_I2_O) 0.045 -0.117 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/BF2/bf2_do_re[3]_i_1__0/O + net (fo=1, routed) 0.000 -0.117 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_sp_re[3] + SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.937 -0.371 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/sys_clk + SLICE_X118Y50 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3]/C + clock pessimism 0.037 -0.334 + SLICE_X118Y50 FDRE (Hold_fdre_C_D) 0.107 -0.227 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_do_re_reg[3] + ------------------------------------------------------------------- + required time 0.227 + arrival time -0.117 + ------------------------------------------------------------------- + slack 0.111 + +Slack (MET) : 0.112ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.428ns (logic 0.141ns (32.928%) route 0.287ns (67.072%)) + Logic Levels: 0 + Clock Path Skew: 0.261ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.490ns + Source Clock Delay (SCD): -0.711ns + Clock Pessimism Removal (CPR): -0.040ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.552 -0.711 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X85Y171 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/C + ------------------------------------------------------------------- ------------------- + SLICE_X85Y171 FDCE (Prop_fdce_C_Q) 0.141 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[12]/Q + net (fo=14, routed) 0.287 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s1_reg[23]_1[12] + SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.817 -0.490 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/sys_clk + SLICE_X81Y173 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12]/C + clock pessimism 0.040 -0.450 + SLICE_X81Y173 FDCE (Hold_fdce_C_D) 0.055 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s2_reg[12] + ------------------------------------------------------------------- + required time 0.395 + arrival time -0.283 + ------------------------------------------------------------------- + slack 0.112 + +Slack (MET) : 0.114ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.488ns (logic 0.231ns (47.314%) route 0.257ns (52.686%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.267ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.399ns + Source Clock Delay (SCD): -0.629ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.633 -0.629 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/sys_clk + SLICE_X83Y93 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/C + ------------------------------------------------------------------- ------------------- + SLICE_X83Y93 FDCE (Prop_fdce_C_Q) 0.128 -0.501 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10/Q + net (fo=118, routed) 0.257 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_rep__10_n_0 + SLICE_X85Y98 LUT2 (Prop_lut2_I0_O) 0.103 -0.141 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1/O + net (fo=1, routed) 0.000 -0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf[1360]_i_1_n_0 + SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.909 -0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/sys_clk + SLICE_X85Y98 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360]/C + clock pessimism 0.037 -0.362 + SLICE_X85Y98 FDCE (Hold_fdce_C_D) 0.107 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/squeeze_buf_reg[1360] + ------------------------------------------------------------------- + required time 0.255 + arrival time -0.141 + ------------------------------------------------------------------- + slack 0.114 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/confreg_int_edge_reg[3]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.402ns (logic 0.209ns (51.988%) route 0.193ns (48.012%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.798 -0.465 u_confreg/sys_clk + SLICE_X2Y49 FDRE r u_confreg/confreg_int_edge_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X2Y49 FDRE (Prop_fdre_C_Q) 0.164 -0.301 r u_confreg/confreg_int_edge_reg[3]/Q + net (fo=3, routed) 0.193 -0.108 u_confreg/u_int_ctrl/edge_int_state_reg[31]_1[3] + SLICE_X3Y50 LUT5 (Prop_lut5_I0_O) 0.045 -0.063 r u_confreg/u_int_ctrl/edge_int_state[3]_i_1/O + net (fo=1, routed) 0.000 -0.063 u_confreg/u_int_ctrl/edge_int_state[3]_i_1_n_0 + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.003 -0.305 u_confreg/u_int_ctrl/sys_clk + SLICE_X3Y50 FDCE r u_confreg/u_int_ctrl/edge_int_state_reg[3]/C + clock pessimism 0.037 -0.268 + SLICE_X3Y50 FDCE (Hold_fdce_C_D) 0.091 -0.177 u_confreg/u_int_ctrl/edge_int_state_reg[3] + ------------------------------------------------------------------- + required time 0.177 + arrival time -0.063 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.115ns (arrival time - required time) + Source: u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.387ns (logic 0.141ns (36.445%) route 0.246ns (63.555%)) + Logic Levels: 0 + Clock Path Skew: 0.196ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): -0.465ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.798 -0.465 u_confreg/u_int_ctrl/sys_clk + SLICE_X1Y49 FDCE r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_confreg/u_int_ctrl/int_in_sync_d2_reg[5]/Q + net (fo=3, routed) 0.246 -0.078 u_confreg/u_int_ctrl/int_in_sync_d2[5] + SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.003 -0.305 u_confreg/u_int_ctrl/sys_clk + SLICE_X3Y51 FDCE r u_confreg/u_int_ctrl/int_in_sync_d3_reg[5]/C + clock pessimism 0.037 -0.268 + SLICE_X3Y51 FDCE (Hold_fdce_C_D) 0.075 -0.193 u_confreg/u_int_ctrl/int_in_sync_d3_reg[5] + ------------------------------------------------------------------- + required time 0.193 + arrival time -0.078 + ------------------------------------------------------------------- + slack 0.115 + +Slack (MET) : 0.116ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.465ns (logic 0.141ns (30.326%) route 0.324ns (69.674%)) + Logic Levels: 0 + Clock Path Skew: 0.277ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.387ns + Source Clock Delay (SCD): -0.619ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.644 -0.619 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X157Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X157Y151 FDCE (Prop_fdce_C_Q) 0.141 -0.478 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p11_reg[19]/Q + net (fo=15, routed) 0.324 -0.154 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/Q[19] + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/sys_clk + SLICE_X159Y140 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19]/C + clock pessimism 0.045 -0.342 + SLICE_X159Y140 FDCE (Hold_fdce_C_D) 0.072 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/u_bc/p21_reg[19] + ------------------------------------------------------------------- + required time 0.270 + arrival time -0.154 + ------------------------------------------------------------------- + slack 0.116 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 ------------------------------------------------------------------- slack 0.117 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMA_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/WADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMC_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.117ns (arrival time - required time) + Source: u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.622ns (logic 0.164ns (26.372%) route 0.458ns (73.628%)) + Logic Levels: 0 + Clock Path Skew: 0.194ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.164 -0.331 r u_Axi_CDC/rFifo/pushCC_pushPtr_reg[0]/Q + net (fo=62, routed) 0.458 0.127 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/ADDRD0 + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/ADR0 + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMS32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1/CLK + clock pessimism 0.037 -0.300 + SLICE_X16Y54 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 0.010 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMD_D1 + ------------------------------------------------------------------- + required time -0.010 + arrival time 0.127 + ------------------------------------------------------------------- + slack 0.117 + +Slack (MET) : 0.118ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.013%) route 0.266ns (55.987%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.623 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X144Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.266 -0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.165 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1/O + net (fo=1, routed) 0.000 -0.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][8]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.887 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8]/C + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.092 -0.283 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][8] + ------------------------------------------------------------------- + required time 0.283 + arrival time -0.165 + ------------------------------------------------------------------- + slack 0.118 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.475ns (logic 0.209ns (44.040%) route 0.266ns (55.960%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: 0.264ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.403ns + Source Clock Delay (SCD): -0.630ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.632 -0.630 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk + SLICE_X84Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/C + ------------------------------------------------------------------- ------------------- + SLICE_X84Y61 FDRE (Prop_fdre_C_Q) 0.164 -0.466 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][7]__0/Q + net (fo=6, routed) 0.266 -0.201 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_im_reg[511][14]__0_0[7] + SLICE_X82Y61 LUT6 (Prop_lut6_I3_O) 0.045 -0.156 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/bf1_do_re[7]_i_1/O + net (fo=1, routed) 0.000 -0.156 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_sp_re[7] + SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.905 -0.403 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/sys_clk + SLICE_X82Y61 FDRE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7]/C + clock pessimism 0.037 -0.366 + SLICE_X82Y61 FDRE (Hold_fdre_C_D) 0.092 -0.274 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_do_re_reg[7] + ------------------------------------------------------------------- + required time 0.274 + arrival time -0.156 + ------------------------------------------------------------------- + slack 0.119 + +Slack (MET) : 0.119ns (arrival time - required time) + Source: u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: sys_clk Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns + Destination Clock Delay (DCD): -0.418ns + Source Clock Delay (SCD): -0.645ns + Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7931,12 +5793,12 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=35652, routed) 0.618 -0.645 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/C ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + SLICE_X39Y105 FDRE (Prop_fdre_C_Q) 0.141 -0.504 r u_matmul_axi_slave/mult_inst[3].u_mult/prod_reg[59]/Q + net (fo=1, routed) 0.056 -0.448 u_matmul_axi_slave/mult_inst[3].u_mult/prod[59] + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -7948,15 +5810,70 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=35652, routed) 0.890 -0.418 u_matmul_axi_slave/mult_inst[3].u_mult/sys_clk + SLICE_X39Y105 FDRE r u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59]/C + clock pessimism -0.227 -0.645 + SLICE_X39Y105 FDRE (Hold_fdre_C_D) 0.078 -0.567 u_matmul_axi_slave/mult_inst[3].u_mult/p_reg[59] ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 + required time 0.567 + arrival time -0.448 ------------------------------------------------------------------- - slack 0.121 + slack 0.119 + +Slack (MET) : 0.120ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: sys_clk + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.476ns (logic 0.209ns (43.921%) route 0.267ns (56.079%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.265ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.420ns + Source Clock Delay (SCD): -0.640ns + Clock Pessimism Removal (CPR): -0.045ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.623 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X144Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/C + ------------------------------------------------------------------- ------------------- + SLICE_X144Y148 FDCE (Prop_fdce_C_Q) 0.164 -0.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4/Q + net (fo=127, routed) 0.267 -0.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt_reg[1]_rep__4_n_0 + SLICE_X151Y155 LUT5 (Prop_lut5_I1_O) 0.045 -0.164 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1/O + net (fo=1, routed) 0.000 -0.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A[127][6]_i_1_n_0 + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.887 -0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/sys_clk + SLICE_X151Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6]/C + clock pessimism 0.045 -0.375 + SLICE_X151Y155 FDCE (Hold_fdce_C_D) 0.091 -0.284 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[127][6] + ------------------------------------------------------------------- + required time 0.284 + arrival time -0.164 + ------------------------------------------------------------------- + slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C @@ -7969,9 +5886,9 @@ Slack (MET) : 0.121ns (arrival time - required time) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.234ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -7984,12 +5901,12 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D + SLICE_X9Y43 FDCE (Prop_fdce_C_Q) 0.141 -0.354 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q + net (fo=1, routed) 0.056 -0.298 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -8001,970 +5918,16 @@ Slack (MET) : 0.121ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.234 -0.495 + SLICE_X9Y43 FDCE (Hold_fdce_C_D) 0.076 -0.419 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 + required time 0.419 + arrival time -0.298 ------------------------------------------------------------------- slack 0.121 -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.999 -0.309 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/C - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.659 -0.603 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.569ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.693 -0.569 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.569 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.075 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.494 - arrival time -0.372 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.229 -0.570 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X113Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.226 -0.615 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.540 - arrival time -0.418 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.059 -0.267 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.236 -0.467 - SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.076 -0.391 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.391 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.203ns (logic 0.141ns (69.572%) route 0.062ns (30.428%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.062 -0.264 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.236 -0.467 - SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.078 -0.389 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.389 - arrival time -0.264 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.071 -0.501 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.501 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.071 -0.505 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.505 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.126 - @@ -8977,6152 +5940,157 @@ Period(ns): 20.000 Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X1Y28 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y11 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X5Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y7 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X5Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y27 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y26 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_im_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X7Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/TW/ff_re_reg/CLKARDCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y16 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y34 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK +Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X7Y18 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y35 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X7Y30 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK +Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X6Y31 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y66 u_cdma_matmul_bridge/load_next_idx_reg[15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[17]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[18]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y67 u_cdma_matmul_bridge/load_next_idx_reg[19]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y63 u_cdma_matmul_bridge/load_next_idx_reg[1]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[20]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[21]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[22]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y68 u_cdma_matmul_bridge/load_next_idx_reg[23]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X62Y69 u_cdma_matmul_bridge/load_next_idx_reg[24]/C +Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X141Y157 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[105][11]/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.054ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 - ------------------------------------------------------------------- - slack 0.054 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.113ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.678ns (logic 0.478ns (70.458%) route 0.200ns (29.542%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O - net (fo=1, routed) 0.200 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 0.014 - arrival time 0.099 - ------------------------------------------------------------------- - slack 0.113 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.641ns (logic 0.394ns (61.457%) route 0.247ns (38.543%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/O - net (fo=1, routed) 0.247 0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[38] - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y76 FDRE (Hold_fdre_C_D) -0.007 -0.069 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.069 - arrival time 0.058 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.129ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.720ns (logic 0.478ns (66.344%) route 0.242ns (33.656%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.242 0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[37] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.137 - ------------------------------------------------------------------- - slack 0.129 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.629ns (logic 0.394ns (62.601%) route 0.235ns (37.399%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/O - net (fo=1, routed) 0.235 0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[32] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) -0.027 -0.085 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.085 - arrival time 0.049 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.725ns (logic 0.388ns (53.539%) route 0.337ns (46.461%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O - net (fo=1, routed) 0.337 0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.066 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time -0.004 - arrival time 0.141 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.666ns (logic 0.492ns (73.905%) route 0.174ns (26.095%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.090 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.174 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.006 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42] - ------------------------------------------------------------------- - required time 0.054 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.668ns (logic 0.492ns (73.684%) route 0.176ns (26.316%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O - net (fo=1, routed) 0.176 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.005 -0.055 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.055 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.734ns (logic 0.386ns (52.563%) route 0.348ns (47.437%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.348 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[41] - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.386ns (52.125%) route 0.355ns (47.875%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.355 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.072 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.160 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.153ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.670ns (logic 0.394ns (58.792%) route 0.276ns (41.208%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/O - net (fo=1, routed) 0.276 0.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[32] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) -0.003 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.063 - arrival time 0.090 - ------------------------------------------------------------------- - slack 0.153 - -Slack (MET) : 0.157ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.681ns (logic 0.390ns (57.280%) route 0.291ns (42.720%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/O - net (fo=1, routed) 0.291 0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[40] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.002 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40] - ------------------------------------------------------------------- - required time 0.060 - arrival time 0.097 - ------------------------------------------------------------------- - slack 0.157 - -Slack (MET) : 0.167ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.767ns (logic 0.164ns (21.391%) route 0.603ns (78.609%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.603 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.076 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.029 - arrival time 0.196 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.170ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.754ns (logic 0.141ns (18.697%) route 0.613ns (81.303%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.613 0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] - SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X16Y86 FDCE (Hold_fdce_C_D) 0.059 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.183 - ------------------------------------------------------------------- - slack 0.170 - -Slack (MET) : 0.182ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.775ns (logic 0.478ns (61.697%) route 0.297ns (38.303%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.297 0.195 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[49] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.071 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49] - ------------------------------------------------------------------- - required time -0.013 - arrival time 0.195 - ------------------------------------------------------------------- - slack 0.182 - -Slack (MET) : 0.194ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.714ns (logic 0.394ns (55.191%) route 0.320ns (44.809%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/O - net (fo=1, routed) 0.320 0.132 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[44] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) -0.001 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44] - ------------------------------------------------------------------- - required time 0.063 - arrival time 0.132 - ------------------------------------------------------------------- - slack 0.194 - -Slack (MET) : 0.195ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.388ns (50.735%) route 0.377ns (49.265%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.377 0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[33] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 0.011 - arrival time 0.184 - ------------------------------------------------------------------- - slack 0.195 - -Slack (MET) : 0.198ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.768ns (logic 0.141ns (18.369%) route 0.627ns (81.631%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.627 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.046 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.198 - -Slack (MET) : 0.205ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.775ns (logic 0.141ns (18.187%) route 0.634ns (81.813%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.634 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.046 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.193 - ------------------------------------------------------------------- - slack 0.205 - -Slack (MET) : 0.220ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.738ns (logic 0.128ns (17.350%) route 0.610ns (82.650%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.610 0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) -0.006 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.099 - arrival time 0.121 - ------------------------------------------------------------------- - slack 0.220 - -Slack (MET) : 0.225ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.748ns (logic 0.390ns (52.130%) route 0.358ns (47.870%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.358 0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[34] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.002 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.168 - ------------------------------------------------------------------- - slack 0.225 - -Slack (MET) : 0.227ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.815ns (logic 0.141ns (17.291%) route 0.674ns (82.709%)) - Logic Levels: 0 - Clock Path Skew: 0.322ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.361ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.674 0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] - SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.947 -0.361 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.262 - clock uncertainty 0.197 -0.066 - SLICE_X32Y74 FDCE (Hold_fdce_C_D) 0.070 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.004 - arrival time 0.231 - ------------------------------------------------------------------- - slack 0.227 - -Slack (MET) : 0.228ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.766ns (logic 0.128ns (16.716%) route 0.638ns (83.284%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.128 -0.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.638 0.181 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.018 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.181 - ------------------------------------------------------------------- - slack 0.228 - -Slack (MET) : 0.234ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.781ns (logic 0.148ns (18.960%) route 0.633ns (81.040%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.148 -0.422 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.633 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.023 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.024 - arrival time 0.210 - ------------------------------------------------------------------- - slack 0.234 - -Slack (MET) : 0.236ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.831ns (logic 0.386ns (46.464%) route 0.445ns (53.536%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.445 0.250 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[35] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.072 0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time -0.014 - arrival time 0.250 - ------------------------------------------------------------------- - slack 0.236 - -Slack (MET) : 0.238ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.827ns (logic 0.141ns (17.044%) route 0.686ns (82.956%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.686 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.070 0.005 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.005 - arrival time 0.243 - ------------------------------------------------------------------- - slack 0.238 - -Slack (MET) : 0.241ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.823ns (logic 0.388ns (47.171%) route 0.435ns (52.829%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.435 0.242 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[33] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.061 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time -0.001 - arrival time 0.242 - ------------------------------------------------------------------- - slack 0.241 - -Slack (MET) : 0.257ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.827ns (logic 0.141ns (17.047%) route 0.686ns (82.953%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.686 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.047 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.245 - ------------------------------------------------------------------- - slack 0.257 - -Slack (MET) : 0.259ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.857ns (logic 0.164ns (19.129%) route 0.693ns (80.871%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.693 0.287 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.075 0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.028 - arrival time 0.287 - ------------------------------------------------------------------- - slack 0.259 - -Slack (MET) : 0.259ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.788ns (logic 0.492ns (62.440%) route 0.296ns (37.560%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O - net (fo=1, routed) 0.296 0.211 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.009 -0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.049 - arrival time 0.211 - ------------------------------------------------------------------- - slack 0.259 - -Slack (MET) : 0.262ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.788ns (logic 0.492ns (62.458%) route 0.296ns (37.542%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.296 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] - SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X26Y70 FDRE (Hold_fdre_C_D) 0.004 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48] - ------------------------------------------------------------------- - required time 0.054 - arrival time 0.208 - ------------------------------------------------------------------- - slack 0.262 - -Slack (MET) : 0.272ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.793ns (logic 0.492ns (62.032%) route 0.301ns (37.968%)) - Logic Levels: 0 - Clock Path Skew: 0.320ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.358ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.301 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] - SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.950 -0.358 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C - clock pessimism 0.099 -0.259 - clock uncertainty 0.197 -0.063 - SLICE_X25Y74 FDRE (Hold_fdre_C_D) 0.004 -0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 0.059 - arrival time 0.214 - ------------------------------------------------------------------- - slack 0.272 - -Slack (MET) : 0.287ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.856ns (logic 0.141ns (16.478%) route 0.715ns (83.522%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.715 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.048 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.287 - -Slack (MET) : 0.289ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.861ns (logic 0.141ns (16.382%) route 0.720ns (83.618%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.720 0.278 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.011 - arrival time 0.278 - ------------------------------------------------------------------- - slack 0.289 - -Slack (MET) : 0.319ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.916ns (logic 0.478ns (52.162%) route 0.438ns (47.838%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.104 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/O - net (fo=1, routed) 0.438 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[43] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.075 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43] - ------------------------------------------------------------------- - required time -0.015 - arrival time 0.334 - ------------------------------------------------------------------- - slack 0.319 - -Slack (MET) : 0.351ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.478ns (51.242%) route 0.455ns (48.758%)) - Logic Levels: 0 - Clock Path Skew: 0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.455 0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49] - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.353 - ------------------------------------------------------------------- - slack 0.351 - -Slack (MET) : 0.363ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.879ns (logic 0.128ns (14.560%) route 0.751ns (85.440%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.751 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.067 - arrival time 0.297 - ------------------------------------------------------------------- - slack 0.363 - -Slack (MET) : 0.364ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.953ns (logic 0.388ns (40.695%) route 0.565ns (59.305%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O - net (fo=1, routed) 0.565 0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.070 0.010 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time -0.010 - arrival time 0.374 - ------------------------------------------------------------------- - slack 0.364 - -Slack (MET) : 0.389ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.957ns (logic 0.141ns (14.730%) route 0.816ns (85.270%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.816 0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.014 - arrival time 0.375 - ------------------------------------------------------------------- - slack 0.389 - -Slack (MET) : 0.405ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.922ns (logic 0.128ns (13.878%) route 0.794ns (86.122%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.794 0.340 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) -0.007 -0.065 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.065 - arrival time 0.340 - ------------------------------------------------------------------- - slack 0.405 - -Slack (MET) : 0.464ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.033ns (logic 0.141ns (13.645%) route 0.892ns (86.355%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=2, routed) 0.892 0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.417 - ------------------------------------------------------------------- - slack 0.464 - -Slack (MET) : 0.480ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.000ns (logic 0.492ns (49.207%) route 0.508ns (50.793%)) - Logic Levels: 0 - Clock Path Skew: 0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.508 0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.004 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48] - ------------------------------------------------------------------- - required time 0.060 - arrival time 0.420 - ------------------------------------------------------------------- - slack 0.480 - -Slack (MET) : 0.497ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.967ns (logic 0.394ns (40.759%) route 0.573ns (59.241%)) - Logic Levels: 0 - Clock Path Skew: 0.283ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.573 0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[2] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.010 -0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 0.115 - arrival time 0.382 - ------------------------------------------------------------------- - slack 0.497 - -Slack (MET) : 0.502ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.108ns (logic 0.386ns (34.837%) route 0.722ns (65.163%)) - Logic Levels: 0 - Clock Path Skew: 0.339ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.387ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.722 0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[11] - SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.288 - clock uncertainty 0.197 -0.092 - SLICE_X110Y72 FDRE (Hold_fdre_C_D) 0.070 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 0.022 - arrival time 0.481 - ------------------------------------------------------------------- - slack 0.502 - -Slack (MET) : 0.533ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.124ns (logic 0.388ns (34.515%) route 0.736ns (65.485%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.736 0.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[9] - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X100Y72 FDRE (Hold_fdre_C_D) 0.063 -0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 0.037 - arrival time 0.497 - ------------------------------------------------------------------- - slack 0.533 - -Slack (MET) : 0.632ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.187ns (logic 0.386ns (32.521%) route 0.801ns (67.479%)) - Logic Levels: 0 - Clock Path Skew: 0.282ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O - net (fo=1, routed) 0.801 0.604 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) 0.076 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 0.029 - arrival time 0.604 - ------------------------------------------------------------------- - slack 0.632 - -Slack (MET) : 0.642ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.159ns (logic 0.394ns (33.980%) route 0.765ns (66.020%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.765 0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[8] - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X100Y72 FDRE (Hold_fdre_C_D) -0.010 -0.110 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 0.110 - arrival time 0.532 - ------------------------------------------------------------------- - slack 0.642 - -Slack (MET) : 0.658ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.258ns (logic 0.386ns (30.689%) route 0.872ns (69.311%)) - Logic Levels: 0 - Clock Path Skew: 0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.385ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.872 0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[35] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.286 - clock uncertainty 0.197 -0.090 - SLICE_X116Y77 FDRE (Hold_fdre_C_D) 0.063 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.631 - ------------------------------------------------------------------- - slack 0.658 - -Slack (MET) : 0.705ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.170ns (logic 0.390ns (33.342%) route 0.780ns (66.658%)) - Logic Levels: 0 - Clock Path Skew: 0.283ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.780 0.585 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[4] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.015 -0.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 0.120 - arrival time 0.585 - ------------------------------------------------------------------- - slack 0.705 - - - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 - ------------------------------------------------------------------- - slack 0.032 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.656ns (logic 0.492ns (75.032%) route 0.164ns (24.968%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O - net (fo=1, routed) 0.164 0.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.004 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.050 - arrival time 0.078 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.130ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.648ns (logic 0.394ns (60.840%) route 0.254ns (39.160%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.254 0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) -0.007 -0.064 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.064 - arrival time 0.066 - ------------------------------------------------------------------- - slack 0.130 - -Slack (MET) : 0.142ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.739ns (logic 0.478ns (64.724%) route 0.261ns (35.276%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.146 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.261 0.114 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.072 -0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25] - ------------------------------------------------------------------- - required time 0.028 - arrival time 0.114 - ------------------------------------------------------------------- - slack 0.142 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.492ns (73.994%) route 0.173ns (26.006%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.399ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.173 0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.909 -0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C - clock pessimism 0.099 -0.300 - clock uncertainty 0.197 -0.104 - SLICE_X62Y76 FDRE (Hold_fdre_C_D) -0.007 -0.111 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 0.111 - arrival time 0.038 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.172ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.699ns (logic 0.390ns (55.761%) route 0.309ns (44.239%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.309 0.075 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.003 -0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 0.097 - arrival time 0.075 - ------------------------------------------------------------------- - slack 0.172 - -Slack (MET) : 0.172ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.141ns (19.033%) route 0.600ns (80.967%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.600 0.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.125 - ------------------------------------------------------------------- - slack 0.172 - -Slack (MET) : 0.173ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.390ns (56.076%) route 0.305ns (43.924%)) - Logic Levels: 0 - Clock Path Skew: 0.322ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK - SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.305 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X28Y72 FDRE (Hold_fdre_C_D) 0.004 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.115 - ------------------------------------------------------------------- - slack 0.173 - -Slack (MET) : 0.178ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.141ns (18.448%) route 0.623ns (81.552%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 0.623 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.061 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time -0.015 - arrival time 0.193 - ------------------------------------------------------------------- - slack 0.178 - -Slack (MET) : 0.180ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.709ns (logic 0.390ns (55.003%) route 0.319ns (44.997%)) - Logic Levels: 0 - Clock Path Skew: 0.330ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.319 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.002 -0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 0.098 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.180 - -Slack (MET) : 0.187ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.766ns (logic 0.164ns (21.399%) route 0.602ns (78.601%)) - Logic Levels: 0 - Clock Path Skew: 0.337ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.612ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.164 -0.448 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q - net (fo=2, routed) 0.602 0.154 u_fft_mlkem_axi_slave/mlkem_intr_m - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - clock pessimism 0.099 -0.275 - clock uncertainty 0.197 -0.079 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.046 -0.033 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] - ------------------------------------------------------------------- - required time 0.033 - arrival time 0.154 - ------------------------------------------------------------------- - slack 0.187 - -Slack (MET) : 0.189ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.758ns (logic 0.141ns (18.596%) route 0.617ns (81.404%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.617 0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X114Y76 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.143 - ------------------------------------------------------------------- - slack 0.189 - -Slack (MET) : 0.199ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.767ns (logic 0.141ns (18.390%) route 0.626ns (81.610%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.626 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.048 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.199 - -Slack (MET) : 0.200ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.721ns (logic 0.390ns (54.106%) route 0.331ns (45.894%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.331 0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) -0.009 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 0.107 - arrival time 0.093 - ------------------------------------------------------------------- - slack 0.200 - -Slack (MET) : 0.211ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.780ns (logic 0.141ns (18.081%) route 0.639ns (81.919%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.639 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.019 - arrival time 0.192 - ------------------------------------------------------------------- - slack 0.211 - -Slack (MET) : 0.216ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.790ns (logic 0.141ns (17.837%) route 0.649ns (82.163%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.649 0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.240 - clock uncertainty 0.197 -0.044 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.047 0.003 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.003 - arrival time 0.219 - ------------------------------------------------------------------- - slack 0.216 - -Slack (MET) : 0.221ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.844ns (logic 0.386ns (45.725%) route 0.458ns (54.275%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.458 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.221 - -Slack (MET) : 0.228ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.822ns (logic 0.388ns (47.208%) route 0.434ns (52.792%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 0.434 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.245 - ------------------------------------------------------------------- - slack 0.228 - -Slack (MET) : 0.233ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.802ns (logic 0.141ns (17.574%) route 0.661ns (82.426%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.661 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.220 - ------------------------------------------------------------------- - slack 0.233 - -Slack (MET) : 0.234ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.803ns (logic 0.141ns (17.555%) route 0.662ns (82.445%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.662 0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.047 -0.018 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.018 - arrival time 0.216 - ------------------------------------------------------------------- - slack 0.234 - -Slack (MET) : 0.236ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.807ns (logic 0.141ns (17.466%) route 0.666ns (82.534%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.666 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.236 - -Slack (MET) : 0.238ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.811ns (logic 0.141ns (17.379%) route 0.670ns (82.621%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.670 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.240 - clock uncertainty 0.197 -0.044 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.046 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.238 - -Slack (MET) : 0.241ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.746ns (logic 0.492ns (65.912%) route 0.254ns (34.088%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.254 0.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) -0.019 -0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 0.119 - arrival time 0.122 - ------------------------------------------------------------------- - slack 0.241 - -Slack (MET) : 0.246ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.850ns (logic 0.388ns (45.663%) route 0.462ns (54.337%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.462 0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.076 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 0.021 - arrival time 0.225 - ------------------------------------------------------------------- - slack 0.246 - -Slack (MET) : 0.247ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.848ns (logic 0.386ns (45.530%) route 0.462ns (54.470%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.462 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.076 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 0.024 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.247 - -Slack (MET) : 0.249ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.822ns (logic 0.386ns (46.947%) route 0.436ns (53.053%)) - Logic Levels: 0 - Clock Path Skew: 0.330ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.436 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.047 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 0.053 - arrival time 0.196 - ------------------------------------------------------------------- - slack 0.249 - -Slack (MET) : 0.252ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.824ns (logic 0.141ns (17.122%) route 0.683ns (82.878%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.683 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.252 - -Slack (MET) : 0.255ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.845ns (logic 0.478ns (56.587%) route 0.367ns (43.413%)) - Logic Levels: 0 - Clock Path Skew: 0.321ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.367 0.263 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.072 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.255 - -Slack (MET) : 0.256ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.828ns (logic 0.141ns (17.038%) route 0.687ns (82.962%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.687 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.244 - ------------------------------------------------------------------- - slack 0.256 - -Slack (MET) : 0.260ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.829ns (logic 0.141ns (16.998%) route 0.688ns (83.002%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.588ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.674 -0.588 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.447 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.688 0.241 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X30Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.019 - arrival time 0.241 - ------------------------------------------------------------------- - slack 0.260 - -Slack (MET) : 0.261ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.776ns (logic 0.128ns (16.502%) route 0.648ns (83.498%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.648 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X114Y76 FDCE (Hold_fdce_C_D) -0.008 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.101 - arrival time 0.160 - ------------------------------------------------------------------- - slack 0.261 - -Slack (MET) : 0.266ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.785ns (logic 0.128ns (16.296%) route 0.657ns (83.704%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.128 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 0.657 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) -0.006 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.052 - arrival time 0.214 - ------------------------------------------------------------------- - slack 0.266 - -Slack (MET) : 0.268ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.823ns (logic 0.394ns (47.859%) route 0.429ns (52.141%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.429 0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) -0.001 -0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 0.066 - arrival time 0.202 - ------------------------------------------------------------------- - slack 0.268 - -Slack (MET) : 0.290ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.868ns (logic 0.478ns (55.096%) route 0.390ns (44.904%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.149 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.390 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.047 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 0.050 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.290 - -Slack (MET) : 0.311ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.837ns (logic 0.394ns (47.100%) route 0.443ns (52.900%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.443 0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.002 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 0.099 - arrival time 0.212 - ------------------------------------------------------------------- - slack 0.311 - -Slack (MET) : 0.319ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.942ns (logic 0.388ns (41.191%) route 0.554ns (58.809%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 0.554 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.066 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time -0.001 - arrival time 0.321 - ------------------------------------------------------------------- - slack 0.319 - -Slack (MET) : 0.323ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.955ns (logic 0.388ns (40.612%) route 0.567ns (59.388%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.567 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.076 0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time -0.011 - arrival time 0.334 - ------------------------------------------------------------------- - slack 0.323 - -Slack (MET) : 0.346ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.883ns (logic 0.128ns (14.500%) route 0.755ns (85.500%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.755 0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X26Y73 FDCE (Hold_fdce_C_D) 0.016 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.300 - ------------------------------------------------------------------- - slack 0.346 - -Slack (MET) : 0.347ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.851ns (logic 0.394ns (46.280%) route 0.457ns (53.720%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.457 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.026 -0.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 0.123 - arrival time 0.224 - ------------------------------------------------------------------- - slack 0.347 - -Slack (MET) : 0.402ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.983ns (logic 0.141ns (14.340%) route 0.842ns (85.660%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.842 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y73 FDCE (Hold_fdce_C_D) 0.061 -0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.001 - arrival time 0.401 - ------------------------------------------------------------------- - slack 0.402 - -Slack (MET) : 0.410ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.005ns (logic 0.388ns (38.609%) route 0.617ns (61.391%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 0.617 0.424 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.070 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time -0.013 - arrival time 0.424 - ------------------------------------------------------------------- - slack 0.410 - -Slack (MET) : 0.416ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.986ns (logic 0.492ns (49.918%) route 0.494ns (50.082%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.129 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.494 0.364 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.012 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 0.052 - arrival time 0.364 - ------------------------------------------------------------------- - slack 0.416 - -Slack (MET) : 0.420ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.054ns (logic 0.386ns (36.630%) route 0.668ns (63.370%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.668 0.432 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.076 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.432 - ------------------------------------------------------------------- - slack 0.420 - - +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y61 axi4WriteOnlyArbiter_6/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_18_23/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y76 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y80 u_matmul_axi_slave/b1_c_reg_r2_0_15_42_47/RAMD_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMB_D1/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMC_D1/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD/CLK +Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X18Y72 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMD_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X2Y45 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_12_17/RAMD_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMA_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMB_D1/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC/CLK +High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMC_D1/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD/CLK +High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y82 u_matmul_axi_slave/b1_c_reg_r1_0_15_24_29/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y84 u_matmul_axi_slave/b1_c_reg_r1_0_15_42_47/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y81 u_matmul_axi_slave/b1_c_reg_r1_0_15_48_53/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMA_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMB_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMC_D1/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD/CLK +High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y83 u_matmul_axi_slave/b1_c_reg_r1_0_15_54_59/RAMD_D1/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA/CLK +High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y74 u_matmul_axi_slave/b1_c_reg_r2_0_15_0_5/RAMA_D1/CLK @@ -15132,508 +6100,13 @@ From Clock: cpu_clk To Clock: cpu_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.651ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.727ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) +Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR @@ -15641,122 +6114,12 @@ Slack (MET) : 0.885ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -15768,15 +6131,15 @@ Slack (MET) : 0.936ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -15787,403 +6150,18 @@ Slack (MET) : 0.936ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y39 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 + required time 0.573 + arrival time 0.154 ------------------------------------------------------------------- - slack 0.936 + slack 0.727 -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.005ns (arrival time - required time) +Slack (MET) : 0.727ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR @@ -16191,12 +6169,12 @@ Slack (MET) : 1.005ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) + Data Path Delay: 0.651ns (logic 0.227ns (34.873%) route 0.424ns (65.127%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16208,15 +6186,15 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.143 0.154 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y39 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16227,18 +6205,73 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y39 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.218 -0.481 + SLICE_X11Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.573 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 + required time 0.573 + arrival time 0.154 ------------------------------------------------------------------- - slack 1.005 + slack 0.727 -Slack (MET) : 1.005ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.547 + arrival time 0.218 + ------------------------------------------------------------------- + slack 0.765 + +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR @@ -16246,12 +6279,12 @@ Slack (MET) : 1.005ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16263,15 +6296,15 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16282,73 +6315,18 @@ Slack (MET) : 1.005ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.005 + slack 0.765 -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR @@ -16356,12 +6334,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16373,15 +6351,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16392,73 +6370,18 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR @@ -16466,12 +6389,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16483,15 +6406,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16502,18 +6425,18 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR @@ -16521,12 +6444,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16538,15 +6461,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16557,73 +6480,18 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.765ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR @@ -16631,12 +6499,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16648,15 +6516,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X10Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16667,18 +6535,18 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X10Y40 FDCE (Remov_fdce_C_CLR) -0.067 -0.547 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.547 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.012 + slack 0.765 -Slack (MET) : 1.012ns (arrival time - required time) +Slack (MET) : 0.790ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR @@ -16686,12 +6554,12 @@ Slack (MET) : 1.012ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) + Data Path Delay: 0.736ns (logic 0.227ns (30.836%) route 0.509ns (69.164%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.263ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16703,15 +6571,15 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.228 0.239 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y39 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16722,31 +6590,31 @@ Slack (MET) : 1.012ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y39 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.196 -0.459 + SLICE_X13Y39 FDCE (Remov_fdce_C_CLR) -0.092 -0.551 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 + required time 0.551 + arrival time 0.239 ------------------------------------------------------------------- - slack 1.012 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16758,15 +6626,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16777,31 +6645,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16813,15 +6681,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16832,31 +6700,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16868,15 +6736,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/buffers_1_reg + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16887,31 +6755,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16923,15 +6791,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16942,31 +6810,31 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.790ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) + Data Path Delay: 0.715ns (logic 0.227ns (31.738%) route 0.488ns (68.262%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.017ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -16978,15 +6846,15 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.207 0.218 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X11Y40 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -16997,348 +6865,18 @@ Slack (MET) : 1.290ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.218 -0.480 + SLICE_X11Y40 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 + required time 0.572 + arrival time 0.218 ------------------------------------------------------------------- - slack 1.290 + slack 0.790 -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR @@ -17346,12 +6884,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17363,15 +6901,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17382,18 +6920,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR @@ -17401,12 +6939,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17418,15 +6956,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17437,18 +6975,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR @@ -17456,12 +6994,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17473,15 +7011,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17492,18 +7030,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR @@ -17511,12 +7049,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17528,15 +7066,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17547,18 +7085,18 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.356ns (arrival time - required time) +Slack (MET) : 0.853ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR @@ -17566,12 +7104,12 @@ Slack (MET) : 1.356ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.797ns (logic 0.186ns (23.350%) route 0.611ns (76.650%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.011ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17583,15 +7121,15 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.259 0.329 u_Axi_CDC/awFifo/p_0_in + SLICE_X10Y44 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17602,18 +7140,1173 @@ Slack (MET) : 1.356ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X10Y44 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 + required time 0.524 + arrival time 0.329 ------------------------------------------------------------------- - slack 1.356 + slack 0.853 -Slack (MET) : 1.366ns (arrival time - required time) +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.860ns (logic 0.186ns (21.633%) route 0.674ns (78.367%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.322 0.392 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in + SLICE_X10Y41 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.392 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.917ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.865ns (logic 0.227ns (26.247%) route 0.638ns (73.753%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.357 0.368 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X13Y43 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.368 + ------------------------------------------------------------------- + slack 0.917 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.970ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.918ns (logic 0.227ns (24.721%) route 0.691ns (75.279%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.410 0.421 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 + SLICE_X13Y44 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X13Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.549 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.549 + arrival time 0.421 + ------------------------------------------------------------------- + slack 0.970 + +Slack (MET) : 0.994ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.524 + arrival time 0.470 + ------------------------------------------------------------------- + slack 0.994 + +Slack (MET) : 0.994ns (arrival time - required time) Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR @@ -17621,12 +8314,12 @@ Slack (MET) : 1.366ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.358ns (logic 0.227ns (16.717%) route 1.131ns (83.283%)) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.059ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17638,15 +8331,15 @@ Slack (MET) : 1.366ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.924 0.783 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17657,31 +8350,31 @@ Slack (MET) : 1.366ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/cpu_clk - SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.516 - SLICE_X6Y74 FDCE (Remov_fdce_C_CLR) -0.067 -0.583 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.583 - arrival time 0.783 + required time 0.524 + arrival time 0.470 ------------------------------------------------------------------- - slack 1.366 + slack 0.994 -Slack (MET) : 1.381ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.994ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17693,15 +8386,15 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17712,31 +8405,31 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.524 + arrival time 0.470 ------------------------------------------------------------------- - slack 1.381 + slack 0.994 -Slack (MET) : 1.381ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C +Slack (MET) : 0.994ns (arrival time - required time) + Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 0.967ns (logic 0.227ns (23.471%) route 0.740ns (76.529%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.040ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.497ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17748,15 +8441,15 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk + SLICE_X11Y38 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X11Y38 FDCE (Prop_fdce_C_Q) 0.128 -0.369 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.281 -0.088 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 + SLICE_X11Y39 LUT1 (Prop_lut1_I0_O) 0.099 0.011 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O + net (fo=30, routed) 0.459 0.470 u_Axi_CDC/rFifo/buffers_0_reg[3] + SLICE_X14Y43 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17767,31 +8460,31 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.047 -0.261 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y43 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C + clock pessimism -0.196 -0.457 + SLICE_X14Y43 FDCE (Remov_fdce_C_CLR) -0.067 -0.524 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.524 + arrival time 0.470 ------------------------------------------------------------------- - slack 1.381 + slack 0.994 -Slack (MET) : 1.381ns (arrival time - required time) +Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17803,15 +8496,15 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17822,31 +8515,31 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.550 + arrival time 0.559 ------------------------------------------------------------------- - slack 1.381 + slack 1.109 -Slack (MET) : 1.381ns (arrival time - required time) +Slack (MET) : 1.109ns (arrival time - required time) Source: pll_clk.u_rst_cpu/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -17858,15 +8551,15 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -17877,3280 +8570,291 @@ Slack (MET) : 1.381ns (arrival time - required time) PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 + required time 0.550 + arrival time 0.559 ------------------------------------------------------------------- - slack 1.381 + slack 1.109 - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.613ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 + required time 0.550 + arrival time 0.559 ------------------------------------------------------------------- - slack 0.613 + slack 1.109 -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 + required time 0.550 + arrival time 0.559 ------------------------------------------------------------------- - slack 0.613 + slack 1.109 -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 + required time 0.550 + arrival time 0.559 ------------------------------------------------------------------- - slack 0.613 + slack 1.109 -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 + required time 0.550 + arrival time 0.559 ------------------------------------------------------------------- - slack 0.629 + slack 1.109 -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) +Slack (MET) : 1.109ns (arrival time - required time) + Source: pll_clk.u_rst_cpu/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR + (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) + Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) + Data Path Delay: 1.027ns (logic 0.186ns (18.117%) route 0.841ns (81.883%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns + Clock Path Skew: 0.010ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.468ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 0.795 -0.468 pll_clk.u_rst_cpu/cpu_clk + SLICE_X5Y45 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X5Y45 FDCE (Prop_fdce_C_Q) 0.141 -0.327 r pll_clk.u_rst_cpu/delay_reg[1]/Q + net (fo=1, routed) 0.351 0.025 pll_clk.u_rst_cpu/cpu_resetn + SLICE_X8Y45 LUT1 (Prop_lut1_I0_O) 0.045 0.070 f pll_clk.u_rst_cpu/reset_i_1/O + net (fo=40, routed) 0.489 0.559 u_Axi_CDC/wFifo/p_0_in + SLICE_X13Y42 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r + (clock cpu_clk rise edge) 0.000 0.000 r K21 0.000 0.000 r clk (IN) net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/C - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/C - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.824ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/C - clock pessimism -0.192 -0.574 - SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.824 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/C - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0] - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/C - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/C - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/C - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 2.861ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 2.861ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.351ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 0.216 - arrival time 2.645 - ------------------------------------------------------------------- - slack 2.861 - -Slack (MET) : 2.861ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.351ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.216 - arrival time 2.645 - ------------------------------------------------------------------- - slack 2.861 - -Slack (MET) : 4.207ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.380ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C - clock pessimism 0.099 -0.281 - clock uncertainty 0.197 -0.085 - SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[0] - ------------------------------------------------------------------- - required time 0.243 - arrival time 3.964 - ------------------------------------------------------------------- - slack 4.207 - -Slack (MET) : 4.207ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.380ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - clock pessimism 0.099 -0.281 - clock uncertainty 0.197 -0.085 - SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[1] - ------------------------------------------------------------------- - required time 0.243 - arrival time 3.964 - ------------------------------------------------------------------- - slack 4.207 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 2.991ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 2.991ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.365ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 0.138 - arrival time 2.853 - ------------------------------------------------------------------- - slack 2.991 - -Slack (MET) : 2.991ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.365ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.138 - arrival time 2.853 - ------------------------------------------------------------------- - slack 2.991 + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X13Y42 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] + ------------------------------------------------------------------- + required time 0.550 + arrival time 0.559 + ------------------------------------------------------------------- + slack 1.109 @@ -21162,838 +8866,13 @@ From Clock: sys_clk To Clock: sys_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.479ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.761ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.524ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - clock pessimism -0.192 -0.534 - SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.626 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.524 - -Slack (MET) : 0.548ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.214 -0.556 - SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.648 - arrival time -0.101 - ------------------------------------------------------------------- - slack 0.548 - -Slack (MET) : 0.558ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.214 -0.553 - SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.620 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.650ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X16Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/C - clock pessimism -0.192 -0.531 - SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.598 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.650 - -Slack (MET) : 0.800ns (arrival time - required time) +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR @@ -22001,12 +8880,12 @@ Slack (MET) : 0.800ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22019,14 +8898,14 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22038,17 +8917,17 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.800ns (arrival time - required time) +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR @@ -22056,12 +8935,12 @@ Slack (MET) : 0.800ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22074,14 +8953,14 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22093,17 +8972,17 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.800ns (arrival time - required time) +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR @@ -22111,12 +8990,12 @@ Slack (MET) : 0.800ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22129,14 +9008,14 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22148,17 +9027,17 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.800ns (arrival time - required time) +Slack (MET) : 0.761ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR @@ -22166,12 +9045,12 @@ Slack (MET) : 0.800ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) + Data Path Delay: 0.731ns (logic 0.246ns (33.644%) route 0.485ns (66.356%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22184,14 +9063,14 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.199 0.236 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X10Y42 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22203,17 +9082,347 @@ Slack (MET) : 0.800ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X10Y42 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 + required time 0.525 + arrival time 0.236 ------------------------------------------------------------------- - slack 0.800 + slack 0.761 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[0] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.808ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.729ns (logic 0.246ns (33.767%) route 0.483ns (66.233%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.221ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.196 0.234 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 + SLICE_X9Y43 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.221 -0.482 + SLICE_X9Y43 FDCE (Remov_fdce_C_CLR) -0.092 -0.574 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] + ------------------------------------------------------------------- + required time 0.574 + arrival time 0.234 + ------------------------------------------------------------------- + slack 0.808 + +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR @@ -22221,12 +9430,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22239,14 +9448,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22258,17 +9467,17 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR @@ -22276,12 +9485,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22294,14 +9503,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22313,127 +9522,17 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR @@ -22441,12 +9540,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22459,14 +9558,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22478,17 +9577,17 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.860ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR @@ -22496,12 +9595,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.805ns (logic 0.246ns (30.564%) route 0.559ns (69.436%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22514,14 +9613,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.272 0.310 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X11Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22533,17 +9632,72 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C + clock pessimism -0.196 -0.458 + SLICE_X11Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.550 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.550 + arrival time 0.310 ------------------------------------------------------------------- - slack 0.805 + slack 0.860 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.871ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] + ------------------------------------------------------------------- + required time 0.572 + arrival time 0.299 + ------------------------------------------------------------------- + slack 0.871 + +Slack (MET) : 0.871ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR @@ -22551,12 +9705,12 @@ Slack (MET) : 0.805ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.794ns (logic 0.246ns (30.972%) route 0.548ns (69.028%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22569,14 +9723,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.262 0.299 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X9Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22588,30 +9742,30 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C + clock pessimism -0.218 -0.480 + SLICE_X9Y41 FDCE (Remov_fdce_C_CLR) -0.092 -0.572 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.572 + arrival time 0.299 ------------------------------------------------------------------- - slack 0.805 + slack 0.871 -Slack (MET) : 0.805ns (arrival time - required time) +Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22624,14 +9778,14 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22643,30 +9797,30 @@ Slack (MET) : 0.805ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 + required time 0.571 + arrival time 0.301 ------------------------------------------------------------------- - slack 0.805 + slack 0.872 -Slack (MET) : 0.859ns (arrival time - required time) +Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22679,14 +9833,14 @@ Slack (MET) : 0.859ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22698,30 +9852,30 @@ Slack (MET) : 0.859ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 + required time 0.571 + arrival time 0.301 ------------------------------------------------------------------- - slack 0.859 + slack 0.872 -Slack (MET) : 0.859ns (arrival time - required time) +Slack (MET) : 0.872ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR + Destination: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) + Data Path Delay: 0.796ns (logic 0.246ns (30.897%) route 0.550ns (69.103%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -22734,14 +9888,14 @@ Slack (MET) : 0.859ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.264 0.301 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y45 FDCE f u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22753,139 +9907,29 @@ Slack (MET) : 0.859ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y45 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2] ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 + required time 0.571 + arrival time 0.301 ------------------------------------------------------------------- - slack 0.859 + slack 0.872 -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.890ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) + Data Path Delay: 0.864ns (logic 0.186ns (21.517%) route 0.678ns (78.483%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 1.001ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns + Clock Path Skew: 0.041ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.380ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22899,14 +9943,14 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.372 0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22918,29 +9962,29 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.546 - SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] + net (fo=35652, routed) 0.928 -0.380 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0]/C + clock pessimism -0.192 -0.572 + SLICE_X112Y66 FDCE (Remov_fdce_C_CLR) -0.067 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/busy_sync_reg[0] ------------------------------------------------------------------- - required time 0.638 - arrival time 0.363 + required time 0.639 + arrival time 0.251 ------------------------------------------------------------------- - slack 1.001 + slack 0.890 -Slack (MET) : 1.001ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.914ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns + Data Path Delay: 0.786ns (logic 0.249ns (31.687%) route 0.537ns (68.313%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.377ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -22954,14 +9998,14 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.371 0.179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -22973,17 +10017,182 @@ Slack (MET) : 1.001ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.546 - SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] + net (fo=35652, routed) 0.931 -0.377 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X125Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253]/C + clock pessimism -0.192 -0.569 + SLICE_X125Y65 FDCE (Remov_fdce_C_CLR) -0.165 -0.734 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[253] ------------------------------------------------------------------- - required time 0.638 - arrival time 0.363 + required time 0.734 + arrival time 0.179 ------------------------------------------------------------------- - slack 1.001 + slack 0.914 -Slack (MET) : 1.086ns (arrival time - required time) +Slack (MET) : 0.918ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 1.021ns (logic 0.246ns (24.092%) route 0.775ns (75.908%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.195ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): -0.037ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.489 0.526 u_Axi_CDC/wFifo/buffers_0_reg[3] + SLICE_X11Y53 FDCE f u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.972 -0.336 u_Axi_CDC/wFifo/sys_clk + SLICE_X11Y53 FDCE r u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg/C + clock pessimism 0.037 -0.299 + SLICE_X11Y53 FDCE (Remov_fdce_C_CLR) -0.092 -0.391 u_Axi_CDC/wFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.391 + arrival time 0.526 + ------------------------------------------------------------------- + slack 0.918 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_addressGen_rValid_reg + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[0]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[0] + ------------------------------------------------------------------- + required time 0.571 + arrival time 0.357 + ------------------------------------------------------------------- + slack 0.928 + +Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR @@ -22991,12 +10200,12 @@ Slack (MET) : 1.086ns (arrival time - required time) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.001ns (logic 0.227ns (22.676%) route 0.774ns (77.324%)) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.007ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -23009,14 +10218,14 @@ Slack (MET) : 1.086ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.491 0.460 u_Axi_CDC/awFifo/buffers_1_reg - SLICE_X15Y64 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23028,305 +10237,30 @@ Slack (MET) : 1.086ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y64 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.534 - SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] ------------------------------------------------------------------- - required time 0.626 - arrival time 0.460 + required time 0.571 + arrival time 0.357 ------------------------------------------------------------------- - slack 1.086 + slack 0.928 -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.207ns (arrival time - required time) +Slack (MET) : 0.928ns (arrival time - required time) Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) + Data Path Delay: 0.852ns (logic 0.246ns (28.889%) route 0.606ns (71.111%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns + Clock Path Skew: 0.016ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.261ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.218ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -23339,14 +10273,14 @@ Slack (MET) : 1.207ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.319 0.357 u_Axi_CDC/awFifo/buffers_1_reg + SLICE_X9Y44 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23358,29 +10292,29 @@ Slack (MET) : 1.207ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] + net (fo=35652, routed) 1.047 -0.261 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y44 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[2]/C + clock pessimism -0.218 -0.479 + SLICE_X9Y44 FDCE (Remov_fdce_C_CLR) -0.092 -0.571 u_Axi_CDC/awFifo/popCC_popPtr_reg[2] ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 + required time 0.571 + arrival time 0.357 ------------------------------------------------------------------- - slack 1.207 + slack 0.928 -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.932ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23394,14 +10328,14 @@ Slack (MET) : 1.207ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X112Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23413,29 +10347,29 @@ Slack (MET) : 1.207ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] + net (fo=35652, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X112Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10]/C + clock pessimism -0.192 -0.581 + SLICE_X112Y75 FDCE (Remov_fdce_C_CLR) -0.140 -0.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[10] ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 + required time 0.721 + arrival time 0.210 ------------------------------------------------------------------- - slack 1.207 + slack 0.932 -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23449,14 +10383,14 @@ Slack (MET) : 1.207ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23468,249 +10402,29 @@ Slack (MET) : 1.207ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.256ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.546 - SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[0] ------------------------------------------------------------------- required time 0.638 - arrival time 0.618 + arrival time 0.297 ------------------------------------------------------------------- - slack 1.256 + slack 0.935 -Slack (MET) : 1.256ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%)) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23724,14 +10438,14 @@ Slack (MET) : 1.256ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23743,29 +10457,29 @@ Slack (MET) : 1.256ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.546 - SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[1] ------------------------------------------------------------------- required time 0.638 - arrival time 0.618 + arrival time 0.297 ------------------------------------------------------------------- - slack 1.256 + slack 0.935 -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23779,14 +10493,14 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23798,29 +10512,29 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[0] + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2] ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 + required time 0.638 + arrival time 0.297 ------------------------------------------------------------------- - slack 1.359 + slack 0.935 -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.935ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23834,14 +10548,14 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X112Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23853,29 +10567,29 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[1] + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3]/C + clock pessimism -0.192 -0.571 + SLICE_X112Y65 FDCE (Remov_fdce_C_CLR) -0.067 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[3] ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 + required time 0.638 + arrival time 0.297 ------------------------------------------------------------------- - slack 1.359 + slack 0.935 -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns Clock Pessimism Removal (CPR): 0.192ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -23889,14 +10603,14 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -23908,15 +10622,1005 @@ Slack (MET) : 1.359ns (arrival time - required time) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[2] + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X127Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217]/C + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[217] ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 + required time 0.735 + arrival time 0.208 ------------------------------------------------------------------- - slack 1.359 + slack 0.944 + +Slack (MET) : 0.944ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.815ns (logic 0.249ns (30.565%) route 0.566ns (69.435%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.400 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X127Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X127Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223]/C + clock pessimism -0.192 -0.570 + SLICE_X127Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[223] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.208 + ------------------------------------------------------------------- + slack 0.944 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[233] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[234] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[236] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[237] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.948ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.819ns (logic 0.249ns (30.402%) route 0.570ns (69.598%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.036ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.378ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.404 0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X126Y66 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.930 -0.378 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X126Y66 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239]/C + clock pessimism -0.192 -0.570 + SLICE_X126Y66 FDCE (Remov_fdce_C_CLR) -0.165 -0.735 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[239] + ------------------------------------------------------------------- + required time 0.735 + arrival time 0.213 + ------------------------------------------------------------------- + slack 0.948 + +Slack (MET) : 0.952ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.822ns (logic 0.249ns (30.308%) route 0.573ns (69.692%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.035ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.407 0.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X125Y67 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X125Y67 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37]/C + clock pessimism -0.192 -0.571 + SLICE_X125Y67 FDCE (Remov_fdce_C_CLR) -0.165 -0.736 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[37] + ------------------------------------------------------------------- + required time 0.736 + arrival time 0.215 + ------------------------------------------------------------------- + slack 0.952 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.955ns (arrival time - required time) + Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.925ns (logic 0.246ns (26.589%) route 0.679ns (73.411%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.037ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.262ns + Source Clock Delay (SCD): -0.495ns + Clock Pessimism Removal (CPR): 0.196ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.768 -0.495 u_Axi_CDC/awFifo/bufferCC_12/sys_clk + SLICE_X8Y43 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y43 FDCE (Prop_fdce_C_Q) 0.148 -0.347 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q + net (fo=1, routed) 0.286 -0.060 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 + SLICE_X8Y43 LUT1 (Prop_lut1_I0_O) 0.098 0.038 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O + net (fo=43, routed) 0.393 0.430 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X12Y41 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.046 -0.262 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C + clock pessimism -0.196 -0.458 + SLICE_X12Y41 FDCE (Remov_fdce_C_CLR) -0.067 -0.525 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] + ------------------------------------------------------------------- + required time 0.525 + arrival time 0.430 + ------------------------------------------------------------------- + slack 0.955 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.817ns (logic 0.249ns (30.489%) route 0.568ns (69.511%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.025ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.389ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.402 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X113Y75 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5]/C + clock pessimism -0.192 -0.581 + SLICE_X113Y75 FDCE (Remov_fdce_C_CLR) -0.165 -0.746 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r_reg[5] + ------------------------------------------------------------------- + required time 0.746 + arrival time 0.210 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.932 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X131Y64 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90]/C + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[90] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.957ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.830ns (logic 0.249ns (29.992%) route 0.581ns (70.008%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.038ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.376ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.415 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X131Y64 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.932 -0.376 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X131Y64 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93]/C + clock pessimism -0.192 -0.568 + SLICE_X131Y64 FDCE (Remov_fdce_C_CLR) -0.165 -0.733 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/z_r_reg[93] + ------------------------------------------------------------------- + required time 0.733 + arrival time 0.224 + ------------------------------------------------------------------- + slack 0.957 + +Slack (MET) : 0.960ns (arrival time - required time) + Source: pll_clk.u_rst_sys/delay_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.910ns (logic 0.186ns (20.429%) route 0.724ns (79.571%)) + Logic Levels: 1 (LUT1=1) + Clock Path Skew: 0.042ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.379ns + Source Clock Delay (SCD): -0.613ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.649 -0.613 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X106Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.472 r pll_clk.u_rst_sys/delay_reg[1]/Q + net (fo=125, routed) 0.306 -0.166 pll_clk.u_rst_sys/Q[0] + SLICE_X110Y58 LUT1 (Prop_lut1_I0_O) 0.045 -0.121 f pll_clk.u_rst_sys/rdb_addr[11]_i_3/O + net (fo=5108, routed) 0.419 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/p_0_in + SLICE_X113Y65 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.929 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X113Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2]/C + clock pessimism -0.192 -0.571 + SLICE_X113Y65 FDCE (Remov_fdce_C_CLR) -0.092 -0.663 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_sync_reg[2] + ------------------------------------------------------------------- + required time 0.663 + arrival time 0.297 + ------------------------------------------------------------------- + slack 0.960 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[1] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[2] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[3] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[4] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 + +Slack (MET) : 0.961ns (arrival time - required time) + Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: **async_default** + Path Type: Removal (Min at Fast Process Corner) + Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) + Data Path Delay: 0.827ns (logic 0.249ns (30.107%) route 0.578ns (69.893%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: 0.031ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.383ns + Source Clock Delay (SCD): -0.606ns + Clock Pessimism Removal (CPR): 0.192ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.656 -0.606 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/sys_clk + SLICE_X112Y65 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X112Y65 FDCE (Prop_fdce_C_Q) 0.148 -0.458 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/srst_cnt_reg[2]/Q + net (fo=6, routed) 0.166 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/srst_cnt_reg[2] + SLICE_X112Y66 LUT5 (Prop_lut5_I3_O) 0.101 -0.192 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O + net (fo=24670, routed) 0.412 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul_n_0 + SLICE_X122Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sys_clk + SLICE_X122Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5]/C + clock pessimism -0.192 -0.575 + SLICE_X122Y70 FDCE (Remov_fdce_C_CLR) -0.165 -0.740 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dec_ba_reg[5] + ------------------------------------------------------------------- + required time 0.740 + arrival time 0.221 + ------------------------------------------------------------------- + slack 0.961 @@ -23935,17 +11639,17 @@ Min Delay 59 Endpoints Min Delay Paths -------------------------------------------------------------------------------------- Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.686ns (logic 0.418ns (60.951%) route 0.268ns (39.049%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns + Data Path Delay: 0.735ns (logic 0.467ns (63.560%) route 0.268ns (36.440%)) + Logic Levels: 1 (LUT5=1) + Clock Path Skew: -0.384ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.110ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -23964,12 +11668,14 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C + net (fo=35652, routed) 1.718 -2.110 u_snix_axil_cdma_mux_8ch/sys_clk + SLICE_X49Y58 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.268 -1.332 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X49Y58 FDRE (Prop_fdre_C_Q) 0.367 -1.743 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q + net (fo=3, routed) 0.268 -1.476 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 + SLICE_X49Y56 LUT5 (Prop_lut5_I0_O) 0.100 -1.376 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O + net (fo=1, routed) 0.000 -1.376 u_cpu/u_csr/interrupt[1] + SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -23980,9 +11686,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.847 -2.495 u_cpu/u_csr/cpu_clk + SLICE_X49Y56 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C @@ -23991,11 +11697,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.622ns (logic 0.367ns (58.974%) route 0.255ns (41.026%)) + Data Path Delay: 0.555ns (logic 0.418ns (75.283%) route 0.137ns (24.717%)) Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24014,12 +11720,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=2, routed) 0.255 -1.321 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=2, routed) 0.137 -1.275 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24030,9 +11736,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C @@ -24041,11 +11747,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.623ns (logic 0.367ns (58.905%) route 0.256ns (41.095%)) + Data Path Delay: 0.559ns (logic 0.418ns (74.744%) route 0.141ns (25.256%)) Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24064,12 +11770,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.256 -1.320 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.141 -1.271 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24080,322 +11786,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.720ns (logic 0.337ns (46.825%) route 0.383ns (53.175%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.383 -1.299 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.743ns (logic 0.367ns (49.384%) route 0.376ns (50.616%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.376 -1.275 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.842ns (logic 0.418ns (49.650%) route 0.424ns (50.350%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.424 -1.176 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.843ns (logic 0.337ns (39.996%) route 0.506ns (60.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.506 -1.176 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.782ns (logic 0.367ns (46.956%) route 0.415ns (53.044%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.415 -1.162 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.630ns (logic 0.367ns (58.287%) route 0.263ns (41.713%)) - Logic Levels: 0 - Clock Path Skew: -0.564ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.316ns - Source Clock Delay (SCD): -1.752ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.263 -1.122 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.632ns (logic 0.367ns (58.089%) route 0.265ns (41.911%)) + Data Path Delay: 0.644ns (logic 0.367ns (56.976%) route 0.277ns (43.024%)) Logic Levels: 0 Clock Path Skew: -0.377ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.129ns - Source Clock Delay (SCD): -1.752ns + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24414,12 +11820,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.265 -1.120 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.277 -1.188 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24430,59 +11836,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.922ns (logic 0.367ns (39.803%) route 0.555ns (60.197%)) - Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.555 -1.095 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C @@ -24491,11 +11847,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.888ns (logic 0.337ns (37.964%) route 0.551ns (62.036%)) + Data Path Delay: 0.656ns (logic 0.385ns (58.677%) route 0.271ns (41.323%)) Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.943ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24514,12 +11870,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.337 -1.606 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.551 -1.056 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.385 -1.446 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=4, routed) 0.271 -1.175 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24530,61 +11886,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.005 -2.337 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.075ns (logic 0.518ns (48.184%) route 0.557ns (51.816%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.382ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.498ns - Source Clock Delay (SCD): -2.115ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 -2.115 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X56Y62 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X56Y62 FDRE (Prop_fdre_C_Q) 0.418 -1.697 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q - net (fo=3, routed) 0.557 -1.140 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 - SLICE_X57Y58 LUT5 (Prop_lut5_I3_O) 0.100 -1.040 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O - net (fo=1, routed) 0.000 -1.040 u_cpu/u_csr/interrupt[1] - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.844 -2.498 u_cpu/u_csr/cpu_clk - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C @@ -24593,11 +11897,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.742ns (logic 0.367ns (49.468%) route 0.375ns (50.532%)) + Data Path Delay: 0.673ns (logic 0.418ns (62.094%) route 0.255ns (37.906%)) Logic Levels: 0 - Clock Path Skew: -0.377ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.129ns - Source Clock Delay (SCD): -1.752ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24616,12 +11920,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.375 -1.010 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.255 -1.159 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24632,22 +11936,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.025ns (logic 0.337ns (32.867%) route 0.688ns (67.133%)) + Data Path Delay: 0.675ns (logic 0.418ns (61.898%) route 0.257ns (38.102%)) Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24666,12 +11970,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + net (fo=35652, routed) 1.998 -1.831 u_Axi_CDC/rFifo/sys_clk + SLICE_X12Y44 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.337 -1.680 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.688 -0.992 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + SLICE_X12Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.257 -1.155 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24682,59 +11986,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.073ns (logic 0.367ns (34.191%) route 0.706ns (65.809%)) - Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.706 -0.944 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X13Y44 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C @@ -24743,11 +11997,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.147ns (logic 0.367ns (31.992%) route 0.780ns (68.008%)) + Data Path Delay: 0.686ns (logic 0.418ns (60.908%) route 0.268ns (39.092%)) Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24766,12 +12020,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.780 -0.871 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.268 -1.145 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24782,9 +12036,109 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.698ns (logic 0.385ns (55.120%) route 0.313ns (44.880%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.834ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk + SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.385 -1.449 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.313 -1.135 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.715ns (logic 0.418ns (58.464%) route 0.297ns (41.536%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.834ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk + SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.416 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.297 -1.119 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C @@ -24793,11 +12147,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.043ns (logic 0.337ns (32.302%) route 0.706ns (67.698%)) + Data Path Delay: 0.760ns (logic 0.385ns (50.673%) route 0.375ns (49.327%)) Logic Levels: 0 - Clock Path Skew: -0.564ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.316ns - Source Clock Delay (SCD): -1.752ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24816,12 +12170,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.415 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.706 -0.708 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.385 -1.447 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.375 -1.072 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24832,22 +12186,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf - Source: u_matmul_axi_slave/done_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.754ns (logic 0.418ns (23.829%) route 1.336ns (76.171%)) + Data Path Delay: 0.798ns (logic 0.367ns (46.017%) route 0.431ns (53.983%)) Logic Levels: 0 - Clock Path Skew: -0.104ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.228ns - Source Clock Delay (SCD): -2.123ns + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.832ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -24866,12 +12220,12 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 -2.123 u_matmul_axi_slave/sys_clk - SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.418 -1.705 r u_matmul_axi_slave/done_reg/Q - net (fo=12, routed) 1.336 -0.369 u_cpu/u_csr/interrupt[2] - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.431 -1.034 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24882,9 +12236,309 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.114 -2.228 u_cpu/u_csr/cpu_clk - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.815ns (logic 0.385ns (47.225%) route 0.430ns (52.775%)) + Logic Levels: 0 + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.385 -1.447 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.430 -1.016 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.828ns (logic 0.418ns (50.501%) route 0.410ns (49.499%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.834ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.995 -1.834 u_Axi_CDC/bFifo/sys_clk + SLICE_X8Y40 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X8Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.416 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.410 -1.006 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.826ns (logic 0.418ns (50.576%) route 0.408ns (49.424%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.408 -1.005 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.890ns (logic 0.367ns (41.256%) route 0.523ns (58.744%)) + Logic Levels: 0 + Clock Path Skew: -0.377ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/awFifo/sys_clk + SLICE_X9Y45 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y45 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.523 -0.942 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.133 -2.209 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y45 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.950ns (logic 0.418ns (44.008%) route 0.532ns (55.992%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/wFifo/sys_clk + SLICE_X10Y42 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y42 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.532 -0.882 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk + SLICE_X10Y41 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.959ns (logic 0.418ns (43.591%) route 0.541ns (56.409%)) + Logic Levels: 0 + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.997 -1.832 u_Axi_CDC/arFifo/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X16Y46 FDCE (Prop_fdce_C_Q) 0.418 -1.414 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.541 -0.873 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.131 -2.211 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk + SLICE_X16Y45 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf Source: u_confreg/int_out_or_q2_reg/C @@ -24893,10 +12547,110 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.063ns (logic 0.367ns (17.786%) route 1.696ns (82.214%)) + Data Path Delay: 1.250ns (logic 0.337ns (26.970%) route 0.913ns (73.030%)) Logic Levels: 0 - Clock Path Skew: -0.223ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.231ns + Clock Path Skew: -0.388ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.219ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.998 -1.831 u_confreg/sys_clk + SLICE_X9Y47 FDRE r u_confreg/int_out_or_q2_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y47 FDRE (Prop_fdre_C_Q) 0.337 -1.494 r u_confreg/int_out_or_q2_reg/Q + net (fo=1, routed) 0.913 -0.581 u_cpu/u_csr/interrupt[0] + SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.123 -2.219 u_cpu/u_csr/cpu_clk + SLICE_X9Y33 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C + +Slack: inf + Source: u_matmul_axi_slave/done_reg/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_cpu/u_csr/csr_estat_reg[4]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.161ns (logic 0.367ns (16.979%) route 1.794ns (83.021%)) + Logic Levels: 0 + Clock Path Skew: -0.457ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.494ns + Source Clock Delay (SCD): -2.036ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.792 -2.036 u_matmul_axi_slave/sys_clk + SLICE_X41Y78 FDRE r u_matmul_axi_slave/done_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X41Y78 FDRE (Prop_fdre_C_Q) 0.367 -1.669 r u_matmul_axi_slave/done_reg/Q + net (fo=11, routed) 1.794 0.125 u_cpu/u_csr/interrupt[2] + SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.848 -2.494 u_cpu/u_csr/cpu_clk + SLICE_X47Y52 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.190ns (logic 1.062ns (48.490%) route 1.128ns (51.510%)) + Logic Levels: 0 + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.218ns Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE @@ -24916,12 +12670,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.821 -2.007 u_confreg/sys_clk - SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK + SLICE_X16Y54 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.367 -1.640 r u_confreg/int_out_or_q2_reg/Q - net (fo=1, routed) 1.696 0.056 u_cpu/u_csr/interrupt[0] - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D + SLICE_X16Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.945 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O + net (fo=1, routed) 1.128 0.183 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] + SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -24932,213 +12687,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.111 -2.231 u_cpu/u_csr/cpu_clk - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.149ns (logic 1.078ns (50.163%) route 1.071ns (49.837%)) - Logic Levels: 0 - Clock Path Skew: -0.371ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 1.071 0.127 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.153ns (logic 1.062ns (49.332%) route 1.091ns (50.668%)) - Logic Levels: 0 - Clock Path Skew: -0.376ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.398ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 1.091 0.131 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.944 -2.398 u_Axi_CDC/rFifo/cpu_clk - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.174ns (logic 1.056ns (48.570%) route 1.118ns (51.430%)) - Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 1.118 0.150 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.202ns (logic 1.078ns (48.964%) route 1.124ns (51.036%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.946 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 1.124 0.177 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.124 -2.218 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y34 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK @@ -25147,11 +12698,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.203ns (logic 1.083ns (49.171%) route 1.120ns (50.829%)) + Data Path Delay: 2.232ns (logic 1.083ns (48.530%) route 1.149ns (51.470%)) Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.216ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -25170,13 +12721,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 1.120 0.178 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.924 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O + net (fo=1, routed) 1.149 0.224 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25187,22 +12738,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.208ns (logic 1.083ns (49.047%) route 1.125ns (50.953%)) + Data Path Delay: 2.343ns (logic 1.056ns (45.069%) route 1.287ns (54.931%)) Logic Levels: 0 - Clock Path Skew: -0.370ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.395ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.220ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.228ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -25221,13 +12772,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 1.125 0.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.951 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O + net (fo=1, routed) 1.287 0.336 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25238,366 +12789,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.216ns (logic 1.078ns (48.649%) route 1.138ns (51.351%)) - Logic Levels: 0 - Clock Path Skew: -0.372ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 1.138 0.195 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.231ns (logic 1.056ns (47.336%) route 1.175ns (52.664%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 1.175 0.207 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.300ns (logic 1.056ns (45.907%) route 1.244ns (54.093%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.966 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 1.244 0.278 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.329ns (logic 1.084ns (46.543%) route 1.245ns (53.457%)) - Logic Levels: 0 - Clock Path Skew: -0.369ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 1.245 0.305 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.337ns (logic 1.059ns (45.323%) route 1.278ns (54.677%)) - Logic Levels: 0 - Clock Path Skew: -0.373ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.395ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 1.278 0.315 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.340ns (logic 1.059ns (45.262%) route 1.281ns (54.738%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.963 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 1.281 0.317 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.340ns (logic 1.056ns (45.123%) route 1.284ns (54.877%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 1.284 0.319 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.114 -2.228 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK @@ -25606,11 +12800,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.349ns (logic 1.084ns (46.148%) route 1.265ns (53.852%)) + Data Path Delay: 2.348ns (logic 1.084ns (46.168%) route 1.264ns (53.832%)) Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.220ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.228ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -25629,13 +12823,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK + net (fo=35652, routed) 1.821 -2.007 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK + SLICE_X18Y55 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 1.265 0.325 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D + SLICE_X18Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.923 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O + net (fo=1, routed) 1.264 0.341 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25646,22 +12840,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.114 -2.228 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.378ns (logic 1.083ns (45.550%) route 1.295ns (54.450%)) + Data Path Delay: 2.406ns (logic 1.084ns (45.052%) route 1.322ns (54.948%)) Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: -0.208ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.223ns + Source Clock Delay (SCD): -2.014ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -25680,13 +12874,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 1.295 0.355 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.930 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O + net (fo=1, routed) 1.322 0.392 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] + SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25697,22 +12891,22 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.119 -2.223 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.380ns (logic 1.062ns (44.630%) route 1.318ns (55.370%)) + Data Path Delay: 2.432ns (logic 1.056ns (43.427%) route 1.376ns (56.573%)) Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.013ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -25731,13 +12925,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + net (fo=35652, routed) 1.815 -2.013 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.960 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 1.318 0.357 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.957 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O + net (fo=1, routed) 1.376 0.418 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -25748,315 +12942,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.383ns (logic 1.062ns (44.564%) route 1.321ns (55.436%)) - Logic Levels: 0 - Clock Path Skew: -0.186ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 1.321 0.362 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.393ns (logic 1.062ns (44.383%) route 1.331ns (55.617%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 1.331 0.372 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.414ns (logic 1.083ns (44.858%) route 1.331ns (55.142%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 1.331 0.392 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.434ns (logic 1.062ns (43.637%) route 1.372ns (56.363%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 1.372 0.409 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.441ns (logic 1.078ns (44.167%) route 1.363ns (55.833%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 1.363 0.418 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.491ns (logic 1.083ns (43.479%) route 1.408ns (56.521%)) - Logic Levels: 0 - Clock Path Skew: -0.190ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 1.408 0.470 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK @@ -26065,11 +12953,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.529ns (logic 1.056ns (41.755%) route 1.473ns (58.245%)) + Data Path Delay: 2.459ns (logic 1.056ns (42.943%) route 1.403ns (57.057%)) Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.014ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26088,13 +12976,13 @@ Slack: inf -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 1.473 0.508 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.958 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O + net (fo=1, routed) 1.403 0.445 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -26105,213 +12993,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.538ns (logic 1.084ns (42.711%) route 1.454ns (57.289%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.937 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 1.454 0.517 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.565ns (logic 1.078ns (42.030%) route 1.487ns (57.970%)) - Logic Levels: 0 - Clock Path Skew: -0.190ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 1.487 0.544 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.570ns (logic 1.084ns (42.178%) route 1.486ns (57.822%)) - Logic Levels: 0 - Clock Path Skew: -0.189ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 1.486 0.548 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.131ns (logic 0.386ns (34.129%) route 0.745ns (65.871%)) - Logic Levels: 0 - Clock Path Skew: 0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.745 0.552 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK @@ -26319,12 +13003,114 @@ Slack: inf Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.175ns (logic 0.386ns (32.837%) route 0.789ns (67.163%)) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.501ns (logic 1.059ns (42.335%) route 1.442ns (57.665%)) Logic Levels: 0 - Clock Path Skew: 0.314ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.263ns - Source Clock Delay (SCD): -0.577ns + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.013ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.815 -2.013 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.954 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O + net (fo=1, routed) 1.442 0.488 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.513ns (logic 1.059ns (42.141%) route 1.454ns (57.859%)) + Logic Levels: 0 + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.222ns + Source Clock Delay (SCD): -2.012ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.953 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O + net (fo=1, routed) 1.454 0.501 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.120 -2.222 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.094ns (logic 0.394ns (36.013%) route 0.700ns (63.987%)) + Logic Levels: 0 + Clock Path Skew: 0.299ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.272ns + Source Clock Delay (SCD): -0.571ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26343,13 +13129,13 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.789 0.598 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O + net (fo=1, routed) 0.700 0.523 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -26360,9 +13146,978 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.036 -0.272 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.095ns (logic 0.390ns (35.601%) route 0.705ns (64.399%)) + Logic Levels: 0 + Clock Path Skew: 0.293ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O + net (fo=1, routed) 0.705 0.524 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.549ns (logic 1.083ns (42.493%) route 1.466ns (57.507%)) + Logic Levels: 0 + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.222ns + Source Clock Delay (SCD): -2.012ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.929 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O + net (fo=1, routed) 1.466 0.536 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.120 -2.222 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.116ns (logic 0.390ns (34.953%) route 0.726ns (65.047%)) + Logic Levels: 0 + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.275ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O + net (fo=1, routed) 0.726 0.543 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.033 -0.275 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.116ns (logic 0.390ns (34.933%) route 0.726ns (65.067%)) + Logic Levels: 0 + Clock Path Skew: 0.295ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.276ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O + net (fo=1, routed) 0.726 0.545 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] + SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.032 -0.276 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.565ns (logic 1.056ns (41.172%) route 1.509ns (58.828%)) + Logic Levels: 0 + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.225ns + Source Clock Delay (SCD): -2.014ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.958 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O + net (fo=1, routed) 1.509 0.551 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.117 -2.225 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.567ns (logic 1.059ns (41.247%) route 1.508ns (58.753%)) + Logic Levels: 0 + Clock Path Skew: -0.209ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.224ns + Source Clock Delay (SCD): -2.014ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.814 -2.014 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.955 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O + net (fo=1, routed) 1.508 0.553 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.118 -2.224 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.129ns (logic 0.388ns (34.373%) route 0.741ns (65.627%)) + Logic Levels: 0 + Clock Path Skew: 0.300ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.272ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.184 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O + net (fo=1, routed) 0.741 0.556 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.036 -0.272 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y30 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.135ns (logic 0.394ns (34.715%) route 0.741ns (65.285%)) + Logic Levels: 0 + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.274ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.177 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O + net (fo=1, routed) 0.741 0.564 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.148ns (logic 0.386ns (33.633%) route 0.762ns (66.367%)) + Logic Levels: 0 + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.274ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.386 -0.185 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O + net (fo=1, routed) 0.762 0.576 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.034 -0.274 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y28 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.151ns (logic 0.390ns (33.893%) route 0.761ns (66.107%)) + Logic Levels: 0 + Clock Path Skew: 0.299ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.273ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.182 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O + net (fo=1, routed) 0.761 0.578 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.151ns (logic 0.394ns (34.237%) route 0.757ns (65.763%)) + Logic Levels: 0 + Clock Path Skew: 0.295ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK + SLICE_X16Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.178 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O + net (fo=1, routed) 0.757 0.578 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.153ns (logic 0.388ns (33.638%) route 0.765ns (66.362%)) + Logic Levels: 0 + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O + net (fo=1, routed) 0.765 0.582 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] + SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X15Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.182ns (logic 0.388ns (32.831%) route 0.794ns (67.169%)) + Logic Levels: 0 + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O + net (fo=1, routed) 0.794 0.610 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] + SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X14Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.224ns (logic 0.390ns (31.861%) route 0.834ns (68.139%)) + Logic Levels: 0 + Clock Path Skew: 0.293ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.390 -0.181 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O + net (fo=1, routed) 0.834 0.653 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.266ns (logic 0.388ns (30.652%) route 0.878ns (69.348%)) + Logic Levels: 0 + Clock Path Skew: 0.293ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.388 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O + net (fo=1, routed) 0.878 0.694 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y25 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.273ns (logic 0.492ns (38.660%) route 0.781ns (61.340%)) + Logic Levels: 0 + Clock Path Skew: 0.297ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.275ns + Source Clock Delay (SCD): -0.572ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.080 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O + net (fo=1, routed) 0.781 0.700 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.033 -0.275 u_Axi_CDC/rFifo/cpu_clk + SLICE_X18Y27 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 2.727ns (logic 1.056ns (38.721%) route 1.671ns (61.279%)) + Logic Levels: 0 + Clock Path Skew: -0.210ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.223ns + Source Clock Delay (SCD): -2.012ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.816 -2.012 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK + SLICE_X14Y63 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X14Y63 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.956 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O + net (fo=1, routed) 1.671 0.715 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 2.119 -2.223 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y21 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.291ns (logic 0.492ns (38.120%) route 0.799ns (61.880%)) + Logic Levels: 0 + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.277ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK + SLICE_X18Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.079 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O + net (fo=1, routed) 0.799 0.719 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.031 -0.277 u_Axi_CDC/rFifo/cpu_clk + SLICE_X16Y26 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.292ns (logic 0.492ns (38.091%) route 0.800ns (61.909%)) + Logic Levels: 0 + Clock Path Skew: 0.298ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.273ns + Source Clock Delay (SCD): -0.571ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.691 -0.571 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK + SLICE_X16Y65 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) + 0.492 -0.079 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O + net (fo=1, routed) 0.800 0.720 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.035 -0.273 u_Axi_CDC/rFifo/cpu_clk + SLICE_X19Y29 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C Slack: inf Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK @@ -26371,11 +14126,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.178ns (logic 0.394ns (33.456%) route 0.784ns (66.544%)) + Data Path Delay: 1.331ns (logic 0.394ns (29.608%) route 0.937ns (70.392%)) Logic Levels: 0 - Clock Path Skew: 0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.577ns + Clock Path Skew: 0.294ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.278ns + Source Clock Delay (SCD): -0.572ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -26394,13 +14149,13 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK + net (fo=35652, routed) 0.690 -0.572 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK + SLICE_X18Y66 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.784 0.600 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D + SLICE_X18Y66 RAMD32 (Prop_ramd32_CLK_O) + 0.394 -0.178 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O + net (fo=1, routed) 0.937 0.758 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] + SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D ------------------------------------------------------------------- ------------------- (clock cpu_clk rise edge) 0.000 0.000 r @@ -26411,60 +14166,9 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.182ns (logic 0.386ns (32.666%) route 0.796ns (67.334%)) - Logic Levels: 0 - Clock Path Skew: 0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.263ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.796 0.601 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.030 -0.278 u_Axi_CDC/rFifo/cpu_clk + SLICE_X17Y24 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C @@ -26476,512 +14180,12 @@ From Clock: cpu_clk To Clock: sys_clk Max Delay 0 Endpoints -Min Delay 162 Endpoints +Min Delay 154 Endpoints -------------------------------------------------------------------------------------- Min Delay Paths -------------------------------------------------------------------------------------- -Slack: inf - Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.597ns (logic 0.337ns (56.456%) route 0.260ns (43.544%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.337 -1.671 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.260 -1.411 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.617ns (logic 0.337ns (54.608%) route 0.280ns (45.392%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.337 -1.677 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.280 -1.397 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.634ns (logic 0.367ns (57.910%) route 0.267ns (42.090%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.267 -1.381 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.654ns (logic 0.385ns (58.892%) route 0.269ns (41.108%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.385 -1.633 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.269 -1.365 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.621ns (logic 0.337ns (54.306%) route 0.284ns (45.694%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.946ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.337 -1.609 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.284 -1.326 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.736ns (logic 0.367ns (49.854%) route 0.369ns (50.146%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.369 -1.272 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.740ns (logic 0.367ns (49.584%) route 0.373ns (50.416%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.373 -1.268 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.792ns (logic 0.367ns (46.311%) route 0.425ns (53.689%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.425 -1.222 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.817ns (logic 0.418ns (51.164%) route 0.399ns (48.836%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.399 -1.201 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] - SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.833ns (logic 0.418ns (50.157%) route 0.415ns (49.843%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.415 -1.185 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) @@ -26989,11 +14193,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.793ns (logic 0.367ns (46.283%) route 0.426ns (53.717%)) + Data Path Delay: 0.503ns (logic 0.367ns (72.947%) route 0.136ns (27.053%)) Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.946ns + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27011,13 +14215,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.426 -1.153 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q + net (fo=1, routed) 0.136 -1.328 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27029,21 +14233,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C + net (fo=35652, routed) 2.133 -2.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.632ns (logic 0.337ns (53.354%) route 0.295ns (46.646%)) + Data Path Delay: 0.609ns (logic 0.337ns (55.331%) route 0.272ns (44.669%)) Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.213ns + Source Clock Delay (SCD): -1.833ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27061,13 +14265,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk + SLICE_X11Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.413 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 0.295 -1.118 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + SLICE_X11Y40 FDCE (Prop_fdce_C_Q) 0.337 -1.496 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q + net (fo=2, routed) 0.272 -1.224 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27079,58 +14283,8 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.641ns (logic 0.367ns (57.215%) route 0.274ns (42.785%)) - Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.274 -1.108 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C @@ -27139,11 +14293,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.928ns (logic 0.367ns (39.555%) route 0.561ns (60.445%)) + Data Path Delay: 0.622ns (logic 0.367ns (58.987%) route 0.255ns (41.013%)) Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.334ns - Source Clock Delay (SCD): -1.946ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27161,13 +14315,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.561 -1.018 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q + net (fo=1, routed) 0.255 -1.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27179,21 +14333,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%)) + Data Path Delay: 0.642ns (logic 0.337ns (52.522%) route 0.305ns (47.478%)) Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27211,13 +14365,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 0.403 -0.979 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.337 -1.494 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.305 -1.189 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27229,8 +14383,358 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X16Y46 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.684ns (logic 0.418ns (61.129%) route 0.266ns (38.871%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.213ns + Source Clock Delay (SCD): -1.833ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.415 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q + net (fo=2, routed) 0.266 -1.149 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.754ns (logic 0.367ns (48.681%) route 0.387ns (51.319%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.387 -1.078 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.782ns (logic 0.385ns (49.223%) route 0.397ns (50.777%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.385 -1.446 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=4, routed) 0.397 -1.049 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.811ns (logic 0.418ns (51.570%) route 0.393ns (48.430%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.393 -1.020 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.845ns (logic 0.418ns (49.462%) route 0.427ns (50.538%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.213ns + Source Clock Delay (SCD): -1.833ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.996 -1.833 u_Axi_CDC/bFifo/cpu_clk + SLICE_X10Y40 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y40 FDCE (Prop_fdce_C_Q) 0.418 -1.415 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q + net (fo=2, routed) 0.427 -0.988 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.129 -2.213 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk + SLICE_X9Y40 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.844ns (logic 0.418ns (49.514%) route 0.426ns (50.486%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.211ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/awFifo/cpu_clk + SLICE_X10Y44 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X10Y44 FDCE (Prop_fdce_C_Q) 0.418 -1.413 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.426 -0.986 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.131 -2.211 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y43 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C + +Slack: inf + Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 0.868ns (logic 0.337ns (38.842%) route 0.531ns (61.158%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.209ns + Source Clock Delay (SCD): -1.831ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.337 -1.494 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q + net (fo=1, routed) 0.531 -0.963 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.133 -2.209 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y43 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C Slack: inf Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C @@ -27239,11 +14743,11 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.000ns (logic 0.367ns (36.693%) route 0.633ns (63.307%)) + Data Path Delay: 0.899ns (logic 0.367ns (40.831%) route 0.532ns (59.169%)) Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.334ns - Source Clock Delay (SCD): -1.946ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27261,13 +14765,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/rFifo/cpu_clk + SLICE_X13Y43 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.633 -0.946 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D + SLICE_X13Y43 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q + net (fo=1, routed) 0.532 -0.932 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27279,21 +14783,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk + SLICE_X12Y42 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.892ns (logic 0.367ns (41.149%) route 0.525ns (58.851%)) + Data Path Delay: 0.899ns (logic 0.367ns (40.814%) route 0.532ns (59.186%)) Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27311,13 +14815,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.525 -0.858 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q + net (fo=2, routed) 0.532 -0.931 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27329,21 +14833,121 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.019ns (logic 0.367ns (36.005%) route 0.652ns (63.995%)) + Logic Levels: 0 + Clock Path Skew: -0.380ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.212ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q + net (fo=3, routed) 0.652 -0.812 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.130 -2.212 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X9Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.035ns (logic 0.337ns (32.545%) route 0.698ns (67.455%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.337 -1.495 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q + net (fo=5, routed) 0.698 -0.796 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X12Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%)) + Data Path Delay: 1.240ns (logic 1.078ns (86.936%) route 0.162ns (13.064%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27361,14 +14965,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.953 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 0.159 -0.794 u_Axi_CDC/awFifo/_zz_ram_port10[1] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D + SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.929 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC/O + net (fo=1, routed) 0.162 -0.767 u_Axi_CDC/awFifo/_zz_ram_port10[34] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27380,365 +14984,8 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.218ns (logic 1.059ns (86.968%) route 0.159ns (13.032%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.950 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/O - net (fo=1, routed) 0.159 -0.792 u_Axi_CDC/awFifo/_zz_ram_port10[5] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.399ns - Source Clock Delay (SCD): -2.011ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.949 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O - net (fo=1, routed) 0.159 -0.791 u_Axi_CDC/awFifo/_zz_ram_port10[45] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.947 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 0.159 -0.789 u_Axi_CDC/awFifo/_zz_ram_port10[3] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 0.162 -0.778 u_Axi_CDC/arFifo/_zz_ram_port10__1[6] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.934 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.162 -0.772 u_Axi_CDC/arFifo/_zz_ram_port10__1[48] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.245ns (logic 1.083ns (86.954%) route 0.162ns (13.046%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.015ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.932 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O - net (fo=1, routed) 0.162 -0.770 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.015ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.931 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.162 -0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[34]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK @@ -27747,11 +14994,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.329ns (logic 1.078ns (81.137%) route 0.251ns (18.863%)) + Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27769,14 +15016,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.946 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 0.251 -0.696 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -1.030 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O + net (fo=1, routed) 0.281 -0.749 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27788,21 +15035,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.340ns (logic 1.062ns (79.263%) route 0.278ns (20.737%)) + Data Path Delay: 1.363ns (logic 1.084ns (79.504%) route 0.279ns (20.496%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27820,14 +15067,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 0.278 -0.684 u_Axi_CDC/arFifo/_zz_ram_port10__1[3] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.024 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O + net (fo=1, routed) 0.279 -0.745 u_Axi_CDC/arFifo/_zz_ram_port10__1[6] + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27839,21 +15086,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.338ns (logic 1.059ns (79.147%) route 0.279ns (20.853%)) + Data Path Delay: 1.106ns (logic 0.367ns (33.193%) route 0.739ns (66.807%)) Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.379ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.831ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -27871,14 +15118,13 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.998 -1.831 u_Axi_CDC/arFifo/cpu_clk + SLICE_X17Y47 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.962 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/O - net (fo=1, routed) 0.279 -0.683 u_Axi_CDC/awFifo/_zz_ram_port10[53] - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D + SLICE_X17Y47 FDCE (Prop_fdce_C_Q) 0.367 -1.464 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.739 -0.725 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -27890,8 +15136,8 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/C + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk + SLICE_X16Y47 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK @@ -27900,313 +15146,7 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.334ns (logic 1.056ns (79.142%) route 0.278ns (20.858%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.278 -0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.340ns (logic 1.062ns (79.249%) route 0.278ns (20.751%)) - Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.412ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.956 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/O - net (fo=1, routed) 0.278 -0.678 u_Axi_CDC/arFifo/_zz_ram_port10__1[51] - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.337ns (logic 1.056ns (79.009%) route 0.281ns (20.991%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.013ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.957 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.281 -0.677 u_Axi_CDC/awFifo/_zz_ram_port10[37] - SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.360ns (logic 1.078ns (79.282%) route 0.282ns (20.718%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/O - net (fo=1, routed) 0.282 -0.662 u_Axi_CDC/awFifo/_zz_ram_port10[52] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.398ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.926 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.281 -0.645 u_Axi_CDC/awFifo/_zz_ram_port10[2] - SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.944 -2.398 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.411ns (logic 1.062ns (75.266%) route 0.349ns (24.734%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.402ns - Source Clock Delay (SCD): -2.013ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.951 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/O - net (fo=1, routed) 0.349 -0.602 u_Axi_CDC/awFifo/_zz_ram_port10[39] - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.432ns (logic 1.083ns (75.645%) route 0.349ns (24.355%)) + Data Path Delay: 1.301ns (logic 1.056ns (81.139%) route 0.245ns (18.861%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -2.396ns @@ -28228,14 +15168,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X20Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 0.349 -0.577 u_Axi_CDC/awFifo/_zz_ram_port10[8] - SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D + SLICE_X20Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.952 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O + net (fo=1, routed) 0.245 -0.707 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28247,21 +15187,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/arFifo/sys_clk + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) + Data Path Delay: 1.301ns (logic 1.056ns (81.139%) route 0.245ns (18.861%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28279,14 +15219,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.395 -0.570 u_Axi_CDC/awFifo/_zz_ram_port10[49] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D + SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.951 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O + net (fo=1, routed) 0.245 -0.706 u_Axi_CDC/awFifo/_zz_ram_port10[31] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28298,21 +15238,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.454ns (logic 1.062ns (73.041%) route 0.392ns (26.959%)) + Data Path Delay: 1.328ns (logic 1.056ns (79.500%) route 0.272ns (20.500%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.412ns + Source Clock Delay (SCD): -2.025ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28330,14 +15270,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.803 -2.025 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK + SLICE_X40Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/O - net (fo=1, routed) 0.392 -0.567 u_Axi_CDC/awFifo/_zz_ram_port10[51] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D + SLICE_X40Y57 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.969 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.272 -0.697 u_Axi_CDC/awFifo/_zz_ram_port10[13] + SLICE_X38Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28349,21 +15289,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/C + net (fo=35652, routed) 1.930 -2.412 u_Axi_CDC/awFifo/sys_clk + SLICE_X38Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[13]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.454ns (logic 1.059ns (72.851%) route 0.395ns (27.149%)) + Data Path Delay: 1.331ns (logic 1.083ns (81.357%) route 0.248ns (18.643%)) Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.018ns + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28381,14 +15321,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.395 -0.565 u_Axi_CDC/awFifo/_zz_ram_port10[35] - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D + SLICE_X18Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.248 -0.676 u_Axi_CDC/awFifo/_zz_ram_port10[32] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28400,8 +15340,160 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.157ns (logic 0.367ns (31.718%) route 0.790ns (68.282%)) + Logic Levels: 0 + Clock Path Skew: -0.378ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.210ns + Source Clock Delay (SCD): -1.832ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.997 -1.832 u_Axi_CDC/wFifo/cpu_clk + SLICE_X13Y42 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X13Y42 FDCE (Prop_fdce_C_Q) 0.367 -1.465 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q + net (fo=2, routed) 0.790 -0.675 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 2.132 -2.210 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk + SLICE_X11Y41 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.333ns (logic 1.062ns (79.680%) route 0.271ns (20.320%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.945 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB_D1/O + net (fo=1, routed) 0.271 -0.674 u_Axi_CDC/arFifo/_zz_ram_port10__1[33] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[33]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.338ns (logic 1.062ns (79.382%) route 0.276ns (20.618%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK + SLICE_X20Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.946 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMB_D1/O + net (fo=1, routed) 0.276 -0.670 u_Axi_CDC/arFifo/_zz_ram_port10__1[39] + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/arFifo/sys_clk + SLICE_X21Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[39]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK @@ -28410,11 +15502,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.453ns (logic 1.056ns (72.668%) route 0.397ns (27.332%)) + Data Path Delay: 1.344ns (logic 1.056ns (78.598%) route 0.288ns (21.402%)) Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.017ns + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28432,14 +15524,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O - net (fo=1, routed) 0.397 -0.564 u_Axi_CDC/arFifo/_zz_ram_port10__1[31] - SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -0.951 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O + net (fo=1, routed) 0.288 -0.664 u_Axi_CDC/arFifo/_zz_ram_port10__1[31] + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28451,21 +15543,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.457ns (logic 1.062ns (72.904%) route 0.395ns (27.096%)) + Data Path Delay: 1.348ns (logic 1.062ns (78.762%) route 0.286ns (21.238%)) Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.018ns + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28483,14 +15575,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.956 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.395 -0.562 u_Axi_CDC/awFifo/_zz_ram_port10[33] - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.944 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB_D1/O + net (fo=1, routed) 0.286 -0.658 u_Axi_CDC/arFifo/_zz_ram_port10__1[45] + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28502,161 +15594,8 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.482ns (logic 1.083ns (73.069%) route 0.399ns (26.931%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 0.399 -0.542 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.482ns (logic 1.083ns (73.083%) route 0.399ns (26.917%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.938 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/O - net (fo=1, routed) 0.399 -0.539 u_Axi_CDC/awFifo/_zz_ram_port10[50] - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.479ns (logic 1.078ns (72.907%) route 0.401ns (27.093%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.939 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.401 -0.539 u_Axi_CDC/arFifo/_zz_ram_port10__1[34] - SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/arFifo/sys_clk - SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/C + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[45]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK @@ -28665,11 +15604,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%)) + Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) Logic Levels: 0 Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28687,14 +15626,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 0.437 -0.532 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.052 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O + net (fo=1, routed) 0.395 -0.657 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28706,174 +15645,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.437 -0.526 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.496ns (logic 1.059ns (70.775%) route 0.437ns (29.225%)) - Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.412ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.959 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/O - net (fo=1, routed) 0.437 -0.522 u_Axi_CDC/arFifo/_zz_ram_port10__1[53] - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.497ns (logic 1.059ns (70.746%) route 0.438ns (29.254%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.958 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.438 -0.520 u_Axi_CDC/arFifo/_zz_ram_port10__1[41] - SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk - SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.059ns (70.929%) route 0.434ns (29.071%)) + Data Path Delay: 1.359ns (logic 1.078ns (79.297%) route 0.281ns (20.703%)) Logic Levels: 0 Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.399ns - Source Clock Delay (SCD): -2.011ns + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28891,14 +15677,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/CLK ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.952 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/O - net (fo=1, routed) 0.434 -0.518 u_Axi_CDC/awFifo/_zz_ram_port10[47] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.930 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC/O + net (fo=1, routed) 0.281 -0.649 u_Axi_CDC/awFifo/_zz_ram_port10[46] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28910,8 +15696,263 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/C + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[46]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.359ns (logic 1.083ns (79.691%) route 0.276ns (20.309%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.924 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMB/O + net (fo=1, routed) 0.276 -0.648 u_Axi_CDC/arFifo/_zz_ram_port10__1[32] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[32]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB/O + net (fo=1, routed) 0.281 -0.644 u_Axi_CDC/awFifo/_zz_ram_port10[44] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[44]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.364ns (logic 1.084ns (79.446%) route 0.280ns (20.554%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK + SLICE_X18Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y57 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA/O + net (fo=1, routed) 0.280 -0.644 u_Axi_CDC/awFifo/_zz_ram_port10[48] + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/awFifo/sys_clk + SLICE_X19Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[48]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.475ns (logic 1.059ns (71.806%) route 0.416ns (28.194%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.049 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC_D1/O + net (fo=1, routed) 0.416 -0.633 u_Axi_CDC/arFifo/_zz_ram_port10__1[11] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[11]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.375ns (logic 1.084ns (78.853%) route 0.291ns (21.147%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.923 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA/O + net (fo=1, routed) 0.291 -0.633 u_Axi_CDC/arFifo/_zz_ram_port10__1[30] + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X14Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[30]/C Slack: inf Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK @@ -28920,11 +15961,11 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.511ns (logic 1.083ns (71.691%) route 0.428ns (28.309%)) + Data Path Delay: 1.484ns (logic 1.083ns (72.970%) route 0.401ns (27.030%)) Logic Levels: 0 - Clock Path Skew: -0.382ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.024ns + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28942,14 +15983,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.428 -0.514 u_Axi_CDC/arFifo/_zz_ram_port10__1[2] - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/O + net (fo=1, routed) 0.401 -0.624 u_Axi_CDC/arFifo/_zz_ram_port10__1[2] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -28961,21 +16002,21 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/C Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.504ns (logic 1.059ns (70.415%) route 0.445ns (29.585%)) + Data Path Delay: 1.484ns (logic 1.083ns (72.970%) route 0.401ns (27.030%)) Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.402ns - Source Clock Delay (SCD): -2.013ns + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns Clock Pessimism Removal (CPR): -0.000ns Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -28993,14 +16034,14 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.954 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.445 -0.509 u_Axi_CDC/awFifo/_zz_ram_port10[41] - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O + net (fo=1, routed) 0.401 -0.624 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -29012,8 +16053,671 @@ Slack: inf -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/C + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.389ns (logic 1.084ns (78.063%) route 0.305ns (21.937%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.922 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.305 -0.618 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.463ns (logic 1.084ns (74.106%) route 0.379ns (25.894%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -0.924 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O + net (fo=1, routed) 0.379 -0.546 u_Axi_CDC/awFifo/_zz_ram_port10[42] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.480ns (logic 1.078ns (72.829%) route 0.402ns (27.171%)) + Logic Levels: 0 + Clock Path Skew: -0.382ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.405ns + Source Clock Delay (SCD): -2.022ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.806 -2.022 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK + SLICE_X36Y56 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X36Y56 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.944 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC/O + net (fo=1, routed) 0.402 -0.542 u_Axi_CDC/awFifo/_zz_ram_port10[40] + SLICE_X35Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.937 -2.405 u_Axi_CDC/awFifo/sys_clk + SLICE_X35Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[40]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.571ns (logic 1.059ns (67.419%) route 0.512ns (32.581%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -1.049 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC_D1/O + net (fo=1, routed) 0.512 -0.537 u_Axi_CDC/arFifo/_zz_ram_port10__1[5] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[5]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.576ns (logic 1.062ns (67.383%) route 0.514ns (32.617%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.046 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O + net (fo=1, routed) 0.514 -0.532 u_Axi_CDC/arFifo/_zz_ram_port10__1[3] + SLICE_X45Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y56 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.482ns (logic 1.078ns (72.759%) route 0.404ns (27.241%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.078 -0.928 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O + net (fo=1, routed) 0.404 -0.525 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y50 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.488ns (logic 1.059ns (71.167%) route 0.429ns (28.833%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.395ns + Source Clock Delay (SCD): -2.007ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.821 -2.007 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK + SLICE_X18Y53 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X18Y53 RAMD32 (Prop_ramd32_CLK_O) + 1.059 -0.948 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC_D1/O + net (fo=1, routed) 0.429 -0.519 u_Axi_CDC/arFifo/_zz_ram_port10__1[35] + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.947 -2.395 u_Axi_CDC/arFifo/sys_clk + SLICE_X17Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[35]/C + +Slack: inf + Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.493ns (logic 1.062ns (71.119%) route 0.431ns (28.881%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.396ns + Source Clock Delay (SCD): -2.008ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK + SLICE_X20Y55 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X20Y55 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -0.946 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O + net (fo=1, routed) 0.431 -0.515 u_Axi_CDC/awFifo/_zz_ram_port10[45] + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk + SLICE_X21Y56 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.492ns (logic 1.083ns (72.568%) route 0.409ns (27.432%)) + Logic Levels: 0 + Clock Path Skew: -0.387ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.394ns + Source Clock Delay (SCD): -2.006ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.822 -2.006 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK + SLICE_X16Y50 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X16Y50 RAMD32 (Prop_ramd32_CLK_O) + 1.083 -0.923 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O + net (fo=1, routed) 0.409 -0.514 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.948 -2.394 u_Axi_CDC/arFifo/sys_clk + SLICE_X15Y51 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.597ns (logic 1.062ns (66.517%) route 0.535ns (33.483%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK + SLICE_X44Y52 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y52 RAMD32 (Prop_ramd32_CLK_O) + 1.062 -1.046 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB_D1/O + net (fo=1, routed) 0.535 -0.512 u_Axi_CDC/arFifo/_zz_ram_port10__1[9] + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[9]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.601ns (logic 1.056ns (65.965%) route 0.545ns (34.035%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.496ns + Source Clock Delay (SCD): -2.109ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.719 -2.109 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.056 -1.053 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA_D1/O + net (fo=1, routed) 0.545 -0.508 u_Axi_CDC/arFifo/_zz_ram_port10__1[13] + SLICE_X43Y55 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.846 -2.496 u_Axi_CDC/arFifo/sys_clk + SLICE_X43Y55 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[13]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.601ns (logic 1.084ns (67.687%) route 0.517ns (32.313%)) + Logic Levels: 0 + Clock Path Skew: -0.385ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.109ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.719 -2.109 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK + SLICE_X44Y54 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y54 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.025 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O + net (fo=1, routed) 0.517 -0.508 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X45Y54 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C + +Slack: inf + Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK + (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) + Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Slow Process Corner) + Data Path Delay: 1.601ns (logic 1.084ns (67.690%) route 0.517ns (32.310%)) + Logic Levels: 0 + Clock Path Skew: -0.386ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -2.495ns + Source Clock Delay (SCD): -2.108ns + Clock Pessimism Removal (CPR): -0.000ns + Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Discrete Jitter (DJ): 0.130ns + Phase Error (PE): 0.120ns + Timing Exception: Asynchronous Clock Groups + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock cpu_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) + -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 + net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll + BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O + net (fo=6484, routed) 1.720 -2.108 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK + SLICE_X44Y51 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK + ------------------------------------------------------------------- ------------------- + SLICE_X44Y51 RAMD32 (Prop_ramd32_CLK_O) + 1.084 -1.024 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O + net (fo=1, routed) 0.517 -0.507 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.847 -2.495 u_Axi_CDC/arFifo/sys_clk + SLICE_X44Y53 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C @@ -29056,7 +16760,7 @@ Slack: inf PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll - BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O + BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN ------------------------------------------------------------------- ------------------- @@ -29103,20 +16807,20 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.794 -0.468 video_clk_OBUF + net (fo=35652, routed) 0.794 -0.468 video_clk_OBUF H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O net (fo=0) 0.000 0.766 video_clk H22 r video_clk (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[0]_lopt_replica/C + Source: u_confreg/led_data_reg[15]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[0] + Destination: leds[15] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.665ns (logic 1.416ns (53.147%) route 1.249ns (46.853%)) + Data Path Delay: 2.765ns (logic 1.404ns (50.799%) route 1.360ns (49.201%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29134,24 +16838,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[0]_lopt_replica/Q - net (fo=1, routed) 1.249 0.852 lopt - B24 OBUF (Prop_obuf_I_O) 1.275 2.128 r leds_OBUF[0]_inst/O - net (fo=0) 0.000 2.128 leds[0] - B24 r leds[0] (OUT) + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[15]_lopt_replica/Q + net (fo=1, routed) 1.360 0.960 lopt_6 + B20 OBUF (Prop_obuf_I_O) 1.263 2.223 r leds_OBUF[15]_inst/O + net (fo=0) 0.000 2.223 leds[15] + B20 r leds[15] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[1]_lopt_replica/C + Source: u_confreg/led_data_reg[12]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[1] + Destination: leds[12] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.771ns (logic 1.383ns (49.914%) route 1.388ns (50.086%)) + Data Path Delay: 2.814ns (logic 1.384ns (49.180%) route 1.430ns (50.820%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29169,14 +16873,14 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y85 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[1]_lopt_replica/Q - net (fo=1, routed) 1.388 0.992 lopt_7 - E21 OBUF (Prop_obuf_I_O) 1.242 2.234 r leds_OBUF[1]_inst/O - net (fo=0) 0.000 2.234 leds[1] - E21 r leds[1] (OUT) + SLICE_X0Y85 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[12]_lopt_replica/Q + net (fo=1, routed) 1.430 1.030 lopt_3 + D20 OBUF (Prop_obuf_I_O) 1.243 2.273 r leds_OBUF[12]_inst/O + net (fo=0) 0.000 2.273 leds[12] + D20 r leds[12] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29186,7 +16890,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.806ns (logic 1.454ns (51.806%) route 1.352ns (48.194%)) + Data Path Delay: 2.837ns (logic 1.414ns (49.822%) route 1.424ns (50.178%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29204,86 +16908,16 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C + net (fo=35652, routed) 0.718 -0.544 u_confreg/sys_clk + SLICE_X0Y81 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[7]_lopt_replica/Q - net (fo=1, routed) 1.352 0.943 lopt_13 - B22 OBUF (Prop_obuf_I_O) 1.326 2.268 r leds_OBUF[7]_inst/O - net (fo=0) 0.000 2.268 leds[7] + SLICE_X0Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r u_confreg/led_data_reg[7]_lopt_replica/Q + net (fo=1, routed) 1.424 1.020 lopt_13 + B22 OBUF (Prop_obuf_I_O) 1.273 2.293 r leds_OBUF[7]_inst/O + net (fo=0) 0.000 2.293 leds[7] B22 r leds[7] (OUT) ------------------------------------------------------------------- ------------------- -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[7] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.807ns (logic 1.362ns (48.520%) route 1.445ns (51.480%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q - net (fo=1, routed) 1.445 1.050 dpy1_OBUF[7] - G17 OBUF (Prop_obuf_I_O) 1.221 2.271 r dpy1_OBUF[7]_inst/O - net (fo=0) 0.000 2.271 dpy1[7] - G17 r dpy1[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[13]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[13] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.809ns (logic 1.412ns (50.266%) route 1.397ns (49.734%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[13]_lopt_replica/Q - net (fo=1, routed) 1.397 1.002 lopt_4 - A22 OBUF (Prop_obuf_I_O) 1.271 2.273 r leds_OBUF[13]_inst/O - net (fo=0) 0.000 2.273 leds[13] - A22 r leds[13] (OUT) - ------------------------------------------------------------------- ------------------- - Slack: inf Source: u_confreg/led_data_reg[10]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -29291,7 +16925,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.819ns (logic 1.389ns (49.262%) route 1.430ns (50.738%)) + Data Path Delay: 2.845ns (logic 1.389ns (48.821%) route 1.456ns (51.179%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29309,24 +16943,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C + net (fo=35652, routed) 0.718 -0.544 u_confreg/sys_clk + SLICE_X1Y81 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[10]_lopt_replica/Q - net (fo=1, routed) 1.430 1.030 lopt_1 - D21 OBUF (Prop_obuf_I_O) 1.248 2.278 r leds_OBUF[10]_inst/O - net (fo=0) 0.000 2.278 leds[10] + SLICE_X1Y81 FDRE (Prop_fdre_C_Q) 0.141 -0.403 r u_confreg/led_data_reg[10]_lopt_replica/Q + net (fo=1, routed) 1.456 1.052 lopt_1 + D21 OBUF (Prop_obuf_I_O) 1.248 2.300 r leds_OBUF[10]_inst/O + net (fo=0) 0.000 2.300 leds[10] D21 r leds[10] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[14]_lopt_replica/C + Source: u_confreg/led_data_reg[0]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[14] + Destination: leds[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.815ns (logic 1.404ns (49.886%) route 1.411ns (50.114%)) + Data Path Delay: 2.867ns (logic 1.416ns (49.395%) route 1.451ns (50.605%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29344,25 +16978,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[14]_lopt_replica/Q - net (fo=1, routed) 1.411 1.014 lopt_5 - A20 OBUF (Prop_obuf_I_O) 1.263 2.278 r leds_OBUF[14]_inst/O - net (fo=0) 0.000 2.278 leds[14] - A20 r leds[14] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[0]_lopt_replica/Q + net (fo=1, routed) 1.451 1.053 lopt + B24 OBUF (Prop_obuf_I_O) 1.275 2.328 r leds_OBUF[0]_inst/O + net (fo=0) 0.000 2.328 leds[0] + B24 r leds[0] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + Source: u_confreg/led_data_reg[4]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_TX + Destination: leds[4] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.818ns (logic 1.033ns (36.656%) route 1.785ns (63.344%)) - Logic Levels: 2 (LUT3=1 OBUFT=1) + Data Path Delay: 2.934ns (logic 1.404ns (47.847%) route 1.530ns (52.153%)) + Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns @@ -29379,17 +17013,119 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C + net (fo=35652, routed) 0.715 -0.547 u_confreg/sys_clk + SLICE_X0Y78 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y60 FDRE (Prop_fdre_C_Q) 0.164 -0.375 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q - net (fo=2, routed) 0.232 -0.143 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en - SLICE_X3Y60 LUT3 (Prop_lut3_I0_O) 0.045 -0.098 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O - net (fo=1, routed) 1.553 1.455 UART_TX_IOBUF_inst/T - H18 OBUFT (TriStatD_obuft_T_O) - 0.824 2.279 r UART_TX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 2.279 UART_TX - H18 r UART_TX (INOUT) + SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r u_confreg/led_data_reg[4]_lopt_replica/Q + net (fo=1, routed) 1.530 1.124 lopt_10 + C22 OBUF (Prop_obuf_I_O) 1.263 2.386 r leds_OBUF[4]_inst/O + net (fo=0) 0.000 2.386 leds[4] + C22 r leds[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[6]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.974ns (logic 1.383ns (46.512%) route 1.591ns (53.488%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.715 -0.547 u_confreg/sys_clk + SLICE_X0Y78 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y78 FDRE (Prop_fdre_C_Q) 0.141 -0.406 r u_confreg/led_data_reg[6]_lopt_replica/Q + net (fo=1, routed) 1.591 1.185 lopt_12 + E20 OBUF (Prop_obuf_I_O) 1.242 2.427 r leds_OBUF[6]_inst/O + net (fo=0) 0.000 2.427 leds[6] + E20 r leds[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[11]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[11] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.976ns (logic 1.408ns (47.324%) route 1.568ns (52.676%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[11]_lopt_replica/Q + net (fo=1, routed) 1.568 1.169 lopt_2 + A18 OBUF (Prop_obuf_I_O) 1.267 2.436 r leds_OBUF[11]_inst/O + net (fo=0) 0.000 2.436 leds[11] + A18 r leds[11] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.051ns (logic 1.388ns (45.475%) route 1.664ns (54.525%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q + net (fo=1, routed) 1.664 1.267 dpy0_OBUF[5] + C19 OBUF (Prop_obuf_I_O) 1.247 2.514 r dpy0_OBUF[5]_inst/O + net (fo=0) 0.000 2.514 dpy0[5] + C19 r dpy0[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29399,7 +17135,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.902ns (logic 0.965ns (33.253%) route 1.937ns (66.747%)) + Data Path Delay: 2.985ns (logic 0.965ns (32.328%) route 2.020ns (67.672%)) Logic Levels: 1 (OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29417,25 +17153,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X9Y67 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C + net (fo=35652, routed) 0.795 -0.468 u_axi_uart_controller/uart0/regs/sys_clk + SLICE_X3Y39 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X9Y67 FDSE (Prop_fdse_C_Q) 0.141 -0.432 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q - net (fo=28, routed) 1.937 1.505 UART_RX_IOBUF_inst/T + SLICE_X3Y39 FDSE (Prop_fdse_C_Q) 0.141 -0.327 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q + net (fo=28, routed) 2.020 1.693 UART_RX_IOBUF_inst/T J20 OBUFT (TriStatD_obuft_T_O) - 0.824 2.329 r UART_RX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 2.329 UART_RX + 0.824 2.517 r UART_RX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 2.517 UART_RX J20 r UART_RX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[0] + Source: u_confreg/led_data_reg[5]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[5] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.872ns (logic 1.407ns (48.983%) route 1.465ns (51.017%)) + Data Path Delay: 3.109ns (logic 1.435ns (46.158%) route 1.674ns (53.842%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29453,25 +17189,25 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q - net (fo=1, routed) 1.465 1.070 dpy1_OBUF[0] - A17 OBUF (Prop_obuf_I_O) 1.266 2.336 r dpy1_OBUF[0]_inst/O - net (fo=0) 0.000 2.336 dpy1[0] - A17 r dpy1[0] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[5]_lopt_replica/Q + net (fo=1, routed) 1.674 1.263 lopt_11 + C21 OBUF (Prop_obuf_I_O) 1.307 2.570 r leds_OBUF[5]_inst/O + net (fo=0) 0.000 2.570 leds[5] + C21 r leds[5] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[5] + Source: u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/C + (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: UART_TX (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.877ns (logic 1.376ns (47.814%) route 1.502ns (52.186%)) - Logic Levels: 1 (OBUF=1) + Data Path Delay: 3.056ns (logic 1.416ns (46.332%) route 1.640ns (53.668%)) + Logic Levels: 2 (LUT4=1 OBUFT=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns Discrete Jitter (DJ): 0.122ns @@ -29488,24 +17224,26 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + net (fo=35652, routed) 0.796 -0.467 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X0Y41 FDSE r u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q - net (fo=1, routed) 1.502 1.106 dpy1_OBUF[5] - G16 OBUF (Prop_obuf_I_O) 1.235 2.341 r dpy1_OBUF[5]_inst/O - net (fo=0) 0.000 2.341 dpy1[5] - G16 r dpy1[5] (OUT) + SLICE_X0Y41 FDSE (Prop_fdse_C_Q) 0.141 -0.326 r u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg/Q + net (fo=5, routed) 0.136 -0.189 u_axi_uart_controller/uart0/regs/transmitter/stx_o_tmp_reg_0 + SLICE_X0Y40 LUT4 (Prop_lut4_I1_O) 0.045 -0.144 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O + net (fo=1, routed) 1.504 1.360 UART_TX_IOBUF_inst/I + H18 OBUFT (Prop_obuft_I_O) 1.230 2.590 r UART_TX_IOBUF_inst/OBUFT/O + net (fo=1, unset) 0.000 2.590 UART_TX + H18 r UART_TX (INOUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[7] + Destination: dpy0[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.946ns (logic 1.386ns (47.054%) route 1.560ns (52.946%)) + Data Path Delay: 3.150ns (logic 1.400ns (44.449%) route 1.750ns (55.551%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29523,24 +17261,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q - net (fo=1, routed) 1.560 1.096 dpy0_OBUF[7] - C17 OBUF (Prop_obuf_I_O) 1.245 2.341 r dpy0_OBUF[7]_inst/O - net (fo=0) 0.000 2.341 dpy0[7] - C17 r dpy0[7] (OUT) + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q + net (fo=1, routed) 1.750 1.353 dpy0_OBUF[2] + B21 OBUF (Prop_obuf_I_O) 1.259 2.612 r dpy0_OBUF[2]_inst/O + net (fo=0) 0.000 2.612 dpy0[2] + B21 r dpy0[2] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[6] + Destination: dpy0[0] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.958ns (logic 1.398ns (47.262%) route 1.560ns (52.738%)) + Data Path Delay: 3.168ns (logic 1.402ns (44.239%) route 1.767ns (55.761%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29558,14 +17296,119 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q - net (fo=1, routed) 1.560 1.096 dpy0_OBUF[6] - B17 OBUF (Prop_obuf_I_O) 1.257 2.353 r dpy0_OBUF[6]_inst/O - net (fo=0) 0.000 2.353 dpy0[6] - B17 r dpy0[6] (OUT) + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q + net (fo=1, routed) 1.767 1.370 dpy0_OBUF[0] + B19 OBUF (Prop_obuf_I_O) 1.261 2.631 r dpy0_OBUF[0]_inst/O + net (fo=0) 0.000 2.631 dpy0[0] + B19 r dpy0[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.170ns (logic 1.415ns (44.629%) route 1.755ns (55.371%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q + net (fo=1, routed) 1.755 1.359 dpy0_OBUF[3] + A19 OBUF (Prop_obuf_I_O) 1.274 2.632 r dpy0_OBUF[3]_inst/O + net (fo=0) 0.000 2.632 dpy0[3] + A19 r dpy0[3] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.175ns (logic 1.379ns (43.433%) route 1.796ns (56.567%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q + net (fo=1, routed) 1.796 1.398 dpy1_OBUF[6] + F15 OBUF (Prop_obuf_I_O) 1.238 2.636 r dpy1_OBUF[6]_inst/O + net (fo=0) 0.000 2.636 dpy1[6] + F15 r dpy1[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[3]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[3] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.180ns (logic 1.444ns (45.406%) route 1.736ns (54.594%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[3]_lopt_replica/Q + net (fo=1, routed) 1.736 1.324 lopt_9 + D23 OBUF (Prop_obuf_I_O) 1.316 2.640 r leds_OBUF[3]_inst/O + net (fo=0) 0.000 2.640 leds[3] + D23 r leds[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29575,7 +17418,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.927ns (logic 1.391ns (47.509%) route 1.537ns (52.491%)) + Data Path Delay: 3.210ns (logic 1.391ns (43.329%) route 1.819ns (56.671%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29593,13 +17436,13 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q - net (fo=1, routed) 1.537 1.141 dpy1_OBUF[1] - D16 OBUF (Prop_obuf_I_O) 1.250 2.391 r dpy1_OBUF[1]_inst/O - net (fo=0) 0.000 2.391 dpy1[1] + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q + net (fo=1, routed) 1.819 1.422 dpy1_OBUF[1] + D16 OBUF (Prop_obuf_I_O) 1.250 2.671 r dpy1_OBUF[1]_inst/O + net (fo=0) 0.000 2.671 dpy1[1] D16 r dpy1[1] (OUT) ------------------------------------------------------------------- ------------------- @@ -29610,7 +17453,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 2.966ns (logic 1.383ns (46.637%) route 1.583ns (53.363%)) + Data Path Delay: 3.257ns (logic 1.383ns (42.471%) route 1.874ns (57.529%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29628,24 +17471,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q - net (fo=1, routed) 1.583 1.188 dpy1_OBUF[4] - E16 OBUF (Prop_obuf_I_O) 1.242 2.430 r dpy1_OBUF[4]_inst/O - net (fo=0) 0.000 2.430 dpy1[4] + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q + net (fo=1, routed) 1.874 1.476 dpy1_OBUF[4] + E16 OBUF (Prop_obuf_I_O) 1.242 2.719 r dpy1_OBUF[4]_inst/O + net (fo=0) 0.000 2.719 dpy1[4] E16 r dpy1[4] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[3] + Destination: dpy1[3] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.046ns (logic 1.415ns (46.436%) route 1.632ns (53.564%)) + Data Path Delay: 3.258ns (logic 1.356ns (41.632%) route 1.902ns (58.368%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29663,119 +17506,14 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q - net (fo=1, routed) 1.632 1.168 dpy0_OBUF[3] - A19 OBUF (Prop_obuf_I_O) 1.274 2.441 r dpy0_OBUF[3]_inst/O - net (fo=0) 0.000 2.441 dpy0[3] - A19 r dpy0[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[12]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[12] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.006ns (logic 1.384ns (46.047%) route 1.622ns (53.953%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[12]_lopt_replica/Q - net (fo=1, routed) 1.622 1.223 lopt_3 - D20 OBUF (Prop_obuf_I_O) 1.243 2.467 r leds_OBUF[12]_inst/O - net (fo=0) 0.000 2.467 leds[12] - D20 r leds[12] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.083ns (logic 1.402ns (45.458%) route 1.682ns (54.542%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q - net (fo=1, routed) 1.682 1.218 dpy0_OBUF[0] - B19 OBUF (Prop_obuf_I_O) 1.261 2.478 r dpy0_OBUF[0]_inst/O - net (fo=0) 0.000 2.478 dpy0[0] - B19 r dpy0[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[6] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.165ns (logic 1.379ns (43.565%) route 1.786ns (56.435%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q - net (fo=1, routed) 1.786 1.391 dpy1_OBUF[6] - F15 OBUF (Prop_obuf_I_O) 1.238 2.629 r dpy1_OBUF[6]_inst/O - net (fo=0) 0.000 2.629 dpy1[6] - F15 r dpy1[6] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q + net (fo=1, routed) 1.902 1.504 dpy1_OBUF[3] + F17 OBUF (Prop_obuf_I_O) 1.215 2.719 r dpy1_OBUF[3]_inst/O + net (fo=0) 0.000 2.719 dpy1[3] + F17 r dpy1[3] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -29785,7 +17523,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.248ns (logic 1.387ns (42.702%) route 1.861ns (57.298%)) + Data Path Delay: 3.344ns (logic 1.387ns (41.472%) route 1.957ns (58.528%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29803,94 +17541,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q - net (fo=1, routed) 1.861 1.397 dpy0_OBUF[1] - D19 OBUF (Prop_obuf_I_O) 1.246 2.643 r dpy0_OBUF[1]_inst/O - net (fo=0) 0.000 2.643 dpy0[1] + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q + net (fo=1, routed) 1.957 1.561 dpy0_OBUF[1] + D19 OBUF (Prop_obuf_I_O) 1.246 2.807 r dpy0_OBUF[1]_inst/O + net (fo=0) 0.000 2.807 dpy0[1] D19 r dpy0[1] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.258ns (logic 1.388ns (42.591%) route 1.870ns (57.409%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q - net (fo=1, routed) 1.870 1.406 dpy0_OBUF[5] - C19 OBUF (Prop_obuf_I_O) 1.247 2.653 r dpy0_OBUF[5]_inst/O - net (fo=0) 0.000 2.653 dpy0[5] - C19 r dpy0[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.236ns (logic 1.383ns (42.747%) route 1.853ns (57.253%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q - net (fo=1, routed) 1.853 1.457 dpy1_OBUF[2] - E17 OBUF (Prop_obuf_I_O) 1.242 2.700 r dpy1_OBUF[2]_inst/O - net (fo=0) 0.000 2.700 dpy1[2] - E17 r dpy1[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[6]_lopt_replica/C + Source: u_confreg/led_data_reg[14]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[6] + Destination: leds[14] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.273ns (logic 1.423ns (43.486%) route 1.850ns (56.514%)) + Data Path Delay: 3.393ns (logic 1.404ns (41.392%) route 1.989ns (58.608%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29908,24 +17576,133 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[6]_lopt_replica/Q - net (fo=1, routed) 1.850 1.440 lopt_12 - E20 OBUF (Prop_obuf_I_O) 1.295 2.736 r leds_OBUF[6]_inst/O - net (fo=0) 0.000 2.736 leds[6] - E20 r leds[6] (OUT) + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[14]_lopt_replica/Q + net (fo=1, routed) 1.989 1.590 lopt_5 + A20 OBUF (Prop_obuf_I_O) 1.263 2.854 r leds_OBUF[14]_inst/O + net (fo=0) 0.000 2.854 leds[14] + A20 r leds[14] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[11]_lopt_replica/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[6] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.619ns (logic 1.398ns (38.631%) route 2.221ns (61.369%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q + net (fo=1, routed) 2.221 1.825 dpy0_OBUF[6] + B17 OBUF (Prop_obuf_I_O) 1.257 3.082 r dpy0_OBUF[6]_inst/O + net (fo=0) 0.000 3.082 dpy0[6] + B17 r dpy0[6] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.636ns (logic 1.407ns (38.697%) route 2.229ns (61.303%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q + net (fo=1, routed) 2.229 1.831 dpy1_OBUF[0] + A17 OBUF (Prop_obuf_I_O) 1.266 3.097 r dpy1_OBUF[0]_inst/O + net (fo=0) 0.000 3.097 dpy1[0] + A17 r dpy1[0] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[0]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[11] + Destination: video_vsync (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.362ns (logic 1.408ns (41.889%) route 1.954ns (58.111%)) + Data Path Delay: 3.669ns (logic 1.482ns (40.396%) route 2.187ns (59.604%)) + Logic Levels: 3 (LUT4=1 LUT6=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.716 -0.546 u_axi_dvi/sys_clk + SLICE_X1Y79 FDRE r u_axi_dvi/vdata_reg[0]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y79 FDRE (Prop_fdre_C_Q) 0.141 -0.405 r u_axi_dvi/vdata_reg[0]/Q + net (fo=13, routed) 0.170 -0.236 u_axi_dvi/vdata_reg_n_0_[0] + SLICE_X1Y79 LUT6 (Prop_lut6_I3_O) 0.045 -0.191 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O + net (fo=1, routed) 0.189 -0.001 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 + SLICE_X1Y80 LUT4 (Prop_lut4_I0_O) 0.045 0.044 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O + net (fo=1, routed) 1.828 1.872 video_vsync_OBUF + H24 OBUF (Prop_obuf_I_O) 1.251 3.123 r video_vsync_OBUF_inst/O + net (fo=0) 0.000 3.123 video_vsync + H24 r video_vsync (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[7] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.661ns (logic 1.386ns (37.869%) route 2.275ns (62.131%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29943,24 +17720,59 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y56 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[11]_lopt_replica/Q - net (fo=1, routed) 1.954 1.557 lopt_2 - A18 OBUF (Prop_obuf_I_O) 1.267 2.825 r leds_OBUF[11]_inst/O - net (fo=0) 0.000 2.825 leds[11] - A18 r leds[11] (OUT) + SLICE_X0Y56 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q + net (fo=1, routed) 2.275 1.878 dpy0_OBUF[7] + C17 OBUF (Prop_obuf_I_O) 1.245 3.124 r dpy0_OBUF[7]_inst/O + net (fo=0) 0.000 3.124 dpy0[7] + C17 r dpy0[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C + Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy0[4] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.691ns (logic 1.381ns (37.421%) route 2.309ns (62.579%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.725 -0.537 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y55 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y55 FDCE (Prop_fdce_C_Q) 0.141 -0.396 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q + net (fo=1, routed) 2.309 1.913 dpy0_OBUF[4] + E18 OBUF (Prop_obuf_I_O) 1.240 3.153 r dpy0_OBUF[4]_inst/O + net (fo=0) 0.000 3.153 dpy0[4] + E18 r dpy0[4] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Destination: video_de (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.419ns (logic 1.470ns (42.999%) route 1.949ns (57.001%)) + Data Path Delay: 3.778ns (logic 1.447ns (38.313%) route 2.330ns (61.687%)) Logic Levels: 2 (LUT6=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -29978,18 +17790,188 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C + net (fo=35652, routed) 0.713 -0.549 u_axi_dvi/sys_clk + SLICE_X0Y76 FDRE r u_axi_dvi/vdata_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.247 -0.161 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X14Y86 LUT6 (Prop_lut6_I3_O) 0.045 -0.116 r u_axi_dvi/video_de_OBUF_inst_i_1/O - net (fo=1, routed) 1.702 1.586 video_de_OBUF - G24 OBUF (Prop_obuf_I_O) 1.261 2.847 r video_de_OBUF_inst/O - net (fo=0) 0.000 2.847 video_de + SLICE_X0Y76 FDRE (Prop_fdre_C_Q) 0.141 -0.408 f u_axi_dvi/vdata_reg[11]/Q + net (fo=11, routed) 0.358 -0.050 u_axi_dvi/vdata_reg_n_0_[11] + SLICE_X1Y74 LUT6 (Prop_lut6_I1_O) 0.045 -0.005 r u_axi_dvi/video_de_OBUF_inst_i_1/O + net (fo=1, routed) 1.972 1.967 video_de_OBUF + G24 OBUF (Prop_obuf_I_O) 1.261 3.228 r video_de_OBUF_inst/O + net (fo=0) 0.000 3.228 video_de G24 r video_de (OUT) ------------------------------------------------------------------- ------------------- +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.808ns (logic 1.383ns (36.327%) route 2.425ns (63.673%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X0Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q + net (fo=1, routed) 2.425 2.027 dpy1_OBUF[2] + E17 OBUF (Prop_obuf_I_O) 1.242 3.270 r dpy1_OBUF[2]_inst/O + net (fo=0) 0.000 3.270 dpy1[2] + E17 r dpy1[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[2] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.856ns (logic 1.671ns (43.330%) route 2.185ns (56.670%)) + Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q + net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] + SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O + net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 + SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] + net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 + SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] + net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in + SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 1.722 2.019 video_red_OBUF[0] + E26 OBUF (Prop_obuf_I_O) 1.287 3.306 r video_red_OBUF[2]_inst/O + net (fo=0) 0.000 3.306 video_red[2] + E26 r video_red[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.955ns (logic 1.645ns (41.586%) route 2.310ns (58.414%)) + Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q + net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] + SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O + net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 + SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] + net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 + SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] + net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in + SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 1.847 2.144 video_red_OBUF[0] + F24 OBUF (Prop_obuf_I_O) 1.261 3.405 r video_red_OBUF[1]_inst/O + net (fo=0) 0.000 3.405 video_red[1] + F24 r video_red[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_axi_dvi/vdata_reg[2]/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: video_red[0] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 3.987ns (logic 1.617ns (40.568%) route 2.370ns (59.432%)) + Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X0Y74 FDRE r u_axi_dvi/vdata_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y74 FDRE (Prop_fdre_C_Q) 0.141 -0.409 r u_axi_dvi/vdata_reg[2]/Q + net (fo=12, routed) 0.241 -0.169 u_axi_dvi/vdata_reg_n_0_[2] + SLICE_X2Y73 LUT4 (Prop_lut4_I2_O) 0.047 -0.122 r u_axi_dvi/video_red_OBUF[2]_inst_i_53/O + net (fo=1, routed) 0.000 -0.122 u_axi_dvi/video_red_OBUF[2]_inst_i_53_n_0 + SLICE_X2Y73 CARRY4 (Prop_carry4_DI[1]_CO[3]) + 0.111 -0.011 r u_axi_dvi/video_red_OBUF[2]_inst_i_19/CO[3] + net (fo=1, routed) 0.000 -0.011 u_axi_dvi/video_red_OBUF[2]_inst_i_19_n_0 + SLICE_X2Y74 CARRY4 (Prop_carry4_CI_CO[3]) + 0.040 0.029 r u_axi_dvi/video_red_OBUF[2]_inst_i_4/CO[3] + net (fo=1, routed) 0.222 0.252 u_axi_dvi/vdata1_in_range07_in + SLICE_X6Y74 LUT5 (Prop_lut5_I2_O) 0.045 0.297 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O + net (fo=3, routed) 1.907 2.203 video_red_OBUF[0] + K23 OBUF (Prop_obuf_I_O) 1.233 3.437 r video_red_OBUF[0]_inst/O + net (fo=0) 0.000 3.437 video_red[0] + K23 r video_red[0] (OUT) + ------------------------------------------------------------------- ------------------- + Slack: inf Source: u_axi_dvi/hdata_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) @@ -29997,7 +17979,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.614ns (logic 1.455ns (40.253%) route 2.159ns (59.747%)) + Data Path Delay: 4.159ns (logic 1.455ns (34.973%) route 2.705ns (65.027%)) Logic Levels: 2 (LUT5=1 OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30015,108 +17997,26 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C + net (fo=35652, routed) 0.712 -0.550 u_axi_dvi/sys_clk + SLICE_X6Y72 FDRE r u_axi_dvi/hdata_reg[11]/C ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.447 0.038 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X9Y86 LUT5 (Prop_lut5_I1_O) 0.045 0.083 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O - net (fo=1, routed) 1.713 1.796 video_hsync_OBUF - J24 OBUF (Prop_obuf_I_O) 1.246 3.041 r video_hsync_OBUF_inst/O - net (fo=0) 0.000 3.041 video_hsync + SLICE_X6Y72 FDRE (Prop_fdre_C_Q) 0.164 -0.386 f u_axi_dvi/hdata_reg[11]/Q + net (fo=12, routed) 0.410 0.023 u_axi_dvi/hdata_reg_n_0_[11] + SLICE_X0Y72 LUT5 (Prop_lut5_I1_O) 0.045 0.068 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O + net (fo=1, routed) 2.295 2.363 video_hsync_OBUF + J24 OBUF (Prop_obuf_I_O) 1.246 3.609 r video_hsync_OBUF_inst/O + net (fo=0) 0.000 3.609 video_hsync J24 r video_hsync (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_axi_dvi/vdata_reg[8]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_vsync - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.713ns (logic 1.505ns (40.539%) route 2.208ns (59.461%)) - Logic Levels: 3 (LUT4=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.687 -0.575 u_axi_dvi/sys_clk - SLICE_X18Y80 FDRE r u_axi_dvi/vdata_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X18Y80 FDRE (Prop_fdre_C_Q) 0.164 -0.411 f u_axi_dvi/vdata_reg[8]/Q - net (fo=11, routed) 0.333 -0.079 u_axi_dvi/vdata_reg_n_0_[8] - SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 -0.034 f u_axi_dvi/video_vsync_OBUF_inst_i_4/O - net (fo=2, routed) 0.093 0.059 u_axi_dvi/video_vsync_OBUF_inst_i_4_n_0 - SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 0.104 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O - net (fo=1, routed) 1.782 1.886 video_vsync_OBUF - H24 OBUF (Prop_obuf_I_O) 1.251 3.138 r video_vsync_OBUF_inst/O - net (fo=0) 0.000 3.138 video_vsync - H24 r video_vsync (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.728ns (logic 1.648ns (44.198%) route 2.081ns (55.802%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.568 1.869 video_red_OBUF[0] - E26 OBUF (Prop_obuf_I_O) 1.287 3.156 r video_red_OBUF[2]_inst/O - net (fo=0) 0.000 3.156 video_red[2] - E26 r video_red[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[3] + Destination: dpy1[7] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 3.728ns (logic 1.356ns (36.384%) route 2.371ns (63.616%)) + Data Path Delay: 4.208ns (logic 1.362ns (32.369%) route 2.846ns (67.631%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30134,345 +18034,14 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q - net (fo=1, routed) 2.371 1.976 dpy1_OBUF[3] - F17 OBUF (Prop_obuf_I_O) 1.215 3.191 r dpy1_OBUF[3]_inst/O - net (fo=0) 0.000 3.191 dpy1[3] - F17 r dpy1[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.827ns (logic 1.622ns (42.374%) route 2.206ns (57.626%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.693 1.994 video_red_OBUF[0] - F24 OBUF (Prop_obuf_I_O) 1.261 3.255 r video_red_OBUF[1]_inst/O - net (fo=0) 0.000 3.255 video_red[1] - F24 r video_red[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.859ns (logic 1.594ns (41.315%) route 2.265ns (58.685%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.752 2.053 video_red_OBUF[0] - K23 OBUF (Prop_obuf_I_O) 1.233 3.287 r video_red_OBUF[0]_inst/O - net (fo=0) 0.000 3.287 video_red[0] - K23 r video_red[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.903ns (logic 1.400ns (35.872%) route 2.503ns (64.128%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q - net (fo=1, routed) 2.503 2.039 dpy0_OBUF[2] - B21 OBUF (Prop_obuf_I_O) 1.259 3.298 r dpy0_OBUF[2]_inst/O - net (fo=0) 0.000 3.298 dpy0[2] - B21 r dpy0[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[2]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.877ns (logic 1.428ns (36.839%) route 2.448ns (63.161%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[2]_lopt_replica/Q - net (fo=1, routed) 2.448 2.053 lopt_8 - A24 OBUF (Prop_obuf_I_O) 1.287 3.340 r leds_OBUF[2]_inst/O - net (fo=0) 0.000 3.340 leds[2] - A24 r leds[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[3] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.896ns (logic 1.404ns (36.025%) route 2.493ns (63.975%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[3]_lopt_replica/Q - net (fo=1, routed) 2.493 2.097 lopt_9 - D23 OBUF (Prop_obuf_I_O) 1.263 3.360 r leds_OBUF[3]_inst/O - net (fo=0) 0.000 3.360 leds[3] - D23 r leds[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[9] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.250ns (logic 1.424ns (33.494%) route 2.827ns (66.506%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[9]_lopt_replica/Q - net (fo=1, routed) 2.827 2.426 lopt_15 - A23 OBUF (Prop_obuf_I_O) 1.283 3.709 r leds_OBUF[9]_inst/O - net (fo=0) 0.000 3.709 leds[9] - A23 r leds[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.428ns (logic 1.436ns (32.434%) route 2.992ns (67.566%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[5]_lopt_replica/Q - net (fo=1, routed) 2.992 2.582 lopt_11 - C21 OBUF (Prop_obuf_I_O) 1.308 3.890 r leds_OBUF[5]_inst/O - net (fo=0) 0.000 3.890 leds[5] - C21 r leds[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.536ns (logic 1.381ns (30.449%) route 3.155ns (69.551%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q - net (fo=1, routed) 3.155 2.691 dpy0_OBUF[4] - E18 OBUF (Prop_obuf_I_O) 1.240 3.931 r dpy0_OBUF[4]_inst/O - net (fo=0) 0.000 3.931 dpy0[4] - E18 r dpy0[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.540ns (logic 1.404ns (30.920%) route 3.136ns (69.080%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[4]_lopt_replica/Q - net (fo=1, routed) 3.136 2.738 lopt_10 - C22 OBUF (Prop_obuf_I_O) 1.263 4.001 r leds_OBUF[4]_inst/O - net (fo=0) 0.000 4.001 leds[4] - C22 r leds[4] (OUT) + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q + net (fo=1, routed) 2.846 2.449 dpy1_OBUF[7] + G17 OBUF (Prop_obuf_I_O) 1.221 3.670 r dpy1_OBUF[7]_inst/O + net (fo=0) 0.000 3.670 dpy1[7] + G17 r dpy1[7] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf @@ -30482,7 +18051,7 @@ Slack: inf (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 4.629ns (logic 1.426ns (30.799%) route 3.203ns (69.201%)) + Data Path Delay: 4.363ns (logic 1.443ns (33.063%) route 2.921ns (66.937%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30500,24 +18069,24 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_confreg/sys_clk - SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.164 -0.380 r u_confreg/led_data_reg[8]_lopt_replica/Q - net (fo=1, routed) 3.203 2.823 lopt_14 - C23 OBUF (Prop_obuf_I_O) 1.262 4.084 r leds_OBUF[8]_inst/O - net (fo=0) 0.000 4.084 leds[8] + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[8]_lopt_replica/Q + net (fo=1, routed) 2.921 2.509 lopt_14 + C23 OBUF (Prop_obuf_I_O) 1.315 3.824 r leds_OBUF[8]_inst/O + net (fo=0) 0.000 3.824 leds[8] C23 r leds[8] (OUT) ------------------------------------------------------------------- ------------------- Slack: inf - Source: u_confreg/led_data_reg[15]_lopt_replica/C + Source: u_confreg/led_data_reg[2]_lopt_replica/C (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[15] + Destination: leds[2] (output port) Path Group: (none) Path Type: Min at Fast Process Corner - Data Path Delay: 4.721ns (logic 1.404ns (29.752%) route 3.316ns (70.248%)) + Data Path Delay: 4.375ns (logic 1.428ns (32.639%) route 2.947ns (67.361%)) Logic Levels: 1 (OBUF=1) Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.050ns @@ -30535,14 +18104,154 @@ Slack: inf -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[15]_lopt_replica/Q - net (fo=1, routed) 3.316 2.920 lopt_6 - B20 OBUF (Prop_obuf_I_O) 1.263 4.183 r leds_OBUF[15]_inst/O - net (fo=0) 0.000 4.183 leds[15] - B20 r leds[15] (OUT) + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[2]_lopt_replica/Q + net (fo=1, routed) 2.947 2.547 lopt_8 + A24 OBUF (Prop_obuf_I_O) 1.287 3.834 r leds_OBUF[2]_inst/O + net (fo=0) 0.000 3.834 leds[2] + A24 r leds[2] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[9]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[9] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.395ns (logic 1.424ns (32.390%) route 2.972ns (67.610%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.721 -0.541 u_confreg/sys_clk + SLICE_X0Y84 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y84 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[9]_lopt_replica/Q + net (fo=1, routed) 2.972 2.571 lopt_15 + A23 OBUF (Prop_obuf_I_O) 1.283 3.854 r leds_OBUF[9]_inst/O + net (fo=0) 0.000 3.854 leds[9] + A23 r leds[9] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[1]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[1] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.695ns (logic 1.424ns (30.329%) route 3.271ns (69.671%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.128 -0.411 r u_confreg/led_data_reg[1]_lopt_replica/Q + net (fo=1, routed) 3.271 2.860 lopt_7 + E21 OBUF (Prop_obuf_I_O) 1.296 4.155 r leds_OBUF[1]_inst/O + net (fo=0) 0.000 4.155 leds[1] + E21 r leds[1] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/led_data_reg[13]_lopt_replica/C + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: leds[13] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 4.756ns (logic 1.412ns (29.687%) route 3.344ns (70.313%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.723 -0.539 u_confreg/sys_clk + SLICE_X0Y88 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C + ------------------------------------------------------------------- ------------------- + SLICE_X0Y88 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[13]_lopt_replica/Q + net (fo=1, routed) 3.344 2.946 lopt_4 + A22 OBUF (Prop_obuf_I_O) 1.271 4.217 r leds_OBUF[13]_inst/O + net (fo=0) 0.000 4.217 leds[13] + A22 r leds[13] (OUT) + ------------------------------------------------------------------- ------------------- + +Slack: inf + Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: dpy1[5] + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 5.792ns (logic 1.376ns (23.753%) route 4.416ns (76.247%)) + Logic Levels: 1 (OBUF=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.724 -0.538 u_confreg/u_digitaltube_controller/sys_clk + SLICE_X1Y57 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C + ------------------------------------------------------------------- ------------------- + SLICE_X1Y57 FDCE (Prop_fdce_C_Q) 0.141 -0.397 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q + net (fo=1, routed) 4.416 4.019 dpy1_OBUF[5] + G16 OBUF (Prop_obuf_I_O) 1.235 5.254 r dpy1_OBUF[5]_inst/O + net (fo=0) 0.000 5.254 dpy1[5] + G16 r dpy1[5] (OUT) ------------------------------------------------------------------- ------------------- @@ -30561,43 +18270,6 @@ Min Delay 43 Endpoints Min Delay Paths -------------------------------------------------------------------------------------- -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.811ns (logic 0.287ns (15.865%) route 1.523ns (84.135%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.523 1.766 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF - SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.045 1.811 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O - net (fo=1, routed) 0.000 1.811 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C - Slack: inf Source: UART_TX (input port) @@ -30605,10 +18277,10 @@ Slack: inf (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.893ns (logic 0.287ns (15.179%) route 1.605ns (84.821%)) + Data Path Delay: 1.872ns (logic 0.287ns (15.346%) route 1.585ns (84.654%)) Logic Levels: 2 (IBUF=1 LUT4=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.231ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.231ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30617,10 +18289,10 @@ Slack: inf H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.605 1.848 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF - SLICE_X1Y61 LUT4 (Prop_lut4_I2_O) 0.045 1.893 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O - net (fo=1, routed) 0.000 1.893 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D + net (fo=4, routed) 1.585 1.827 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF + SLICE_X0Y42 LUT4 (Prop_lut4_I2_O) 0.045 1.872 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O + net (fo=1, routed) 0.000 1.872 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i + SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30632,78 +18304,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Removal (Min at Fast Process Corner) - Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Removal (Min at Fast Process Corner) - Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C + net (fo=35652, routed) 1.077 -0.231 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk + SLICE_X0Y42 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C Slack: inf Source: UART_TX @@ -30712,10 +18314,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.058ns (logic 0.287ns (13.959%) route 1.771ns (86.041%)) + Data Path Delay: 1.957ns (logic 0.287ns (14.676%) route 1.670ns (85.324%)) Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30724,10 +18326,10 @@ Slack: inf H18 0.000 0.000 r UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.045 1.838 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O - net (fo=1, routed) 0.220 2.058 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D + net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT5 (Prop_lut5_I0_O) 0.045 1.957 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O + net (fo=1, routed) 0.000 1.957 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 + SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30739,8 +18341,45 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y38 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C + +Slack: inf + Source: UART_TX + (input port) + Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 1.987ns (logic 0.287ns (14.457%) route 1.700ns (85.543%)) + Logic Levels: 2 (IBUF=1 LUT5=1) + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + H18 0.000 0.000 f UART_TX (INOUT) + net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO + H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O + net (fo=4, routed) 1.700 1.942 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF + SLICE_X1Y39 LUT5 (Prop_lut5_I2_O) 0.045 1.987 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O + net (fo=1, routed) 0.000 1.987 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C Slack: inf Source: UART_TX @@ -30749,10 +18388,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.089ns (logic 0.408ns (19.545%) route 1.681ns (80.455%)) + Data Path Delay: 2.184ns (logic 0.395ns (18.098%) route 1.789ns (81.902%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30761,12 +18400,12 @@ Slack: inf H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.130 1.971 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.118 2.089 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O - net (fo=1, routed) 0.000 2.089 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D + net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.958 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.119 2.077 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X1Y39 LUT6 (Prop_lut6_I2_O) 0.107 2.184 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O + net (fo=1, routed) 0.000 2.184 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30778,43 +18417,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C - -Slack: inf - Source: touch_btn[0] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.121ns (logic 0.267ns (12.568%) route 1.855ns (87.432%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.339ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T2 0.000 0.000 r touch_btn[0] (IN) - net (fo=0) 0.000 0.000 touch_btn[0] - T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O - net (fo=1, routed) 1.855 2.121 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C Slack: inf Source: UART_TX @@ -30823,10 +18427,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.315ns (logic 0.406ns (17.548%) route 1.909ns (82.452%)) + Data Path Delay: 2.412ns (logic 0.394ns (16.343%) route 2.018ns (83.657%)) Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.232ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.232ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -30835,12 +18439,12 @@ Slack: inf H18 0.000 0.000 f UART_TX (INOUT) net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.239 2.080 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.116 2.196 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O - net (fo=1, routed) 0.119 2.315 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D + net (fo=4, routed) 1.670 1.912 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF + SLICE_X1Y38 LUT2 (Prop_lut2_I1_O) 0.046 1.958 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O + net (fo=2, routed) 0.348 2.306 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 + SLICE_X1Y39 LUT5 (Prop_lut5_I1_O) 0.106 2.412 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O + net (fo=1, routed) 0.000 2.412 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -30852,242 +18456,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C - -Slack: inf - Source: dip_sw[31] - (input port) - Destination: u_confreg/s_rdata_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.513ns (logic 0.351ns (13.984%) route 2.162ns (86.016%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R2 0.000 0.000 r dip_sw[31] (IN) - net (fo=0) 0.000 0.000 dip_sw[31] - R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O - net (fo=1, routed) 1.988 2.249 u_confreg/dip_sw_IBUF[31] - SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.294 r u_confreg/s_rdata[31]_i_6/O - net (fo=1, routed) 0.174 2.468 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.513 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O - net (fo=1, routed) 0.000 2.513 u_confreg/u_int_ctrl_n_0 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C - -Slack: inf - Source: dip_sw[27] - (input port) - Destination: u_confreg/s_rdata_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.522ns (logic 0.362ns (14.372%) route 2.159ns (85.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R1 0.000 0.000 r dip_sw[27] (IN) - net (fo=0) 0.000 0.000 dip_sw[27] - R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O - net (fo=1, routed) 1.804 2.076 u_confreg/dip_sw_IBUF[27] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.121 r u_confreg/s_rdata[27]_i_4/O - net (fo=1, routed) 0.356 2.477 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.522 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O - net (fo=1, routed) 0.000 2.522 u_confreg/u_int_ctrl_n_4 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C - -Slack: inf - Source: dip_sw[22] - (input port) - Destination: u_confreg/s_rdata_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.618ns (logic 0.320ns (12.234%) route 2.298ns (87.766%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P6 0.000 0.000 r dip_sw[22] (IN) - net (fo=0) 0.000 0.000 dip_sw[22] - P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O - net (fo=1, routed) 1.991 2.221 u_confreg/dip_sw_IBUF[22] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.266 r u_confreg/s_rdata[22]_i_4/O - net (fo=1, routed) 0.307 2.573 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 - SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.618 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O - net (fo=1, routed) 0.000 2.618 u_confreg/u_int_ctrl_n_9 - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C - -Slack: inf - Source: dip_sw[28] - (input port) - Destination: u_confreg/s_rdata_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.622ns (logic 0.326ns (12.419%) route 2.296ns (87.581%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R5 0.000 0.000 r dip_sw[28] (IN) - net (fo=0) 0.000 0.000 dip_sw[28] - R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O - net (fo=1, routed) 2.141 2.376 u_confreg/dip_sw_IBUF[28] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.421 r u_confreg/s_rdata[28]_i_4/O - net (fo=1, routed) 0.155 2.577 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.622 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O - net (fo=1, routed) 0.000 2.622 u_confreg/u_int_ctrl_n_3 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C - -Slack: inf - Source: dip_sw[30] - (input port) - Destination: u_confreg/s_rdata_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.648ns (logic 0.317ns (11.976%) route 2.331ns (88.024%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R6 0.000 0.000 r dip_sw[30] (IN) - net (fo=0) 0.000 0.000 dip_sw[30] - R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O - net (fo=1, routed) 1.934 2.162 u_confreg/dip_sw_IBUF[30] - SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.207 r u_confreg/s_rdata[30]_i_4/O - net (fo=1, routed) 0.396 2.603 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.648 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O - net (fo=1, routed) 0.000 2.648 u_confreg/u_int_ctrl_n_1 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C - -Slack: inf - Source: dip_sw[18] - (input port) - Destination: u_confreg/s_rdata_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.666ns (logic 0.347ns (13.011%) route 2.319ns (86.989%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.340ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N3 0.000 0.000 r dip_sw[18] (IN) - net (fo=0) 0.000 0.000 dip_sw[18] - N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O - net (fo=1, routed) 2.090 2.347 u_confreg/dip_sw_IBUF[18] - SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.045 2.392 r u_confreg/s_rdata[18]_i_4/O - net (fo=1, routed) 0.229 2.621 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 2.666 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O - net (fo=1, routed) 0.000 2.666 u_confreg/u_int_ctrl_n_13 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C + net (fo=35652, routed) 1.076 -0.232 u_axi_uart_controller/uart0/regs/transmitter/sys_clk + SLICE_X1Y39 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C Slack: inf Source: dip_sw[29] @@ -31096,10 +18466,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.680ns (logic 0.336ns (12.535%) route 2.344ns (87.465%)) + Data Path Delay: 2.665ns (logic 0.336ns (12.609%) route 2.329ns (87.391%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns + Clock Path Skew: -0.309ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31108,12 +18478,12 @@ Slack: inf T5 0.000 0.000 r dip_sw[29] (IN) net (fo=0) 0.000 0.000 dip_sw[29] T5 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[29]_inst/O - net (fo=1, routed) 1.991 2.237 u_confreg/dip_sw_IBUF[29] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.282 r u_confreg/s_rdata[29]_i_4/O - net (fo=1, routed) 0.353 2.635 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.680 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O - net (fo=1, routed) 0.000 2.680 u_confreg/u_int_ctrl_n_2 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D + net (fo=1, routed) 2.278 2.524 u_confreg/dip_sw_IBUF[29] + SLICE_X5Y59 LUT5 (Prop_lut5_I4_O) 0.045 2.569 r u_confreg/s_rdata[29]_i_4/O + net (fo=1, routed) 0.050 2.620 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 + SLICE_X5Y59 LUT6 (Prop_lut6_I4_O) 0.045 2.665 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O + net (fo=1, routed) 0.000 2.665 u_confreg/u_int_ctrl_n_2 + SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31125,34 +18495,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C + net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk + SLICE_X5Y59 FDRE r u_confreg/s_rdata_reg[29]/C Slack: inf - Source: dip_sw[12] + Source: dip_sw[16] (input port) - Destination: u_confreg/s_rdata_reg[12]/D + Destination: u_confreg/s_rdata_reg[16]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.685ns (logic 0.327ns (12.182%) route 2.358ns (87.818%)) + Data Path Delay: 3.200ns (logic 0.358ns (11.179%) route 2.842ns (88.821%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - M5 0.000 0.000 r dip_sw[12] (IN) - net (fo=0) 0.000 0.000 dip_sw[12] - M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O - net (fo=1, routed) 2.193 2.430 u_confreg/dip_sw_IBUF[12] - SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.045 2.475 r u_confreg/s_rdata[12]_i_4/O - net (fo=1, routed) 0.165 2.640 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 2.685 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O - net (fo=1, routed) 0.000 2.685 u_confreg/u_int_ctrl_n_19 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D + K2 0.000 0.000 r dip_sw[16] (IN) + net (fo=0) 0.000 0.000 dip_sw[16] + K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O + net (fo=1, routed) 2.701 2.969 u_confreg/dip_sw_IBUF[16] + SLICE_X1Y56 LUT5 (Prop_lut5_I4_O) 0.045 3.014 r u_confreg/s_rdata[16]_i_4/O + net (fo=1, routed) 0.142 3.155 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 + SLICE_X1Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.200 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O + net (fo=1, routed) 0.000 3.200 u_confreg/u_int_ctrl_n_15 + SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31164,34 +18534,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X1Y54 FDRE r u_confreg/s_rdata_reg[16]/C Slack: inf - Source: dip_sw[7] + Source: dip_sw[11] (input port) - Destination: u_confreg/s_rdata_reg[7]/D + Destination: u_confreg/s_rdata_reg[11]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.753ns (logic 0.329ns (11.958%) route 2.424ns (88.042%)) + Data Path Delay: 3.265ns (logic 0.329ns (10.081%) route 2.936ns (89.919%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.312ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns + Clock Path Skew: -0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - N6 0.000 0.000 r dip_sw[7] (IN) - net (fo=0) 0.000 0.000 dip_sw[7] - N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O - net (fo=1, routed) 2.373 2.612 u_confreg/dip_sw_IBUF[7] - SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.045 2.657 r u_confreg/s_rdata[7]_i_4/O - net (fo=1, routed) 0.051 2.708 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 - SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.045 2.753 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O - net (fo=1, routed) 0.000 2.753 u_confreg/u_int_ctrl_n_24 - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D + L7 0.000 0.000 r dip_sw[11] (IN) + net (fo=0) 0.000 0.000 dip_sw[11] + L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O + net (fo=1, routed) 2.885 3.124 u_confreg/dip_sw_IBUF[11] + SLICE_X9Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.169 r u_confreg/s_rdata[11]_i_4/O + net (fo=1, routed) 0.051 3.220 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 + SLICE_X9Y51 LUT6 (Prop_lut6_I4_O) 0.045 3.265 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O + net (fo=1, routed) 0.000 3.265 u_confreg/u_int_ctrl_n_20 + SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31203,8 +18573,550 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.996 -0.312 u_confreg/sys_clk - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C + net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk + SLICE_X9Y51 FDRE r u_confreg/s_rdata_reg[11]/C + +Slack: inf + Source: dip_sw[13] + (input port) + Destination: u_confreg/s_rdata_reg[13]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.266ns (logic 0.344ns (10.521%) route 2.922ns (89.479%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K3 0.000 0.000 r dip_sw[13] (IN) + net (fo=0) 0.000 0.000 dip_sw[13] + K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O + net (fo=1, routed) 2.784 3.038 u_confreg/dip_sw_IBUF[13] + SLICE_X10Y52 LUT5 (Prop_lut5_I4_O) 0.045 3.083 r u_confreg/s_rdata[13]_i_4/O + net (fo=1, routed) 0.138 3.221 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 + SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.266 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O + net (fo=1, routed) 0.000 3.266 u_confreg/u_int_ctrl_n_18 + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[13]/C + +Slack: inf + Source: dip_sw[0] + (input port) + Destination: u_confreg/s_rdata_reg[0]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.268ns (logic 0.353ns (10.796%) route 2.915ns (89.204%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T3 0.000 0.000 r dip_sw[0] (IN) + net (fo=0) 0.000 0.000 dip_sw[0] + T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O + net (fo=1, routed) 2.694 2.957 u_confreg/dip_sw_IBUF[0] + SLICE_X8Y54 LUT5 (Prop_lut5_I4_O) 0.045 3.002 r u_confreg/s_rdata[0]_i_4/O + net (fo=1, routed) 0.220 3.223 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 + SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.268 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O + net (fo=1, routed) 0.000 3.268 u_confreg/u_int_ctrl_n_31 + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[0]/C + +Slack: inf + Source: dip_sw[6] + (input port) + Destination: u_confreg/s_rdata_reg[6]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.390ns (logic 0.346ns (10.197%) route 3.045ns (89.803%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.336ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.336ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L3 0.000 0.000 r dip_sw[6] (IN) + net (fo=0) 0.000 0.000 dip_sw[6] + L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O + net (fo=1, routed) 2.741 2.996 u_confreg/dip_sw_IBUF[6] + SLICE_X8Y59 LUT5 (Prop_lut5_I4_O) 0.045 3.041 r u_confreg/s_rdata[6]_i_4/O + net (fo=1, routed) 0.304 3.345 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 + SLICE_X8Y54 LUT6 (Prop_lut6_I4_O) 0.045 3.390 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O + net (fo=1, routed) 0.000 3.390 u_confreg/u_int_ctrl_n_25 + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.972 -0.336 u_confreg/sys_clk + SLICE_X8Y54 FDRE r u_confreg/s_rdata_reg[6]/C + +Slack: inf + Source: dip_sw[19] + (input port) + Destination: u_confreg/s_rdata_reg[19]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.414ns (logic 0.336ns (9.845%) route 3.078ns (90.155%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.338ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L4 0.000 0.000 r dip_sw[19] (IN) + net (fo=0) 0.000 0.000 dip_sw[19] + L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O + net (fo=1, routed) 3.026 3.272 u_confreg/dip_sw_IBUF[19] + SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.317 r u_confreg/s_rdata[19]_i_4/O + net (fo=1, routed) 0.051 3.369 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 + SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.414 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O + net (fo=1, routed) 0.000 3.414 u_confreg/u_int_ctrl_n_12 + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.970 -0.338 u_confreg/sys_clk + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[19]/C + +Slack: inf + Source: dip_sw[14] + (input port) + Destination: u_confreg/s_rdata_reg[14]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.434ns (logic 0.373ns (10.848%) route 3.061ns (89.152%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J1 0.000 0.000 r dip_sw[14] (IN) + net (fo=0) 0.000 0.000 dip_sw[14] + J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O + net (fo=1, routed) 3.010 3.293 u_confreg/dip_sw_IBUF[14] + SLICE_X1Y53 LUT5 (Prop_lut5_I4_O) 0.045 3.338 r u_confreg/s_rdata[14]_i_4/O + net (fo=1, routed) 0.051 3.389 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 + SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.434 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O + net (fo=1, routed) 0.000 3.434 u_confreg/u_int_ctrl_n_17 + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[14]/C + +Slack: inf + Source: dip_sw[10] + (input port) + Destination: u_confreg/s_rdata_reg[10]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.439ns (logic 0.330ns (9.600%) route 3.109ns (90.400%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.260ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.260ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M7 0.000 0.000 r dip_sw[10] (IN) + net (fo=0) 0.000 0.000 dip_sw[10] + M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O + net (fo=1, routed) 3.053 3.293 u_confreg/dip_sw_IBUF[10] + SLICE_X10Y49 LUT5 (Prop_lut5_I4_O) 0.045 3.338 r u_confreg/s_rdata[10]_i_4/O + net (fo=1, routed) 0.056 3.394 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 + SLICE_X10Y49 LUT6 (Prop_lut6_I4_O) 0.045 3.439 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O + net (fo=1, routed) 0.000 3.439 u_confreg/u_int_ctrl_n_21 + SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.048 -0.260 u_confreg/sys_clk + SLICE_X10Y49 FDRE r u_confreg/s_rdata_reg[10]/C + +Slack: inf + Source: dip_sw[8] + (input port) + Destination: u_confreg/s_rdata_reg[8]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.468ns (logic 0.334ns (9.621%) route 3.134ns (90.379%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.335ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.335ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M6 0.000 0.000 r dip_sw[8] (IN) + net (fo=0) 0.000 0.000 dip_sw[8] + M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O + net (fo=1, routed) 2.855 3.099 u_confreg/dip_sw_IBUF[8] + SLICE_X11Y54 LUT5 (Prop_lut5_I4_O) 0.045 3.144 r u_confreg/s_rdata[8]_i_4/O + net (fo=1, routed) 0.279 3.423 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 + SLICE_X11Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.468 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O + net (fo=1, routed) 0.000 3.468 u_confreg/u_int_ctrl_n_23 + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.973 -0.335 u_confreg/sys_clk + SLICE_X11Y52 FDRE r u_confreg/s_rdata_reg[8]/C + +Slack: inf + Source: dip_sw[5] + (input port) + Destination: u_confreg/s_rdata_reg[5]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.503ns (logic 0.328ns (9.375%) route 3.174ns (90.625%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.305ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.305ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L5 0.000 0.000 r dip_sw[5] (IN) + net (fo=0) 0.000 0.000 dip_sw[5] + L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O + net (fo=1, routed) 3.123 3.361 u_confreg/dip_sw_IBUF[5] + SLICE_X3Y52 LUT5 (Prop_lut5_I4_O) 0.045 3.406 r u_confreg/s_rdata[5]_i_4/O + net (fo=1, routed) 0.051 3.458 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 + SLICE_X3Y52 LUT6 (Prop_lut6_I4_O) 0.045 3.503 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O + net (fo=1, routed) 0.000 3.503 u_confreg/u_int_ctrl_n_26 + SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.003 -0.305 u_confreg/sys_clk + SLICE_X3Y52 FDRE r u_confreg/s_rdata_reg[5]/C + +Slack: inf + Source: dip_sw[15] + (input port) + Destination: u_confreg/s_rdata_reg[15]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.507ns (logic 0.352ns (10.034%) route 3.155ns (89.966%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + L2 0.000 0.000 r dip_sw[15] (IN) + net (fo=0) 0.000 0.000 dip_sw[15] + L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O + net (fo=1, routed) 2.926 3.188 u_confreg/dip_sw_IBUF[15] + SLICE_X2Y53 LUT5 (Prop_lut5_I4_O) 0.045 3.233 r u_confreg/s_rdata[15]_i_4/O + net (fo=1, routed) 0.229 3.462 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 + SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.507 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O + net (fo=1, routed) 0.000 3.507 u_confreg/u_int_ctrl_n_16 + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[15]/C + +Slack: inf + Source: touch_btn[2] + (input port) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.530ns (logic 0.255ns (7.212%) route 3.276ns (92.788%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.340ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.340ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P3 0.000 0.000 r touch_btn[2] (IN) + net (fo=0) 0.000 0.000 touch_btn[2] + P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O + net (fo=1, routed) 3.276 3.530 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] + SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.968 -0.340 u_confreg/u_int_ctrl/sys_clk + SLICE_X9Y62 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C + +Slack: inf + Source: dip_sw[9] + (input port) + Destination: u_confreg/s_rdata_reg[9]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.537ns (logic 0.328ns (9.266%) route 3.209ns (90.734%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N7 0.000 0.000 r dip_sw[9] (IN) + net (fo=0) 0.000 0.000 dip_sw[9] + N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O + net (fo=1, routed) 3.010 3.247 u_confreg/dip_sw_IBUF[9] + SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.292 r u_confreg/s_rdata[9]_i_4/O + net (fo=1, routed) 0.199 3.492 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 + SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.045 3.537 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O + net (fo=1, routed) 0.000 3.537 u_confreg/u_int_ctrl_n_22 + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[9]/C + +Slack: inf + Source: dip_sw[23] + (input port) + Destination: u_confreg/s_rdata_reg[23]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.560ns (logic 0.376ns (10.559%) route 3.184ns (89.441%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + N1 0.000 0.000 r dip_sw[23] (IN) + net (fo=0) 0.000 0.000 dip_sw[23] + N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O + net (fo=1, routed) 2.820 3.106 u_confreg/dip_sw_IBUF[23] + SLICE_X15Y60 LUT5 (Prop_lut5_I4_O) 0.045 3.151 r u_confreg/s_rdata[23]_i_4/O + net (fo=1, routed) 0.365 3.515 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 3.560 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O + net (fo=1, routed) 0.000 3.560 u_confreg/u_int_ctrl_n_8 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[23]/C + +Slack: inf + Source: dip_sw[2] + (input port) + Destination: u_confreg/s_rdata_reg[2]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.591ns (logic 0.353ns (9.826%) route 3.238ns (90.174%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M2 0.000 0.000 r dip_sw[2] (IN) + net (fo=0) 0.000 0.000 dip_sw[2] + M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O + net (fo=1, routed) 2.898 3.161 u_confreg/dip_sw_IBUF[2] + SLICE_X2Y56 LUT5 (Prop_lut5_I4_O) 0.045 3.206 r u_confreg/s_rdata[2]_i_4/O + net (fo=1, routed) 0.340 3.546 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 + SLICE_X2Y53 LUT6 (Prop_lut6_I4_O) 0.045 3.591 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O + net (fo=1, routed) 0.000 3.591 u_confreg/u_int_ctrl_n_29 + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X2Y53 FDRE r u_confreg/s_rdata_reg[2]/C + +Slack: inf + Source: dip_sw[17] + (input port) + Destination: u_confreg/s_rdata_reg[17]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.592ns (logic 0.362ns (10.072%) route 3.230ns (89.928%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + K1 0.000 0.000 r dip_sw[17] (IN) + net (fo=0) 0.000 0.000 dip_sw[17] + K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O + net (fo=1, routed) 3.009 3.281 u_confreg/dip_sw_IBUF[17] + SLICE_X3Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.326 r u_confreg/s_rdata[17]_i_4/O + net (fo=1, routed) 0.221 3.547 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 + SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.592 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O + net (fo=1, routed) 0.000 3.592 u_confreg/u_int_ctrl_n_14 + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[17]/C Slack: inf Source: dip_sw[24] @@ -31213,10 +19125,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.843ns (logic 0.324ns (11.413%) route 2.518ns (88.587%)) + Data Path Delay: 3.594ns (logic 0.324ns (9.027%) route 3.270ns (90.973%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns + Clock Path Skew: -0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31225,12 +19137,12 @@ Slack: inf P5 0.000 0.000 r dip_sw[24] (IN) net (fo=0) 0.000 0.000 dip_sw[24] P5 IBUF (Prop_ibuf_I_O) 0.234 0.234 r dip_sw_IBUF[24]_inst/O - net (fo=1, routed) 2.106 2.340 u_confreg/dip_sw_IBUF[24] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.385 r u_confreg/s_rdata[24]_i_4/O - net (fo=1, routed) 0.412 2.798 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.843 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O - net (fo=1, routed) 0.000 2.843 u_confreg/u_int_ctrl_n_7 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D + net (fo=1, routed) 3.131 3.365 u_confreg/dip_sw_IBUF[24] + SLICE_X15Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.410 r u_confreg/s_rdata[24]_i_4/O + net (fo=1, routed) 0.139 3.549 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 + SLICE_X15Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.594 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O + net (fo=1, routed) 0.000 3.594 u_confreg/u_int_ctrl_n_7 + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31242,8 +19154,203 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C + net (fo=35652, routed) 0.970 -0.338 u_confreg/sys_clk + SLICE_X15Y58 FDRE r u_confreg/s_rdata_reg[24]/C + +Slack: inf + Source: dip_sw[12] + (input port) + Destination: u_confreg/s_rdata_reg[12]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.598ns (logic 0.327ns (9.090%) route 3.271ns (90.910%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M5 0.000 0.000 r dip_sw[12] (IN) + net (fo=0) 0.000 0.000 dip_sw[12] + M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O + net (fo=1, routed) 3.009 3.246 u_confreg/dip_sw_IBUF[12] + SLICE_X14Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.291 r u_confreg/s_rdata[12]_i_4/O + net (fo=1, routed) 0.262 3.553 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 + SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.045 3.598 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O + net (fo=1, routed) 0.000 3.598 u_confreg/u_int_ctrl_n_19 + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[12]/C + +Slack: inf + Source: dip_sw[1] + (input port) + Destination: u_confreg/s_rdata_reg[1]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.716ns (logic 0.355ns (9.565%) route 3.361ns (90.435%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + J3 0.000 0.000 r dip_sw[1] (IN) + net (fo=0) 0.000 0.000 dip_sw[1] + J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O + net (fo=1, routed) 3.093 3.358 u_confreg/dip_sw_IBUF[1] + SLICE_X5Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.403 r u_confreg/s_rdata[1]_i_4/O + net (fo=1, routed) 0.268 3.671 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 + SLICE_X5Y50 LUT6 (Prop_lut6_I4_O) 0.045 3.716 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O + net (fo=1, routed) 0.000 3.716 u_confreg/u_int_ctrl_n_30 + SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X5Y50 FDRE r u_confreg/s_rdata_reg[1]/C + +Slack: inf + Source: dip_sw[20] + (input port) + Destination: u_confreg/s_rdata_reg[20]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.770ns (logic 0.333ns (8.832%) route 3.437ns (91.168%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + M4 0.000 0.000 r dip_sw[20] (IN) + net (fo=0) 0.000 0.000 dip_sw[20] + M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O + net (fo=1, routed) 3.269 3.512 u_confreg/dip_sw_IBUF[20] + SLICE_X1Y61 LUT5 (Prop_lut5_I4_O) 0.045 3.557 r u_confreg/s_rdata[20]_i_4/O + net (fo=1, routed) 0.168 3.725 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 + SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.770 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O + net (fo=1, routed) 0.000 3.770 u_confreg/u_int_ctrl_n_11 + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[20]/C + +Slack: inf + Source: dip_sw[26] + (input port) + Destination: u_confreg/s_rdata_reg[26]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.868ns (logic 0.367ns (9.485%) route 3.501ns (90.515%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + T4 0.000 0.000 r dip_sw[26] (IN) + net (fo=0) 0.000 0.000 dip_sw[26] + T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O + net (fo=1, routed) 3.288 3.565 u_confreg/dip_sw_IBUF[26] + SLICE_X1Y58 LUT5 (Prop_lut5_I4_O) 0.045 3.610 r u_confreg/s_rdata[26]_i_4/O + net (fo=1, routed) 0.213 3.823 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 + SLICE_X1Y58 LUT6 (Prop_lut6_I4_O) 0.045 3.868 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O + net (fo=1, routed) 0.000 3.868 u_confreg/u_int_ctrl_n_5 + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X1Y58 FDRE r u_confreg/s_rdata_reg[26]/C + +Slack: inf + Source: dip_sw[3] + (input port) + Destination: u_confreg/s_rdata_reg[3]/D + (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Hold (Min at Fast Process Corner) + Data Path Delay: 3.879ns (logic 0.362ns (9.330%) route 3.517ns (90.670%)) + Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns + Source Clock Delay (SCD): 0.000ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + P1 0.000 0.000 r dip_sw[3] (IN) + net (fo=0) 0.000 0.000 dip_sw[3] + P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O + net (fo=1, routed) 3.459 3.731 u_confreg/dip_sw_IBUF[3] + SLICE_X4Y51 LUT5 (Prop_lut5_I4_O) 0.045 3.776 r u_confreg/s_rdata[3]_i_4/O + net (fo=1, routed) 0.059 3.834 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 + SLICE_X4Y51 LUT6 (Prop_lut6_I4_O) 0.045 3.879 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O + net (fo=1, routed) 0.000 3.879 u_confreg/u_int_ctrl_n_28 + SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X4Y51 FDRE r u_confreg/s_rdata_reg[3]/C Slack: inf Source: touch_btn[1] @@ -31252,7 +19359,7 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.881ns (logic 0.283ns (9.807%) route 2.599ns (90.193%)) + Data Path Delay: 3.995ns (logic 0.283ns (7.072%) route 3.713ns (92.928%)) Logic Levels: 1 (IBUF=1) Clock Path Skew: -0.339ns (DCD - SCD - CPR) Destination Clock Delay (DCD): -0.339ns @@ -31264,8 +19371,8 @@ Slack: inf M1 0.000 0.000 r touch_btn[1] (IN) net (fo=0) 0.000 0.000 touch_btn[1] M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O - net (fo=1, routed) 2.599 2.881 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D + net (fo=1, routed) 3.713 3.995 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] + SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31277,125 +19384,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C - -Slack: inf - Source: dip_sw[3] - (input port) - Destination: u_confreg/s_rdata_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.900ns (logic 0.362ns (12.483%) route 2.538ns (87.517%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.319ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P1 0.000 0.000 r dip_sw[3] (IN) - net (fo=0) 0.000 0.000 dip_sw[3] - P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O - net (fo=1, routed) 2.197 2.469 u_confreg/dip_sw_IBUF[3] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.514 r u_confreg/s_rdata[3]_i_4/O - net (fo=1, routed) 0.340 2.855 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 2.900 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O - net (fo=1, routed) 0.000 2.900 u_confreg/u_int_ctrl_n_28 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C - -Slack: inf - Source: dip_sw[16] - (input port) - Destination: u_confreg/s_rdata_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.965ns (logic 0.358ns (12.066%) route 2.607ns (87.934%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K2 0.000 0.000 r dip_sw[16] (IN) - net (fo=0) 0.000 0.000 dip_sw[16] - K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O - net (fo=1, routed) 2.496 2.764 u_confreg/dip_sw_IBUF[16] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.809 r u_confreg/s_rdata[16]_i_4/O - net (fo=1, routed) 0.111 2.920 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.965 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O - net (fo=1, routed) 0.000 2.965 u_confreg/u_int_ctrl_n_15 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C - -Slack: inf - Source: dip_sw[0] - (input port) - Destination: u_confreg/s_rdata_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.973ns (logic 0.353ns (11.866%) route 2.620ns (88.134%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T3 0.000 0.000 r dip_sw[0] (IN) - net (fo=0) 0.000 0.000 dip_sw[0] - T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O - net (fo=1, routed) 2.278 2.541 u_confreg/dip_sw_IBUF[0] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.586 r u_confreg/s_rdata[0]_i_4/O - net (fo=1, routed) 0.342 2.928 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 2.973 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O - net (fo=1, routed) 0.000 2.973 u_confreg/u_int_ctrl_n_31 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C + net (fo=35652, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk + SLICE_X15Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C Slack: inf Source: touch_btn[3] @@ -31404,10 +19394,10 @@ Slack: inf (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.974ns (logic 0.280ns (9.424%) route 2.694ns (90.576%)) + Data Path Delay: 4.065ns (logic 0.280ns (6.894%) route 3.785ns (93.106%)) Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.317ns + Clock Path Skew: -0.338ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.338ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31416,8 +19406,8 @@ Slack: inf U2 0.000 0.000 r touch_btn[3] (IN) net (fo=0) 0.000 0.000 touch_btn[3] U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O - net (fo=1, routed) 2.694 2.974 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D + net (fo=1, routed) 3.785 4.065 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] + SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31429,34 +19419,30 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.991 -0.317 u_confreg/u_int_ctrl/sys_clk - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C + net (fo=35652, routed) 0.970 -0.338 u_confreg/u_int_ctrl/sys_clk + SLICE_X10Y61 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C Slack: inf - Source: dip_sw[14] + Source: touch_btn[0] (input port) - Destination: u_confreg/s_rdata_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D + (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.984ns (logic 0.373ns (12.482%) route 2.612ns (87.518%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns + Data Path Delay: 4.085ns (logic 0.267ns (6.527%) route 3.818ns (93.473%)) + Logic Levels: 1 (IBUF=1) + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - J1 0.000 0.000 r dip_sw[14] (IN) - net (fo=0) 0.000 0.000 dip_sw[14] - J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O - net (fo=1, routed) 2.273 2.555 u_confreg/dip_sw_IBUF[14] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.600 r u_confreg/s_rdata[14]_i_4/O - net (fo=1, routed) 0.339 2.939 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.984 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O - net (fo=1, routed) 0.000 2.984 u_confreg/u_int_ctrl_n_17 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D + T2 0.000 0.000 r touch_btn[0] (IN) + net (fo=0) 0.000 0.000 touch_btn[0] + T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O + net (fo=1, routed) 3.818 4.085 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] + SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31468,8 +19454,78 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/u_int_ctrl/sys_clk + SLICE_X8Y57 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C + +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 4.205ns (logic 0.045ns (1.070%) route 4.160ns (98.930%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + net (fo=1, routed) 3.932 3.932 pll_clk.u_rst_sys/locked + SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.045 3.977 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.228 4.205 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.922 -0.386 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C + +Slack: inf + Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + (internal pin) + Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR + (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: (none) + Path Type: Removal (Min at Fast Process Corner) + Data Path Delay: 4.205ns (logic 0.045ns (1.070%) route 4.160ns (98.930%)) + Logic Levels: 1 (LUT1=1) + Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Discrete Jitter (DJ): 0.122ns + Phase Error (PE): 0.124ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED + net (fo=1, routed) 3.932 3.932 pll_clk.u_rst_sys/locked + SLICE_X106Y69 LUT1 (Prop_lut1_I0_O) 0.045 3.977 f pll_clk.u_rst_sys/delay[1]_i_1/O + net (fo=2, routed) 0.228 4.205 pll_clk.u_rst_sys/delay[1]_i_1_n_0 + SLICE_X106Y69 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR + ------------------------------------------------------------------- ------------------- + + (clock sys_clk rise edge) 0.000 0.000 r + K21 0.000 0.000 r clk (IN) + net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 + K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O + net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll + PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) + -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 + net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll + BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O + net (fo=35652, routed) 0.922 -0.386 pll_clk.u_rst_sys/sys_clk + SLICE_X106Y69 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C Slack: inf Source: dip_sw[21] @@ -31478,10 +19534,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.997ns (logic 0.346ns (11.544%) route 2.651ns (88.456%)) + Data Path Delay: 4.217ns (logic 0.346ns (8.203%) route 3.871ns (91.797%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31490,12 +19546,12 @@ Slack: inf N2 0.000 0.000 r dip_sw[21] (IN) net (fo=0) 0.000 0.000 dip_sw[21] N2 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[21]_inst/O - net (fo=1, routed) 2.278 2.534 u_confreg/dip_sw_IBUF[21] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.579 r u_confreg/s_rdata[21]_i_4/O - net (fo=1, routed) 0.373 2.952 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.997 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O - net (fo=1, routed) 0.000 2.997 u_confreg/u_int_ctrl_n_10 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D + net (fo=1, routed) 3.762 4.018 u_confreg/dip_sw_IBUF[21] + SLICE_X12Y56 LUT5 (Prop_lut5_I4_O) 0.045 4.063 r u_confreg/s_rdata[21]_i_4/O + net (fo=1, routed) 0.110 4.172 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 + SLICE_X13Y56 LUT6 (Prop_lut6_I4_O) 0.045 4.217 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O + net (fo=1, routed) 0.000 4.217 u_confreg/u_int_ctrl_n_10 + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31507,34 +19563,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y56 FDRE r u_confreg/s_rdata_reg[21]/C Slack: inf - Source: dip_sw[6] + Source: dip_sw[31] (input port) - Destination: u_confreg/s_rdata_reg[6]/D + Destination: u_confreg/s_rdata_reg[31]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.000ns (logic 0.346ns (11.523%) route 2.655ns (88.477%)) + Data Path Delay: 4.251ns (logic 0.351ns (8.267%) route 3.899ns (91.733%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - L3 0.000 0.000 r dip_sw[6] (IN) - net (fo=0) 0.000 0.000 dip_sw[6] - L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O - net (fo=1, routed) 2.297 2.553 u_confreg/dip_sw_IBUF[6] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.598 r u_confreg/s_rdata[6]_i_4/O - net (fo=1, routed) 0.358 2.955 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.000 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O - net (fo=1, routed) 0.000 3.000 u_confreg/u_int_ctrl_n_25 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D + R2 0.000 0.000 r dip_sw[31] (IN) + net (fo=0) 0.000 0.000 dip_sw[31] + R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O + net (fo=1, routed) 3.787 4.048 u_confreg/dip_sw_IBUF[31] + SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.045 4.093 r u_confreg/s_rdata[31]_i_6/O + net (fo=1, routed) 0.112 4.206 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.251 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O + net (fo=1, routed) 0.000 4.251 u_confreg/u_int_ctrl_n_0 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31546,34 +19602,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[31]/C Slack: inf - Source: dip_sw[26] + Source: dip_sw[18] (input port) - Destination: u_confreg/s_rdata_reg[26]/D + Destination: u_confreg/s_rdata_reg[18]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.025ns (logic 0.367ns (12.128%) route 2.658ns (87.872%)) + Data Path Delay: 4.259ns (logic 0.347ns (8.145%) route 3.912ns (91.855%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.340ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - T4 0.000 0.000 r dip_sw[26] (IN) - net (fo=0) 0.000 0.000 dip_sw[26] - T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O - net (fo=1, routed) 2.208 2.485 u_confreg/dip_sw_IBUF[26] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.530 r u_confreg/s_rdata[26]_i_4/O - net (fo=1, routed) 0.450 2.980 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 3.025 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O - net (fo=1, routed) 0.000 3.025 u_confreg/u_int_ctrl_n_5 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D + N3 0.000 0.000 r dip_sw[18] (IN) + net (fo=0) 0.000 0.000 dip_sw[18] + N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O + net (fo=1, routed) 3.633 3.889 u_confreg/dip_sw_IBUF[18] + SLICE_X13Y57 LUT5 (Prop_lut5_I4_O) 0.045 3.934 r u_confreg/s_rdata[18]_i_4/O + net (fo=1, routed) 0.279 4.214 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 + SLICE_X13Y55 LUT6 (Prop_lut6_I4_O) 0.045 4.259 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O + net (fo=1, routed) 0.000 4.259 u_confreg/u_int_ctrl_n_13 + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31585,34 +19641,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X13Y55 FDRE r u_confreg/s_rdata_reg[18]/C Slack: inf - Source: dip_sw[10] + Source: dip_sw[30] (input port) - Destination: u_confreg/s_rdata_reg[10]/D + Destination: u_confreg/s_rdata_reg[30]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.067ns (logic 0.330ns (10.763%) route 2.737ns (89.237%)) + Data Path Delay: 4.355ns (logic 0.317ns (7.282%) route 4.038ns (92.718%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - M7 0.000 0.000 r dip_sw[10] (IN) - net (fo=0) 0.000 0.000 dip_sw[10] - M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O - net (fo=1, routed) 2.590 2.830 u_confreg/dip_sw_IBUF[10] - SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.045 2.875 r u_confreg/s_rdata[10]_i_4/O - net (fo=1, routed) 0.147 3.022 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.067 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O - net (fo=1, routed) 0.000 3.067 u_confreg/u_int_ctrl_n_21 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D + R6 0.000 0.000 r dip_sw[30] (IN) + net (fo=0) 0.000 0.000 dip_sw[30] + R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O + net (fo=1, routed) 3.935 4.162 u_confreg/dip_sw_IBUF[30] + SLICE_X9Y60 LUT5 (Prop_lut5_I4_O) 0.045 4.207 r u_confreg/s_rdata[30]_i_4/O + net (fo=1, routed) 0.103 4.310 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.355 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O + net (fo=1, routed) 0.000 4.355 u_confreg/u_int_ctrl_n_1 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31624,34 +19680,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[30]/C Slack: inf - Source: dip_sw[15] + Source: dip_sw[22] (input port) - Destination: u_confreg/s_rdata_reg[15]/D + Destination: u_confreg/s_rdata_reg[22]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.091ns (logic 0.352ns (11.385%) route 2.739ns (88.615%)) + Data Path Delay: 4.425ns (logic 0.320ns (7.240%) route 4.104ns (92.760%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns + Clock Path Skew: -0.337ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.337ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - L2 0.000 0.000 r dip_sw[15] (IN) - net (fo=0) 0.000 0.000 dip_sw[15] - L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O - net (fo=1, routed) 2.453 2.715 u_confreg/dip_sw_IBUF[15] - SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.045 2.760 r u_confreg/s_rdata[15]_i_4/O - net (fo=1, routed) 0.285 3.046 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.091 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O - net (fo=1, routed) 0.000 3.091 u_confreg/u_int_ctrl_n_16 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D + P6 0.000 0.000 r dip_sw[22] (IN) + net (fo=0) 0.000 0.000 dip_sw[22] + P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O + net (fo=1, routed) 3.963 4.193 u_confreg/dip_sw_IBUF[22] + SLICE_X9Y61 LUT5 (Prop_lut5_I4_O) 0.045 4.238 r u_confreg/s_rdata[22]_i_4/O + net (fo=1, routed) 0.142 4.380 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 + SLICE_X9Y59 LUT6 (Prop_lut6_I4_O) 0.045 4.425 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O + net (fo=1, routed) 0.000 4.425 u_confreg/u_int_ctrl_n_9 + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31663,34 +19719,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C + net (fo=35652, routed) 0.971 -0.337 u_confreg/sys_clk + SLICE_X9Y59 FDRE r u_confreg/s_rdata_reg[22]/C Slack: inf - Source: dip_sw[5] + Source: dip_sw[7] (input port) - Destination: u_confreg/s_rdata_reg[5]/D + Destination: u_confreg/s_rdata_reg[7]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.122ns (logic 0.328ns (10.518%) route 2.794ns (89.482%)) + Data Path Delay: 4.560ns (logic 0.329ns (7.220%) route 4.231ns (92.780%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - L5 0.000 0.000 r dip_sw[5] (IN) - net (fo=0) 0.000 0.000 dip_sw[5] - L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O - net (fo=1, routed) 2.365 2.604 u_confreg/dip_sw_IBUF[5] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.649 r u_confreg/s_rdata[5]_i_4/O - net (fo=1, routed) 0.428 3.077 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.122 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O - net (fo=1, routed) 0.000 3.122 u_confreg/u_int_ctrl_n_26 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D + N6 0.000 0.000 r dip_sw[7] (IN) + net (fo=0) 0.000 0.000 dip_sw[7] + N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O + net (fo=1, routed) 4.018 4.257 u_confreg/dip_sw_IBUF[7] + SLICE_X3Y56 LUT5 (Prop_lut5_I4_O) 0.045 4.302 r u_confreg/s_rdata[7]_i_4/O + net (fo=1, routed) 0.213 4.515 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 + SLICE_X3Y56 LUT6 (Prop_lut6_I4_O) 0.045 4.560 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O + net (fo=1, routed) 0.000 4.560 u_confreg/u_int_ctrl_n_24 + SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31702,125 +19758,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C - -Slack: inf - Source: dip_sw[2] - (input port) - Destination: u_confreg/s_rdata_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.123ns (logic 0.353ns (11.299%) route 2.770ns (88.701%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M2 0.000 0.000 r dip_sw[2] (IN) - net (fo=0) 0.000 0.000 dip_sw[2] - M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O - net (fo=1, routed) 2.335 2.598 u_confreg/dip_sw_IBUF[2] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.643 r u_confreg/s_rdata[2]_i_4/O - net (fo=1, routed) 0.435 3.078 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.123 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O - net (fo=1, routed) 0.000 3.123 u_confreg/u_int_ctrl_n_29 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C - -Slack: inf - Source: dip_sw[17] - (input port) - Destination: u_confreg/s_rdata_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.171ns (logic 0.362ns (11.408%) route 2.809ns (88.593%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K1 0.000 0.000 r dip_sw[17] (IN) - net (fo=0) 0.000 0.000 dip_sw[17] - K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O - net (fo=1, routed) 2.515 2.787 u_confreg/dip_sw_IBUF[17] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.832 r u_confreg/s_rdata[17]_i_4/O - net (fo=1, routed) 0.294 3.126 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.171 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O - net (fo=1, routed) 0.000 3.171 u_confreg/u_int_ctrl_n_14 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C - -Slack: inf - Source: dip_sw[23] - (input port) - Destination: u_confreg/s_rdata_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.218ns (logic 0.376ns (11.683%) route 2.842ns (88.317%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N1 0.000 0.000 r dip_sw[23] (IN) - net (fo=0) 0.000 0.000 dip_sw[23] - N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O - net (fo=1, routed) 2.402 2.688 u_confreg/dip_sw_IBUF[23] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.733 r u_confreg/s_rdata[23]_i_4/O - net (fo=1, routed) 0.440 3.173 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 3.218 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O - net (fo=1, routed) 0.000 3.218 u_confreg/u_int_ctrl_n_8 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X3Y56 FDRE r u_confreg/s_rdata_reg[7]/C Slack: inf Source: dip_sw[4] @@ -31829,10 +19768,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.278ns (logic 0.346ns (10.553%) route 2.932ns (89.447%)) + Data Path Delay: 4.587ns (logic 0.346ns (7.542%) route 4.241ns (92.458%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.313ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.313ns + Clock Path Skew: -0.306ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.306ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31841,12 +19780,12 @@ Slack: inf P4 0.000 0.000 r dip_sw[4] (IN) net (fo=0) 0.000 0.000 dip_sw[4] P4 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[4]_inst/O - net (fo=1, routed) 2.708 2.964 u_confreg/dip_sw_IBUF[4] - SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.045 3.009 r u_confreg/s_rdata[4]_i_4/O - net (fo=1, routed) 0.224 3.233 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 - SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.278 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O - net (fo=1, routed) 0.000 3.278 u_confreg/u_int_ctrl_n_27 - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D + net (fo=1, routed) 3.727 3.983 u_confreg/dip_sw_IBUF[4] + SLICE_X0Y59 LUT5 (Prop_lut5_I4_O) 0.045 4.028 r u_confreg/s_rdata[4]_i_4/O + net (fo=1, routed) 0.514 4.542 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 + SLICE_X1Y53 LUT6 (Prop_lut6_I4_O) 0.045 4.587 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O + net (fo=1, routed) 0.000 4.587 u_confreg/u_int_ctrl_n_27 + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31858,34 +19797,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C + net (fo=35652, routed) 1.002 -0.306 u_confreg/sys_clk + SLICE_X1Y53 FDRE r u_confreg/s_rdata_reg[4]/C Slack: inf - Source: dip_sw[9] + Source: dip_sw[27] (input port) - Destination: u_confreg/s_rdata_reg[9]/D + Destination: u_confreg/s_rdata_reg[27]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.293ns (logic 0.328ns (9.951%) route 2.965ns (90.049%)) + Data Path Delay: 4.738ns (logic 0.362ns (7.650%) route 4.375ns (92.350%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns + Clock Path Skew: -0.309ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - N7 0.000 0.000 r dip_sw[9] (IN) - net (fo=0) 0.000 0.000 dip_sw[9] - N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O - net (fo=1, routed) 2.752 2.990 u_confreg/dip_sw_IBUF[9] - SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.045 3.035 r u_confreg/s_rdata[9]_i_4/O - net (fo=1, routed) 0.213 3.248 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 - SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.045 3.293 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O - net (fo=1, routed) 0.000 3.293 u_confreg/u_int_ctrl_n_22 - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D + R1 0.000 0.000 r dip_sw[27] (IN) + net (fo=0) 0.000 0.000 dip_sw[27] + R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O + net (fo=1, routed) 4.155 4.428 u_confreg/dip_sw_IBUF[27] + SLICE_X5Y58 LUT5 (Prop_lut5_I4_O) 0.045 4.473 r u_confreg/s_rdata[27]_i_4/O + net (fo=1, routed) 0.220 4.693 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 + SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.045 4.738 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O + net (fo=1, routed) 0.000 4.738 u_confreg/u_int_ctrl_n_4 + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31897,69 +19836,34 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C + net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[27]/C Slack: inf - Source: touch_btn[2] + Source: dip_sw[28] (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.287ns (logic 0.255ns (5.940%) route 4.032ns (94.060%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P3 0.000 0.000 r touch_btn[2] (IN) - net (fo=0) 0.000 0.000 touch_btn[2] - P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O - net (fo=1, routed) 4.032 4.287 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/u_int_ctrl/sys_clk - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C - -Slack: inf - Source: dip_sw[19] - (input port) - Destination: u_confreg/s_rdata_reg[19]/D + Destination: u_confreg/s_rdata_reg[28]/D (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.396ns (logic 0.336ns (7.645%) route 4.060ns (92.355%)) + Data Path Delay: 4.824ns (logic 0.326ns (6.749%) route 4.499ns (93.251%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.313ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.313ns + Clock Path Skew: -0.307ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.307ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - L4 0.000 0.000 r dip_sw[19] (IN) - net (fo=0) 0.000 0.000 dip_sw[19] - L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O - net (fo=1, routed) 4.009 4.255 u_confreg/dip_sw_IBUF[19] - SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.045 4.300 r u_confreg/s_rdata[19]_i_4/O - net (fo=1, routed) 0.051 4.351 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 - SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.045 4.396 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O - net (fo=1, routed) 0.000 4.396 u_confreg/u_int_ctrl_n_12 - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D + R5 0.000 0.000 r dip_sw[28] (IN) + net (fo=0) 0.000 0.000 dip_sw[28] + R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O + net (fo=1, routed) 3.990 4.226 u_confreg/dip_sw_IBUF[28] + SLICE_X12Y58 LUT5 (Prop_lut5_I4_O) 0.045 4.271 r u_confreg/s_rdata[28]_i_4/O + net (fo=1, routed) 0.508 4.779 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 + SLICE_X3Y58 LUT6 (Prop_lut6_I4_O) 0.045 4.824 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O + net (fo=1, routed) 0.000 4.824 u_confreg/u_int_ctrl_n_3 + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -31971,8 +19875,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C + net (fo=35652, routed) 1.001 -0.307 u_confreg/sys_clk + SLICE_X3Y58 FDRE r u_confreg/s_rdata_reg[28]/C Slack: inf Source: dip_sw[25] @@ -31981,10 +19885,10 @@ Slack: inf (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) Path Group: (none) Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.440ns (logic 0.347ns (7.817%) route 4.093ns (92.183%)) + Data Path Delay: 5.158ns (logic 0.347ns (6.729%) route 4.811ns (93.271%)) Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns + Clock Path Skew: -0.309ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): -0.309ns Source Clock Delay (SCD): 0.000ns Clock Pessimism Removal (CPR): -0.000ns @@ -31993,12 +19897,12 @@ Slack: inf R3 0.000 0.000 r dip_sw[25] (IN) net (fo=0) 0.000 0.000 dip_sw[25] R3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[25]_inst/O - net (fo=1, routed) 3.854 4.111 u_confreg/dip_sw_IBUF[25] - SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.045 4.156 r u_confreg/s_rdata[25]_i_4/O - net (fo=1, routed) 0.239 4.395 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.440 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O - net (fo=1, routed) 0.000 4.440 u_confreg/u_int_ctrl_n_6 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D + net (fo=1, routed) 4.470 4.727 u_confreg/dip_sw_IBUF[25] + SLICE_X1Y60 LUT5 (Prop_lut5_I4_O) 0.045 4.772 r u_confreg/s_rdata[25]_i_4/O + net (fo=1, routed) 0.341 5.113 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 + SLICE_X5Y58 LUT6 (Prop_lut6_I4_O) 0.045 5.158 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O + net (fo=1, routed) 0.000 5.158 u_confreg/u_int_ctrl_n_6 + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/D ------------------------------------------------------------------- ------------------- (clock sys_clk rise edge) 0.000 0.000 r @@ -32010,203 +19914,8 @@ Slack: inf -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C - -Slack: inf - Source: dip_sw[11] - (input port) - Destination: u_confreg/s_rdata_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.518ns (logic 0.329ns (7.286%) route 4.189ns (92.714%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L7 0.000 0.000 r dip_sw[11] (IN) - net (fo=0) 0.000 0.000 dip_sw[11] - L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O - net (fo=1, routed) 3.969 4.208 u_confreg/dip_sw_IBUF[11] - SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.045 4.253 r u_confreg/s_rdata[11]_i_4/O - net (fo=1, routed) 0.220 4.473 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 4.518 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O - net (fo=1, routed) 0.000 4.518 u_confreg/u_int_ctrl_n_20 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C - -Slack: inf - Source: dip_sw[13] - (input port) - Destination: u_confreg/s_rdata_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.727ns (logic 0.344ns (7.270%) route 4.383ns (92.730%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K3 0.000 0.000 r dip_sw[13] (IN) - net (fo=0) 0.000 0.000 dip_sw[13] - K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O - net (fo=1, routed) 4.162 4.416 u_confreg/dip_sw_IBUF[13] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.461 r u_confreg/s_rdata[13]_i_4/O - net (fo=1, routed) 0.221 4.682 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.727 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O - net (fo=1, routed) 0.000 4.727 u_confreg/u_int_ctrl_n_18 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C - -Slack: inf - Source: dip_sw[1] - (input port) - Destination: u_confreg/s_rdata_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.729ns (logic 0.355ns (7.516%) route 4.374ns (92.484%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J3 0.000 0.000 r dip_sw[1] (IN) - net (fo=0) 0.000 0.000 dip_sw[1] - J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O - net (fo=1, routed) 3.965 4.231 u_confreg/dip_sw_IBUF[1] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.276 r u_confreg/s_rdata[1]_i_4/O - net (fo=1, routed) 0.409 4.684 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 4.729 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O - net (fo=1, routed) 0.000 4.729 u_confreg/u_int_ctrl_n_30 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C - -Slack: inf - Source: dip_sw[20] - (input port) - Destination: u_confreg/s_rdata_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.977ns (logic 0.333ns (6.690%) route 4.644ns (93.310%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M4 0.000 0.000 r dip_sw[20] (IN) - net (fo=0) 0.000 0.000 dip_sw[20] - M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O - net (fo=1, routed) 4.258 4.501 u_confreg/dip_sw_IBUF[20] - SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.546 r u_confreg/s_rdata[20]_i_4/O - net (fo=1, routed) 0.386 4.932 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 4.977 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O - net (fo=1, routed) 0.000 4.977 u_confreg/u_int_ctrl_n_11 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C - -Slack: inf - Source: dip_sw[8] - (input port) - Destination: u_confreg/s_rdata_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 5.044ns (logic 0.334ns (6.614%) route 4.711ns (93.386%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.319ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M6 0.000 0.000 r dip_sw[8] (IN) - net (fo=0) 0.000 0.000 dip_sw[8] - M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O - net (fo=1, routed) 4.491 4.735 u_confreg/dip_sw_IBUF[8] - SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.045 4.780 r u_confreg/s_rdata[8]_i_4/O - net (fo=1, routed) 0.220 4.999 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 5.044 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O - net (fo=1, routed) 0.000 5.044 u_confreg/u_int_ctrl_n_23 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C + net (fo=35652, routed) 0.999 -0.309 u_confreg/sys_clk + SLICE_X5Y58 FDRE r u_confreg/s_rdata_reg[25]/C diff --git a/fpga/vivado_reports_nodsp/utilization.rpt b/fpga/vivado_reports_nodsp/utilization.rpt index ad58480..c0d4e8f 100644 --- a/fpga/vivado_reports_nodsp/utilization.rpt +++ b/fpga/vivado_reports_nodsp/utilization.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 +| Date : Fri Jul 10 04:14:47 2026 | Host : fedora running 64-bit unknown -| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt +| Command : report_utilization -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization.rpt | Design : soc_top | Device : 7a200tfbg676-1 | Design State : Routed ------------------------------------------------------------------------------------------------- +-------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -31,16 +31,16 @@ Table of Contents +----------------------------+-------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+-------+-------+-----------+-------+ -| Slice LUTs | 60995 | 0 | 133800 | 45.59 | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | +| Slice LUTs | 71196 | 0 | 133800 | 53.21 | +| LUT as Logic | 69453 | 0 | 133800 | 51.91 | +| LUT as Memory | 1743 | 0 | 46200 | 3.77 | +| LUT as Distributed RAM | 628 | 0 | | | | LUT as Shift Register | 1115 | 0 | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 | +| Slice Registers | 39690 | 0 | 267600 | 14.83 | +| Register as Flip Flop | 39690 | 0 | 267600 | 14.83 | | Register as Latch | 0 | 0 | 267600 | 0.00 | -| F7 Muxes | 4480 | 0 | 66900 | 6.70 | -| F8 Muxes | 1556 | 0 | 33450 | 4.65 | +| F7 Muxes | 4565 | 0 | 66900 | 6.82 | +| F8 Muxes | 1520 | 0 | 33450 | 4.54 | +----------------------------+-------+-------+-----------+-------+ @@ -57,9 +57,9 @@ Table of Contents | 0 | _ | Reset | - | | 0 | Yes | - | - | | 24 | Yes | - | Set | -| 26637 | Yes | - | Reset | +| 26562 | Yes | - | Reset | | 139 | Yes | Set | - | -| 13131 | Yes | Reset | - | +| 12965 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -69,28 +69,28 @@ Table of Contents +--------------------------------------------+-------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +--------------------------------------------+-------+-------+-----------+-------+ -| Slice | 20066 | 0 | 33450 | 59.99 | -| SLICEL | 13210 | 0 | | | -| SLICEM | 6856 | 0 | | | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | +| Slice | 21289 | 0 | 33450 | 63.64 | +| SLICEL | 13965 | 0 | | | +| SLICEM | 7324 | 0 | | | +| LUT as Logic | 69453 | 0 | 133800 | 51.91 | | using O5 output only | 2 | | | | -| using O6 output only | 49931 | | | | -| using O5 and O6 | 9207 | | | | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | +| using O6 output only | 57661 | | | | +| using O5 and O6 | 11790 | | | | +| LUT as Memory | 1743 | 0 | 46200 | 3.77 | +| LUT as Distributed RAM | 628 | 0 | | | | using O5 output only | 0 | | | | | using O6 output only | 60 | | | | -| using O5 and O6 | 680 | | | | +| using O5 and O6 | 568 | | | | | LUT as Shift Register | 1115 | 0 | | | | using O5 output only | 47 | | | | | using O6 output only | 1008 | | | | | using O5 and O6 | 60 | | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register driven from within the Slice | 20433 | | | | -| Register driven from outside the Slice | 19498 | | | | -| LUT in front of the register is unused | 10788 | | | | -| LUT in front of the register is used | 8710 | | | | -| Unique Control Sets | 1304 | | 33450 | 3.90 | +| Slice Registers | 39690 | 0 | 267600 | 14.83 | +| Register driven from within the Slice | 24917 | | | | +| Register driven from outside the Slice | 14773 | | | | +| LUT in front of the register is unused | 6243 | | | | +| LUT in front of the register is used | 8530 | | | | +| Unique Control Sets | 1278 | | 33450 | 3.82 | +--------------------------------------------+-------+-------+-----------+-------+ * Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. @@ -101,9 +101,9 @@ Table of Contents +-------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 23.5 | 0 | 365 | 6.44 | -| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 | -| RAMB36E1 only | 8 | | | | +| Block RAM Tile | 25.5 | 0 | 365 | 6.99 | +| RAMB36/FIFO* | 10 | 0 | 365 | 2.74 | +| RAMB36E1 only | 10 | | | | | RAMB18 | 31 | 0 | 730 | 4.25 | | RAMB18E1 only | 31 | | | | +-------------------+------+-------+-----------+-------+ @@ -113,12 +113,11 @@ Table of Contents 4. DSP ------ -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| DSPs | 16 | 0 | 740 | 2.16 | -| DSP48E1 only | 16 | | | | -+----------------+------+-------+-----------+-------+ ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 740 | 0.00 | ++-----------+------+-------+-----------+-------+ 5. IO and GT Specific @@ -154,7 +153,7 @@ Table of Contents +------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ -| BUFGCTRL | 4 | 0 | 32 | 12.50 | +| BUFGCTRL | 3 | 0 | 32 | 9.38 | | BUFIO | 0 | 0 | 40 | 0.00 | | MMCME2_ADV | 0 | 0 | 10 | 0.00 | | PLLE2_ADV | 1 | 0 | 10 | 10.00 | @@ -188,20 +187,20 @@ Table of Contents +-----------+-------+---------------------+ | Ref Name | Used | Functional Category | +-----------+-------+---------------------+ -| LUT6 | 35413 | LUT | -| FDCE | 26637 | Flop & Latch | -| FDRE | 13131 | Flop & Latch | -| LUT3 | 9384 | LUT | -| LUT5 | 8477 | LUT | -| LUT4 | 7294 | LUT | -| LUT2 | 6978 | LUT | -| MUXF7 | 4480 | MuxFx | -| CARRY4 | 2859 | CarryLogic | -| MUXF8 | 1556 | MuxFx | -| RAMD32 | 1060 | Distributed Memory | +| LUT6 | 37981 | LUT | +| FDCE | 26562 | Flop & Latch | +| FDRE | 12965 | Flop & Latch | +| LUT5 | 12781 | LUT | +| LUT4 | 10316 | LUT | +| LUT3 | 10135 | LUT | +| LUT2 | 9228 | LUT | +| MUXF7 | 4565 | MuxFx | +| CARRY4 | 3546 | CarryLogic | +| MUXF8 | 1520 | MuxFx | | SRLC32E | 992 | Distributed Memory | -| LUT1 | 801 | LUT | -| RAMS32 | 328 | Distributed Memory | +| RAMD32 | 892 | Distributed Memory | +| LUT1 | 802 | LUT | +| RAMS32 | 272 | Distributed Memory | | SRL16E | 183 | Distributed Memory | | FDSE | 139 | Flop & Latch | | IBUF | 104 | IO | @@ -210,9 +209,8 @@ Table of Contents | RAMD64E | 32 | Distributed Memory | | RAMB18E1 | 31 | Block Memory | | FDPE | 24 | Flop & Latch | -| DSP48E1 | 16 | Block Arithmetic | -| RAMB36E1 | 8 | Block Memory | -| BUFG | 4 | Clock | +| RAMB36E1 | 10 | Block Memory | +| BUFG | 3 | Clock | | PLLE2_ADV | 1 | Clock | +-----------+-------+---------------------+ diff --git a/fpga/vivado_reports_nodsp/utilization_hier.rpt b/fpga/vivado_reports_nodsp/utilization_hier.rpt index 9abba2a..aaf85f8 100644 --- a/fpga/vivado_reports_nodsp/utilization_hier.rpt +++ b/fpga/vivado_reports_nodsp/utilization_hier.rpt @@ -1,13 +1,13 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:06 2026 +| Date : Fri Jul 10 04:14:48 2026 | Host : fedora running 64-bit unknown -| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt +| Command : report_utilization -hierarchical -file /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/vivado_reports_nodsp/utilization_hier.rpt | Design : soc_top | Device : 7a200tfbg676-1 | Design State : Routed -------------------------------------------------------------------------------------------------------------------- +--------------------------------------------------------------------------------------------------------------------------------------------------------- Utilization Design Information @@ -21,255 +21,232 @@ Table of Contents +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks | +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -| soc_top | (top) | 60995 | 59140 | 740 | 1115 | 39931 | 8 | 31 | 16 | -| (soc_top) | (top) | 878 | 822 | 56 | 0 | 4 | 0 | 0 | 0 | +| soc_top | (top) | 71196 | 69453 | 628 | 1115 | 39690 | 10 | 31 | 0 | +| (soc_top) | (top) | 868 | 812 | 56 | 0 | 4 | 0 | 0 | 0 | | pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| inst | clk_pll_clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 459 | 459 | 0 | 0 | 151 | 0 | 0 | 0 | -| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 | +| pll_clk.u_rst_sys | rst_sync_0 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | +| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 357 | 357 | 0 | 0 | 151 | 0 | 0 | 0 | +| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 19 | 19 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_64 | 19 | 19 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_47 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_63 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_48 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_62 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_49 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_61 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 30 | 30 | 0 | 0 | 11 | 0 | 0 | 0 | | (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_58 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_59 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_60 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_55 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_56 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_57 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 26 | 26 | 0 | 0 | 11 | 0 | 0 | 0 | | (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7_52 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_53 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3_54 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | +| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 27 | 27 | 0 | 0 | 11 | 0 | 0 | 0 | | (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 | -| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 | -| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 | -| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 | -| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 133 | 133 | 0 | 0 | 17 | 0 | 0 | 0 | -| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 | +| cmdArbiter | StreamArbiter_7 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | +| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| fifo | StreamFifo_3 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | +| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 89 | 89 | 0 | 0 | 25 | 0 | 0 | 0 | +| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 73 | 73 | 0 | 0 | 12 | 0 | 0 | 0 | +| errorSlave | Axi4ReadOnlyErrorSlave_1_51 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | +| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | +| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | +| errorSlave | Axi4WriteOnlyErrorSlave_1_50 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 | +| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 55 | 55 | 0 | 0 | 17 | 0 | 0 | 0 | +| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 41 | 41 | 0 | 0 | 8 | 0 | 0 | 0 | | errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 | +| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 23 | 23 | 0 | 0 | 14 | 0 | 0 | 0 | | (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_Axi_CDC | Axi_CDC | 410 | 282 | 128 | 0 | 317 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3_48 | 181 | 145 | 36 | 0 | 77 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3_48 | 176 | 140 | 36 | 0 | 65 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC_49 | 103 | 67 | 36 | 0 | 79 | 0 | 0 | 0 | -| (awFifo) | StreamFifoCC_49 | 99 | 63 | 36 | 0 | 65 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| bFifo | StreamFifoCC_2_50 | 15 | 15 | 0 | 0 | 26 | 0 | 0 | 0 | -| (bFifo) | StreamFifoCC_2_50 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 1073 | 1073 | 0 | 0 | 173 | 0 | 0 | 0 | -| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 498 | 498 | 0 | 0 | 85 | 0 | 0 | 0 | -| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 | -| u_axi_dvi | axi_dvi | 283 | 283 | 0 | 0 | 211 | 0 | 0 | 0 | -| u_axi_ram | axi_wrap_ram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | -| u_axi_sram_sp | axi2sram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | +| errorSlave | Axi4WriteOnlyErrorSlave_1 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | +| u_Axi_CDC | Axi_CDC | 407 | 279 | 128 | 0 | 309 | 0 | 0 | 0 | +| arFifo | StreamFifoCC_3 | 180 | 144 | 36 | 0 | 73 | 0 | 0 | 0 | +| (arFifo) | StreamFifoCC_3 | 174 | 138 | 36 | 0 | 61 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9_45 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11_46 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | +| awFifo | StreamFifoCC | 101 | 65 | 36 | 0 | 75 | 0 | 0 | 0 | +| (awFifo) | StreamFifoCC | 94 | 58 | 36 | 0 | 61 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_9 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| bFifo | StreamFifoCC_2 | 14 | 14 | 0 | 0 | 26 | 0 | 0 | 0 | +| (bFifo) | StreamFifoCC_2 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | +| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_4 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_6 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | +| rFifo | StreamFifoCC_4 | 46 | 18 | 28 | 0 | 66 | 0 | 0 | 0 | +| (rFifo) | StreamFifoCC_4 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_1 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| wFifo | StreamFifoCC_1 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 | +| (wFifo) | StreamFifoCC_1 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 | +| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | +| pushToPopGray_buffercc | BufferCC_8 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| u_axi_axil_adapter | axi_axil_adapter | 1338 | 1338 | 0 | 0 | 161 | 0 | 0 | 0 | +| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 635 | 635 | 0 | 0 | 81 | 0 | 0 | 0 | +| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 703 | 703 | 0 | 0 | 80 | 0 | 0 | 0 | +| u_axi_dvi | axi_dvi | 284 | 284 | 0 | 0 | 211 | 0 | 0 | 0 | +| u_axi_ram | axi_wrap_ram_sp_external | 354 | 354 | 0 | 0 | 78 | 0 | 0 | 0 | +| u_axi_sram_sp | axi2sram_sp_external | 354 | 354 | 0 | 0 | 78 | 0 | 0 | 0 | | u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 | -| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 | -| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | -| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | -| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 | +| AA_axi2apb_bridge_cpu | axi2apb_bridge | 250 | 250 | 0 | 0 | 120 | 0 | 0 | 0 | +| uart0 | UART_TOP | 433 | 417 | 16 | 0 | 337 | 0 | 0 | 0 | +| regs | uart_regs | 433 | 417 | 16 | 0 | 337 | 0 | 0 | 0 | +| (regs) | uart_regs | 118 | 118 | 0 | 0 | 155 | 0 | 0 | 0 | | i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 | | (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 | | fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 | | (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 | -| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | +| rfifo | raminfr_44 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | | transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 | | (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 | | fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 | | (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 | | tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 251 | 251 | 0 | 0 | 578 | 0 | 0 | 0 | +| u_cdma_matmul_bridge | cdma_matmul_bridge | 247 | 247 | 0 | 0 | 578 | 0 | 0 | 0 | | u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 | | (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 | | u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 | | u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 | -| u_cpu | core_top | 8551 | 8299 | 252 | 0 | 5591 | 0 | 20 | 0 | +| u_cpu | core_top | 8553 | 8301 | 252 | 0 | 5591 | 0 | 20 | 0 | | (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 | -| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 | +| addr_trans | addr_trans | 2249 | 2109 | 140 | 0 | 1244 | 0 | 0 | 0 | | (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 | -| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 | -| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 | +| tlb_entry | tlb_entry | 2249 | 2109 | 140 | 0 | 1204 | 0 | 0 | 0 | +| axi_bridge | axi_bridge | 39 | 39 | 0 | 0 | 214 | 0 | 0 | 0 | | btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 | -| (btb) | btb | 1044 | 964 | 80 | 0 | 1611 | 0 | 0 | 0 | +| (btb) | btb | 1043 | 963 | 80 | 0 | 1611 | 0 | 0 | 0 | | dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | -| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 | +| dcache | dcache | 553 | 521 | 32 | 0 | 146 | 0 | 10 | 0 | | (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 | -| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 | -| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_46 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 | -| exe_stage | exe_stage | 663 | 663 | 0 | 0 | 233 | 0 | 0 | 0 | -| (exe_stage) | exe_stage | 632 | 632 | 0 | 0 | 233 | 0 | 0 | 0 | +| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_33 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_34 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_35 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_36 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_39 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_40 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 | +| lfsr | lfsr_41 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | +| tagv_ram_way[0].u | tagv_sram_42 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 | +| tagv_ram_way[1].u | tagv_sram_43 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 | +| exe_stage | exe_stage | 664 | 664 | 0 | 0 | 233 | 0 | 0 | 0 | +| (exe_stage) | exe_stage | 633 | 633 | 0 | 0 | 233 | 0 | 0 | 0 | | u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | | icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 | | (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 | | data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_25 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_26 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_27 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_29 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_30 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | +| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_31 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | | lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_35 | 87 | 87 | 0 | 0 | 0 | 0 | 1 | 0 | -| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 | -| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 | -| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 | +| tagv_ram_way[1].u | tagv_sram_32 | 88 | 88 | 0 | 0 | 0 | 0 | 1 | 0 | +| id_stage | id_stage | 1050 | 1050 | 0 | 0 | 108 | 0 | 0 | 0 | +| if_stage | if_stage | 134 | 134 | 0 | 0 | 173 | 0 | 0 | 0 | +| mem_stage | mem_stage | 117 | 117 | 0 | 0 | 211 | 0 | 0 | 0 | | u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 | | u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 | -| u_mul | mul | 936 | 936 | 0 | 0 | 592 | 0 | 0 | 0 | -| wb_stage | wb_stage | 680 | 680 | 0 | 0 | 233 | 0 | 0 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 36148 | 34927 | 112 | 1109 | 27165 | 8 | 10 | 16 | -| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| u_fft_controller | fft_controller | 2646 | 1606 | 0 | 1040 | 1083 | 6 | 4 | 16 | -| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 | -| u_FFT | FFT | 2496 | 1456 | 0 | 1040 | 983 | 6 | 0 | 16 | -| SU1 | SdfUnit | 1071 | 303 | 0 | 768 | 197 | 2 | 0 | 4 | -| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_25 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 | -| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 | -| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| u_mul | mul | 934 | 934 | 0 | 0 | 592 | 0 | 0 | 0 | +| wb_stage | wb_stage | 681 | 681 | 0 | 0 | 233 | 0 | 0 | 0 | +| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 45975 | 44866 | 0 | 1109 | 26955 | 10 | 10 | 0 | +| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | +| u_fft_controller | fft_controller | 6949 | 5909 | 0 | 1040 | 1083 | 8 | 4 | 0 | +| (u_fft_controller) | fft_controller | 118 | 118 | 0 | 0 | 100 | 0 | 0 | 0 | +| u_FFT | FFT | 6783 | 5743 | 0 | 1040 | 983 | 8 | 0 | 0 | +| SU1 | SdfUnit | 2145 | 1377 | 0 | 768 | 197 | 2 | 0 | 0 | +| (SU1) | SdfUnit | 39 | 39 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_21 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | +| DB1 | DelayBuffer | 624 | 112 | 0 | 512 | 32 | 0 | 0 | 0 | +| DB2 | DelayBuffer__parameterized0 | 320 | 64 | 0 | 256 | 32 | 0 | 0 | 0 | +| MU | Multiply_23 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle_24 | 543 | 543 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU2 | SdfUnit__parameterized0 | 1566 | 1374 | 0 | 192 | 197 | 2 | 0 | 0 | +| (SU2) | SdfUnit__parameterized0 | 38 | 38 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_18 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 | -| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU3 | SdfUnit__parameterized1 | 346 | 298 | 0 | 48 | 197 | 0 | 0 | 4 | -| (SU3) | SdfUnit__parameterized1 | 74 | 74 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| MU | Multiply_19 | 611 | 611 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle_20 | 541 | 541 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU3 | SdfUnit__parameterized1 | 1416 | 1368 | 0 | 48 | 197 | 2 | 0 | 0 | +| (SU3) | SdfUnit__parameterized1 | 35 | 35 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_13 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_14 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 | -| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| MU | Multiply_15 | 610 | 610 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle_16 | 539 | 539 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU4 | SdfUnit__parameterized2 | 1398 | 1366 | 0 | 32 | 197 | 2 | 0 | 0 | +| (SU4) | SdfUnit__parameterized2 | 34 | 34 | 0 | 0 | 133 | 0 | 0 | 0 | +| BF1 | Butterfly_11 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0_12 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 | -| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 | +| MU | Multiply | 612 | 612 | 0 | 0 | 0 | 0 | 0 | 0 | +| TW | Twiddle | 536 | 536 | 0 | 0 | 0 | 2 | 0 | 0 | +| SU5 | SdfUnit__parameterized3 | 258 | 258 | 0 | 0 | 195 | 0 | 0 | 0 | +| (SU5) | SdfUnit__parameterized3 | 34 | 34 | 0 | 0 | 99 | 0 | 0 | 0 | | BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| BF2 | Butterfly__parameterized0 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 | | DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | | u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_mlkem_axi_cdc | Axi_CDC_5 | 421 | 309 | 112 | 0 | 272 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3 | 53 | 25 | 28 | 0 | 55 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3 | 44 | 16 | 28 | 0 | 43 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 | -| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 | -| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4 | 57 | 29 | 28 | 0 | 72 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1 | 253 | 225 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1 | 248 | 220 | 28 | 0 | 53 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_mlkem_axi_slave | mlkem_axi_slave | 33082 | 33013 | 0 | 69 | 25804 | 2 | 6 | 0 | -| (u_mlkem_axi_slave) | mlkem_axi_slave | 1202 | 1202 | 0 | 0 | 1068 | 0 | 0 | 0 | -| u_mlkem | mlkem_top | 31884 | 31815 | 0 | 69 | 24736 | 2 | 6 | 0 | -| (u_mlkem) | mlkem_top | 2738 | 2738 | 0 | 0 | 4960 | 0 | 0 | 0 | -| u_bank_a | sd_bram__parameterized0 | 50 | 50 | 0 | 0 | 0 | 1 | 1 | 0 | +| u_in1 | my_bram0_8 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_out0 | my_bram0_9 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_out1 | my_bram0_10 | 45 | 45 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_mlkem_axi_slave | mlkem_axi_slave | 39029 | 38960 | 0 | 69 | 25868 | 2 | 6 | 0 | +| (u_mlkem_axi_slave) | mlkem_axi_slave | 1332 | 1332 | 0 | 0 | 1060 | 0 | 0 | 0 | +| u_mlkem | mlkem_top | 37700 | 37631 | 0 | 69 | 24808 | 2 | 6 | 0 | +| (u_mlkem) | mlkem_top | 2754 | 2754 | 0 | 0 | 4949 | 0 | 0 | 0 | +| u_bank_a | sd_bram__parameterized0 | 51 | 51 | 0 | 0 | 0 | 1 | 1 | 0 | | u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 | -| u_bank_t | sd_bram__parameterized2 | 654 | 654 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_bank_t | sd_bram__parameterized2 | 683 | 683 | 0 | 0 | 0 | 0 | 1 | 0 | | u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_cbd | sample_cbd_sync_shared | 2741 | 2741 | 0 | 0 | 3186 | 0 | 0 | 0 | -| u_comp | comp_decomp_sync | 467 | 466 | 0 | 1 | 323 | 0 | 0 | 0 | -| u_ct_bram | sd_bram_6 | 13 | 13 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_dkp_bram | sd_bram_7 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_ek_bram | sd_bram_8 | 2121 | 2121 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_keccak | keccak_core | 5274 | 5274 | 0 | 0 | 1606 | 0 | 0 | 0 | -| u_ntt | ntt_core | 8625 | 8582 | 0 | 43 | 3861 | 0 | 0 | 0 | -| (u_ntt) | ntt_core | 6101 | 6085 | 0 | 16 | 3358 | 0 | 0 | 0 | -| u_bf | butterfly_unit_pipe | 2260 | 2234 | 0 | 26 | 286 | 0 | 0 | 0 | -| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 | -| u_barrett | barrett_mul_pipe_9 | 2192 | 2191 | 0 | 1 | 211 | 0 | 0 | 0 | -| u_scl | barrett_mul_pipe | 265 | 264 | 0 | 1 | 217 | 0 | 0 | 0 | -| u_pmul | poly_mul_sync | 3881 | 3856 | 0 | 25 | 6743 | 0 | 0 | 0 | -| (u_pmul) | poly_mul_sync | 2434 | 2434 | 0 | 0 | 6280 | 0 | 0 | 0 | +| u_cbd | sample_cbd_sync_shared | 2753 | 2753 | 0 | 0 | 3186 | 0 | 0 | 0 | +| u_comp | comp_decomp_sync | 465 | 464 | 0 | 1 | 323 | 0 | 0 | 0 | +| u_ct_bram | sd_bram_4 | 12 | 12 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_dkp_bram | sd_bram_5 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_ek_bram | sd_bram_6 | 2006 | 2006 | 0 | 0 | 0 | 0 | 1 | 0 | +| u_keccak | keccak_core | 5271 | 5271 | 0 | 0 | 1606 | 0 | 0 | 0 | +| u_ntt | ntt_core | 9893 | 9850 | 0 | 43 | 3869 | 0 | 0 | 0 | +| (u_ntt) | ntt_core | 7376 | 7360 | 0 | 16 | 3366 | 0 | 0 | 0 | +| u_bf | butterfly_unit_pipe | 2256 | 2230 | 0 | 26 | 286 | 0 | 0 | 0 | +| (u_bf) | butterfly_unit_pipe | 58 | 33 | 0 | 25 | 75 | 0 | 0 | 0 | +| u_barrett | barrett_mul_pipe_7 | 2198 | 2197 | 0 | 1 | 211 | 0 | 0 | 0 | +| u_scl | barrett_mul_pipe | 263 | 262 | 0 | 1 | 217 | 0 | 0 | 0 | +| u_pmul | poly_mul_sync | 8281 | 8256 | 0 | 25 | 6818 | 0 | 0 | 0 | +| (u_pmul) | poly_mul_sync | 6834 | 6834 | 0 | 0 | 6355 | 0 | 0 | 0 | | u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 | -| u_sha3 | sha3_top_shared | 1766 | 1766 | 0 | 0 | 2388 | 0 | 0 | 0 | -| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 9758 | 9576 | 176 | 6 | 3248 | 0 | 0 | 0 | -| (u_matmul_axi_slave) | matmul_axi_slave | 5637 | 5455 | 176 | 6 | 2480 | 0 | 0 | 0 | -| mult_inst[0].u_mult | pipelined_mult_32x32 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1788 | 1788 | 0 | 0 | 1476 | 0 | 1 | 0 | -| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 751 | 751 | 0 | 0 | 1180 | 0 | 0 | 0 | -| u_core_engine | snix_axi_mm2mm | 1038 | 1038 | 0 | 0 | 296 | 0 | 1 | 0 | -| (u_core_engine) | snix_axi_mm2mm | 762 | 762 | 0 | 0 | 243 | 0 | 0 | 0 | -| axis_fifo_u0 | snix_axis_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | -| u_fifo | snix_sync_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | +| u_sha3 | sha3_top_shared | 1975 | 1975 | 0 | 0 | 2388 | 0 | 0 | 0 | +| u_snt | sample_ntt_sync_shared | 2108 | 2108 | 0 | 0 | 1669 | 0 | 0 | 0 | +| u_matmul_axi_slave | matmul_axi_slave | 10204 | 10022 | 176 | 6 | 3239 | 0 | 0 | 0 | +| (u_matmul_axi_slave) | matmul_axi_slave | 6085 | 5903 | 176 | 6 | 2471 | 0 | 0 | 0 | +| mult_inst[0].u_mult | pipelined_mult_32x32 | 1061 | 1061 | 0 | 0 | 192 | 0 | 0 | 0 | +| mult_inst[1].u_mult | pipelined_mult_32x32_1 | 998 | 998 | 0 | 0 | 192 | 0 | 0 | 0 | +| mult_inst[2].u_mult | pipelined_mult_32x32_2 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 | +| mult_inst[3].u_mult | pipelined_mult_32x32_3 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 | +| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1558 | 1558 | 0 | 0 | 1476 | 0 | 1 | 0 | +| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 587 | 587 | 0 | 0 | 1180 | 0 | 0 | 0 | +| u_core_engine | snix_axi_mm2mm | 974 | 974 | 0 | 0 | 296 | 0 | 1 | 0 | +| (u_core_engine) | snix_axi_mm2mm | 700 | 700 | 0 | 0 | 243 | 0 | 0 | 0 | +| axis_fifo_u0 | snix_axis_fifo | 274 | 274 | 0 | 0 | 53 | 0 | 1 | 0 | +| u_fifo | snix_sync_fifo | 274 | 274 | 0 | 0 | 53 | 0 | 1 | 0 | +------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ * Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt deleted file mode 100644 index a8a58a3..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clock_interaction.rpt +++ /dev/null @@ -1,28 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_clock_interaction -file /home/fallensigh/vivado_reports_nodsp/clock_interaction.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------- - -Clock Interaction Report - -Clock Interaction Table ------------------------ - - WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock -From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints ------------------ ----------------- ----------- ------- ------- ----------- ----------- --------------- ------------------- ------------------- -cpu_clk cpu_clk rise - rise 2.72 0.00 0 17264 30.32 Clean Timed -cpu_clk sys_clk 0 162 Ignored Asynchronous Groups -mlkem_clk_clk_pll mlkem_clk_clk_pll rise - rise 10.81 0.00 0 74168 40.00 Clean Timed -mlkem_clk_clk_pll sys_clk rise - rise 11.25 0.00 0 61 20.00 Clean Timed -sys_clk cpu_clk 0 59 Ignored Asynchronous Groups -sys_clk mlkem_clk_clk_pll rise - rise 9.16 0.00 0 112 20.00 Clean Timed -sys_clk sys_clk rise - rise 0.17 0.00 0 23704 20.00 Clean Timed - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt deleted file mode 100644 index 7ce6dda..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/clocks.rpt +++ /dev/null @@ -1,76 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_clocks -file /home/fallensigh/vivado_reports_nodsp/clocks.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------- - -Clock Report - - -Attributes - P: Propagated - G: Generated - A: Auto-derived - R: Renamed - V: Virtual - I: Inverted - S: Pin phase-shifted with Latency mode - -Clock Period(ns) Waveform(ns) Attributes Sources -clk 20.000 {0.000 10.000} P {clk} -clkfbout_clk_pll 20.000 {0.000 10.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} -cpu_clk 30.323 {0.000 15.161} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} -mlkem_clk_clk_pll 40.000 {0.000 20.000} P,G,A {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} -sys_clk 20.000 {0.000 10.000} P,G,A,R {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} - - -==================================================== -Generated Clocks -==================================================== - -Generated Clock : clkfbout_clk_pll -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Multiply By : 1 -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT} - -Generated Clock : cpu_clk -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Edges : {1 2 3} -Edge Shifts(ns) : {0.000 5.161 10.323} -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0} - -Generated Clock : mlkem_clk_clk_pll -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Edges : {1 2 3} -Edge Shifts(ns) : {0.000 10.000 20.000} -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2} - -Generated Clock : sys_clk -Master Source : pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Master Clock : clk -Multiply By : 1 -Generated Sources : {pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1} - - - -==================================================== -User Uncertainty -==================================================== - - - -==================================================== -User Jitter -==================================================== - -Clock Jitter(ns) -clk 0.200 - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt deleted file mode 100644 index 441963e..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_complexity.rpt +++ /dev/null @@ -1,37 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:35:00 2026 -| Host : fedora running 64-bit unknown -| Command : report_design_analysis -complexity -file /home/fallensigh/vivado_reports_nodsp/design_analysis_complexity.rpt -| Design : soc_top -| Device : xc7a200t -| Design State : Routed -------------------------------------------------------------------------------------------------------------------------------- - -Report Design Analysis - -Table of Contents ------------------ -1. Complexity Characteristics (Cells) - -1. Complexity Characteristics (Cells) -------------------------------------- - -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| Instance | Module | Rent | Average Fanout | Total Instances | LUT1 | LUT2 | LUT3 | LUT4 | LUT5 | LUT6 | Memory LUT | DSP | RAMB | MUXF | URAM | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -| (top) | soc_top | 0.34 | 3.77 | 118528 | 801(1.2%) | 6978(10.2%) | 9384(13.7%) | 7294(10.7%) | 8477(12.4%) | 35413(51.8%) | 1175 | 16 | 39 | 6020 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 0.50 | 5.92 | 1309 | 0(0.0%) | 8(0.7%) | 43(3.8%) | 100(8.9%) | 200(17.7%) | 776(68.9%) | 0 | 0 | 0 | 0 | 0 | -| u_axi_uart_controller | axi_uart_controller | 0.55 | 3.54 | 1296 | 10(1.2%) | 84(10.4%) | 80(9.9%) | 144(17.9%) | 194(24.1%) | 293(36.4%) | 0 | 0 | 0 | 9 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 0.46 | 2.22 | 1002 | 1(0.3%) | 65(17.1%) | 39(10.3%) | 174(45.8%) | 13(3.4%) | 88(23.2%) | 0 | 0 | 0 | 0 | 0 | -| u_cpu | core_top | 0.56 | 3.96 | 15822 | 168(1.8%) | 579(6.3%) | 1029(11.1%) | 871(9.4%) | 1744(18.9%) | 4860(52.5%) | 0 | 0 | 20 | 276 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 0.56 | 3.75 | 74954 | 362(0.9%) | 3923(9.7%) | 6649(16.4%) | 4109(10.2%) | 4490(11.1%) | 20899(51.7%) | 1169 | 16 | 18 | 5286 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 0.63 | 3.76 | 15159 | 18(0.2%) | 1646(15.2%) | 357(3.3%) | 830(7.6%) | 974(9.0%) | 7026(64.7%) | 6 | 0 | 0 | 413 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 0.36 | 3.45 | 3680 | 136(6.5%) | 181(8.6%) | 405(19.3%) | 255(12.2%) | 342(16.3%) | 776(37.0%) | 0 | 0 | 1 | 4 | 0 | -+---------------------------+---------------------+------+----------------+-----------------+-----------+-------------+-------------+-------------+-------------+--------------+------------+-----+------+------+------+ -* Complexity Ranges -** 0.0 - 0.3 -> Very Low, 0.3 - 0.5 -> low, 0.5 - 0.65 -> normal, 0.65 - 0.85 -> high, 0.85 - 1.0 -> very high -*** -* -> Not computable as cell size is very small - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt deleted file mode 100644 index 6e7bf34..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/design_analysis_timing.rpt +++ /dev/null @@ -1,52 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:29 2026 -| Host : fedora running 64-bit unknown -| Command : report_design_analysis -timing -file /home/fallensigh/vivado_reports_nodsp/design_analysis_timing.rpt -| Design : soc_top -| Device : xc7a200t -| Design State : Routed ------------------------------------------------------------------------------------------------------------------------ - -Report Design Analysis - -Table of Contents ------------------ -1. Setup Path Characteristics 1-1 - -1. Setup Path Characteristics 1-1 ---------------------------------- - -+---------------------------+------------------------------------------------------+ -| Characteristics | Path #1 | -+---------------------------+------------------------------------------------------+ -| Requirement | 20.000 | -| Path Delay | 15.605 | -| Logic Delay | 5.343(35%) | -| Net Delay | 10.263(65%) | -| Clock Skew | -3.858 | -| Slack | 0.167 | -| Clock Relationship | Safely Timed | -| Logic Levels | 9 | -| Routes | 9 | -| Logical Path | FDRE LUT4 LUT6 LUT5 LUT6 RAMD32 LUT6 LUT5 LUT3 OBUFT | -| Start Point Clock | sys_clk | -| End Point Clock | sys_clk | -| DSP Block | None | -| BRAM | None | -| IO Crossings | 3 | -| Config Crossings | 0 | -| SLR Crossings | 0 | -| PBlocks | 0 | -| High Fanout | 130 | -| Dont Touch | 0 | -| Mark Debug | 0 | -| Start Point Pin Primitive | FDRE/C | -| End Point Pin Primitive | ext_ram_data[18] | -| Start Point Pin | FSM_sequential_ext_wr_state_reg[1]/C | -| End Point Pin | ext_ram_data[18] | -+---------------------------+------------------------------------------------------+ -* Bounding box calculated as % of dimensions for the target device (436, 500) - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt deleted file mode 100644 index 213e823..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/drc.rpt +++ /dev/null @@ -1,491 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:33:58 2026 -| Host : fedora running 64-bit unknown -| Command : report_drc -file /home/fallensigh/vivado_reports_nodsp/drc.rpt -| Design : soc_top -| Device : xc7a200tfbg676-1 -| Speed File : -1 -| Design State : Fully Routed ------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: impl_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 90 -+-----------+----------+----------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+----------------------------+------------+ -| CHECK-3 | Warning | Report rule limit reached | 2 | -| DPIP-1 | Warning | Input pipelining | 16 | -| DPOP-1 | Warning | PREG Output pipelining | 16 | -| DPOP-2 | Warning | MREG Output pipelining | 16 | -| REQP-1839 | Warning | RAMB36 async control check | 20 | -| REQP-1840 | Warning | RAMB18 async control check | 20 | -+-----------+----------+----------------------------+------------+ - -2. REPORT DETAILS ------------------ -CHECK-3#1 Warning -Report rule limit reached -REQP-1839 rule limit reached: 20 violations have been found. -Related violations: - -CHECK-3#2 Warning -Report rule limit reached -REQP-1840 rule limit reached: 20 violations have been found. -Related violations: - -DPIP-1#1 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#2 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#3 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#4 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#5 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#6 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#7 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#8 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#9 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#10 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#11 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#12 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#13 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#14 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#15 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPIP-1#16 Warning -Input pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr input u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance. -Related violations: - -DPOP-1#1 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#2 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#3 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#4 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#5 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#6 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#7 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#8 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#9 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#10 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#11 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#12 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#13 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#14 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#15 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-1#16 Warning -PREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr output u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1. -Related violations: - -DPOP-2#1 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#2 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#3 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#4 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#5 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#6 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#7 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#8 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#9 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#10 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#11 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#12 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#13 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#14 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/aibr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#15 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbi/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -DPOP-2#16 Warning -MREG Output pipelining -DSP u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr multiplier stage u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/MU/arbr/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions. -Related violations: - -REQP-1839#1 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#2 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#3 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#4 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#5 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#6 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#7 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#8 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#9 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#10 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[13] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[8]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#11 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#12 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#13 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#14 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#15 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#16 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#17 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#18 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#19 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1839#20 Warning -RAMB36 async control check -The RAMB36E1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg has an input control pin u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/ADDRARDADDR[14] (net: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ADDRARDADDR[9]) which is driven by a register (u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf2_count_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#1 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#2 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#3 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#4 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#5 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#6 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#7 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#8 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRARDADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#9 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[10] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[5]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#10 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[11] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[6]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#11 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[12] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[7]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#12 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[5] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[0]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#13 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[6] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[1]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#14 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[7] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#15 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[8] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#16 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ADDRBWRADDR[9] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_addra[0][0]_26[4]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#17 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENARDEN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_1__15_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#18 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/ENBWREN (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg_i_2__13_n_0) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#19 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[2] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[2]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - -REQP-1840#20 Warning -RAMB18 async control check -The RAMB18E1 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg has an input control pin u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/WEBWE[3] (net: u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/way_bank_wea[0][0]_14[3]) which is driven by a register (u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. -Related violations: - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt deleted file mode 100644 index 5af6bfc..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/high_fanout.rpt +++ /dev/null @@ -1,221 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_high_fanout_nets -fanout_greater_than 100 -max_nets 200 -file /home/fallensigh/vivado_reports_nodsp/high_fanout.rpt -| Design : soc_top -| Device : xc7a200t --------------------------------------------------------------------------------------------------------------------------------------------- - -High Fan-out Nets Information - -1. Summary ----------- - -+---------------------------------------------------------------------------------------+--------+-------------+ -| Net Name | Fanout | Driver Type | -+---------------------------------------------------------------------------------------+--------+-------------+ -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/delay_reg[1] | 24598 | LUT5 | -| pll_clk.u_clk_pll/inst/sys_clk | 10004 | BUFG | -| pll_clk.u_rst_sys/p_0_in | 4130 | LUT1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/E[0] | 2048 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/perm_done_reg_n_0 | 1619 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_0[0] | 1608 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_n_0 | 1608 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_mb_state[2]_i_3_n_0 | 1604 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sel_cbd | 1603 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 | 1601 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 | 1601 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_6_n_0 | 1601 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_7_n_0 | 1601 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r[1599]_i_1_n_0 | 1600 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[1] | 1543 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/addr_even[2] | 1542 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/busy_r_reg_1 | 1109 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inc_reg_n_0 | 1088 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_wb_inz_reg_n_0 | 1088 | FDRE | -| pll_clk.u_rst_mlkem/delay_reg[1]_0 | 1069 | LUT1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_mb_en0 | 936 | LUT5 | -| u_cpu/reset | 799 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[0] | 769 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[1] | 769 | CARRY4 | -| u_matmul_axi_slave/w_addr[2] | 724 | FDRE | -| u_cpu/u_mul/E[0] | 716 | LUT1 | -| u_matmul_axi_slave/w_addr[3] | 628 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/m_r1 | 528 | LUT6 | -| u_matmul_axi_slave/current_r_offset[2] | 522 | LUT5 | -| u_matmul_axi_slave/current_r_offset[3] | 520 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[0] | 516 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_phase_reg_n_0_[1] | 516 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r0 | 512 | LUT2 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/st_reg[0]_rep_2[0] | 512 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[2] | 390 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[2] | 385 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_vld_reg_n_0 | 370 | FDCE | -| u_cpu/wb_stage/w_index[0] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[1] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[2] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[3] | 358 | LUT6 | -| u_cpu/wb_stage/w_index[4] | 358 | LUT6 | -| u_matmul_axi_slave/acc_idx_d4[0] | 354 | FDRE | -| u_matmul_axi_slave/acc_idx_d4[1] | 354 | FDRE | -| u_matmul_axi_slave/acc_idx_d4[2] | 354 | FDRE | -| u_matmul_axi_slave/acc_idx_d4[3] | 354 | FDRE | -| u_cpu/wb_stage/we_0 | 324 | LUT4 | -| u_matmul_axi_slave/w_addr[4] | 317 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/rho_r1 | 290 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[3] | 284 | FDCE | -| u_matmul_axi_slave/cur_bank_reg_n_0 | 277 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[10] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[11] | 263 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[8] | 262 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[9] | 261 | RAMB18E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[0] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[10] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[11] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[1] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[2] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[3] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[4] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[5] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[6] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[7] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[8] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/DOBDO[9] | 261 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/cbd_enc | 261 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[4] | 260 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[0] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[1] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[2] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[3] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[4] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[5] | 259 | RAMB36E1 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/rd_data[6] | 259 | RAMB36E1 | -| u_matmul_axi_slave/pipe_cnt_reg[0]_rep_n_0 | 259 | FDRE | -| u_matmul_axi_slave/pipe_cnt_reg[1]_rep_n_0 | 257 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[0] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[10] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[11] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[1] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[2] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[3] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[4] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[5] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[6] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[7] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[8] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/ntt_in[9] | 256 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/dj_active_reg_rep__7[0] | 256 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_digest_r | 256 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_1_n_0 | 256 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/sha3_mode | 250 | LUT4 | -| u_matmul_axi_slave/w_addr[5] | 246 | FDRE | -| u_snix_axil_cdma_mux_8ch/u_core_engine/wr_start_edge | 245 | LUT3 | -| u_cpu/exe_stage/ds_to_es_bus_r0 | 234 | LUT5 | -| u_cpu/mem_stage/E[0] | 234 | LUT6 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[9] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[0] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[10] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[11] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[1] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[3] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[4] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[5] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[6] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[7] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[8] | 234 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[9] | 234 | FDCE | -| u_matmul_axi_slave/acc_bank_d2_reg_srl2___u_matmul_axi_slave_acc_idx_d2_reg_r_i_2_n_0 | 229 | LUT3 | -| u_matmul_axi_slave/m_in_b[0][31]_i_7_n_0 | 228 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[1] | 227 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[1022]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[126]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[254]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[382]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[510]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[638]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[766]_i_2_n_0 | 224 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r[894]_i_2_n_0 | 224 | LUT4 | -| u_axi_axil_adapter/axi_axil_adapter_wr_inst/delay_reg[1]_0 | 211 | LUT2 | -| u_cpu/mem_stage/es_to_ms_bus_r0 | 210 | LUT2 | -| u_cpu/u_csr/tlbw_r_tlbidx[2] | 210 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[0] | 203 | FDRE | -| u_snix_axil_cdma_mux_8ch/cur_ch_reg_n_0_[1] | 203 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[6] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[4] | 200 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/out_cnt_reg_n_0_[3] | 197 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/grp_ptr_r_reg_n_0_[2] | 196 | FDCE | -| u_snix_axil_cdma_mux_8ch/ADDRA[0] | 196 | LUT6 | -| u_cpu/wb_stage/Q[33] | 194 | FDRE | -| u_cpu/wb_stage/Q[34] | 194 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/buf_ptr_reg_n_0_[5] | 194 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/j_reg[3]_rep[3] | 193 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r_reg[4]_rep_n_0 | 191 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[2] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[3] | 187 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[1] | 187 | FDCE | -| u_matmul_axi_slave/current_r_offset[4] | 187 | LUT5 | -| u_matmul_axi_slave/s_axi_wready_reg_1 | 181 | LUT3 | -| u_cpu/wb_stage/ws_valid_reg_0 | 180 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[3] | 180 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[2] | 177 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[0] | 176 | FDCE | -| u_matmul_axi_slave/p_0_in__0 | 176 | LUT4 | -| u_matmul_axi_slave/p_0_in__0__0 | 176 | LUT4 | -| u_cpu/wb_stage/Q[37] | 173 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[7] | 173 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/d_word_reg[1][31]_i_4_n_7 | 171 | CARRY4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[127]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[383]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[639]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[895]_i_2_n_0 | 169 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] | 169 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/load_cnt[5] | 166 | FDCE | -| u_cpu/wb_stage/Q[32] | 164 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wa_r[0] | 164 | FDCE | -| u_cpu/wb_stage/Q[35] | 163 | FDRE | -| u_cpu/wb_stage/Q[36] | 162 | FDRE | -| u_axi_axil_adapter/axi_axil_adapter_rd_inst/m_axil_araddr_reg_reg[2]_0 | 161 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1023]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[255]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[511]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[767]_i_2_n_0 | 160 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/p_0_in[3] | 155 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/load_cnt[6] | 153 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_2_n_0 | 153 | LUT3 | -| u_cpu/axi_bridge/FSM_sequential_write_requst_state_reg[1]_0 | 151 | FDRE | -| u_snix_axil_cdma_mux_8ch/u_core_engine/num_bytes_comb1 | 150 | CARRY4 | -| u_cpu/dcache/awaddr[31]_i_3_n_0 | 148 | LUT2 | -| u_cpu/dcache/awaddr[31]_i_4_n_0 | 148 | LUT2 | -| u_matmul_axi_slave/s_axi_wready_reg_0 | 148 | LUT5 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_wb_idx_reg_n_0_[0] | 145 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_12_17_i_63_n_0 | 144 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[6] | 143 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_wb_r[6] | 143 | FDCE | -| u_matmul_axi_slave/pipe_cnt[3]_i_3_n_0 | 143 | LUT3 | -| u_matmul_axi_slave/pipe_cnt[3]_i_4_n_0 | 143 | LUT3 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep_n_0 | 142 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[4] | 141 | FDCE | -| u_cpu/dcache/write_buffer_state | 140 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_active_reg_rep__6_n_0 | 140 | FDCE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/men_idx[5] | 140 | FDCE | -| u_cpu/u_csr/tlbw_r_tlbidx[0] | 139 | FDRE | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/ram_reg_0_7_0_5_i_37_n_0 | 139 | LUT4 | -| u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep__3_n_0 | 139 | FDCE | -+---------------------------------------------------------------------------------------+--------+-------------+ - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt deleted file mode 100644 index 82b3488..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/methodology.rpt +++ /dev/null @@ -1,542 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 -| Host : fedora running 64-bit unknown -| Command : report_methodology -file /home/fallensigh/vivado_reports_nodsp/methodology.rpt -| Design : soc_top -| Device : xc7a200tfbg676-1 -| Speed File : -1 -| Design State : Fully Routed ------------------------------------------------------------------------------------------------- - -Report Methodology - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: impl_1 - Design limits: - Max violations: - Violations found: 99 -+-----------+----------+-------------------------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+-------------------------------------------------------------------+------------+ -| LUTAR-1 | Warning | LUT drives async reset alert | 1 | -| SYNTH-5 | Warning | Mapped onto distributed RAM because of timing constraints | 8 | -| SYNTH-6 | Warning | Timing of a block RAM might be sub-optimal | 1 | -| SYNTH-16 | Warning | Address collision | 8 | -| TIMING-10 | Warning | Missing property on synchronizer | 1 | -| TIMING-18 | Warning | Missing input or output delay | 76 | -| TIMING-47 | Warning | False path or asynchronous clock group between synchronous clocks | 2 | -| XDCC-1 | Warning | Scoped Clock constraint overwritten with the same name | 1 | -| XDCC-7 | Warning | Scoped Clock constraint overwritten on the same source | 1 | -+-----------+----------+-------------------------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -LUTAR-1#1 Warning -LUT drives async reset alert -LUT cell u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9, with 2 or more inputs, drives asynchronous preset/clear pin(s) u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_busy_reg/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_i_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_j_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[2]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[3]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_pair_reg[4]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[0]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[1]/CLR, u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/a_widx_reg[2]/CLR (the first 15 of 24584 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. -Related violations: - -SYNTH-5#1 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#2 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#3 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#4 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r1_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#5 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#6 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_0_127_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#7 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-5#8 Warning -Mapped onto distributed RAM because of timing constraints -The instance u_cpu/dcache/way_d_reg_reg_r2_128_255_1_1 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing. -Related violations: - -SYNTH-6#1 Warning -Timing of a block RAM might be sub-optimal -The timing for the instance u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg, implemented as a block RAM, might be sub-optimal as no output register was merged into the block -Related violations: - -SYNTH-16#1 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#2 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1 may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#3 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#4 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#5 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#6 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#7 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -SYNTH-16#8 Warning -Address collision -Block RAM u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended. -Related violations: - -TIMING-10#1 Warning -Missing property on synchronizer -One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage -Related violations: - -TIMING-18#1 Warning -Missing input or output delay -An input delay is missing on UART_RX relative to clock(s) clk -Related violations: - -TIMING-18#2 Warning -Missing input or output delay -An input delay is missing on UART_TX relative to clock(s) clk -Related violations: - -TIMING-18#3 Warning -Missing input or output delay -An input delay is missing on dip_sw[0] relative to clock(s) clk -Related violations: - -TIMING-18#4 Warning -Missing input or output delay -An input delay is missing on dip_sw[10] relative to clock(s) clk -Related violations: - -TIMING-18#5 Warning -Missing input or output delay -An input delay is missing on dip_sw[11] relative to clock(s) clk -Related violations: - -TIMING-18#6 Warning -Missing input or output delay -An input delay is missing on dip_sw[12] relative to clock(s) clk -Related violations: - -TIMING-18#7 Warning -Missing input or output delay -An input delay is missing on dip_sw[13] relative to clock(s) clk -Related violations: - -TIMING-18#8 Warning -Missing input or output delay -An input delay is missing on dip_sw[14] relative to clock(s) clk -Related violations: - -TIMING-18#9 Warning -Missing input or output delay -An input delay is missing on dip_sw[15] relative to clock(s) clk -Related violations: - -TIMING-18#10 Warning -Missing input or output delay -An input delay is missing on dip_sw[16] relative to clock(s) clk -Related violations: - -TIMING-18#11 Warning -Missing input or output delay -An input delay is missing on dip_sw[17] relative to clock(s) clk -Related violations: - -TIMING-18#12 Warning -Missing input or output delay -An input delay is missing on dip_sw[18] relative to clock(s) clk -Related violations: - -TIMING-18#13 Warning -Missing input or output delay -An input delay is missing on dip_sw[19] relative to clock(s) clk -Related violations: - -TIMING-18#14 Warning -Missing input or output delay -An input delay is missing on dip_sw[1] relative to clock(s) clk -Related violations: - -TIMING-18#15 Warning -Missing input or output delay -An input delay is missing on dip_sw[20] relative to clock(s) clk -Related violations: - -TIMING-18#16 Warning -Missing input or output delay -An input delay is missing on dip_sw[21] relative to clock(s) clk -Related violations: - -TIMING-18#17 Warning -Missing input or output delay -An input delay is missing on dip_sw[22] relative to clock(s) clk -Related violations: - -TIMING-18#18 Warning -Missing input or output delay -An input delay is missing on dip_sw[23] relative to clock(s) clk -Related violations: - -TIMING-18#19 Warning -Missing input or output delay -An input delay is missing on dip_sw[24] relative to clock(s) clk -Related violations: - -TIMING-18#20 Warning -Missing input or output delay -An input delay is missing on dip_sw[25] relative to clock(s) clk -Related violations: - -TIMING-18#21 Warning -Missing input or output delay -An input delay is missing on dip_sw[26] relative to clock(s) clk -Related violations: - -TIMING-18#22 Warning -Missing input or output delay -An input delay is missing on dip_sw[27] relative to clock(s) clk -Related violations: - -TIMING-18#23 Warning -Missing input or output delay -An input delay is missing on dip_sw[28] relative to clock(s) clk -Related violations: - -TIMING-18#24 Warning -Missing input or output delay -An input delay is missing on dip_sw[29] relative to clock(s) clk -Related violations: - -TIMING-18#25 Warning -Missing input or output delay -An input delay is missing on dip_sw[2] relative to clock(s) clk -Related violations: - -TIMING-18#26 Warning -Missing input or output delay -An input delay is missing on dip_sw[30] relative to clock(s) clk -Related violations: - -TIMING-18#27 Warning -Missing input or output delay -An input delay is missing on dip_sw[31] relative to clock(s) clk -Related violations: - -TIMING-18#28 Warning -Missing input or output delay -An input delay is missing on dip_sw[3] relative to clock(s) clk -Related violations: - -TIMING-18#29 Warning -Missing input or output delay -An input delay is missing on dip_sw[4] relative to clock(s) clk -Related violations: - -TIMING-18#30 Warning -Missing input or output delay -An input delay is missing on dip_sw[5] relative to clock(s) clk -Related violations: - -TIMING-18#31 Warning -Missing input or output delay -An input delay is missing on dip_sw[6] relative to clock(s) clk -Related violations: - -TIMING-18#32 Warning -Missing input or output delay -An input delay is missing on dip_sw[7] relative to clock(s) clk -Related violations: - -TIMING-18#33 Warning -Missing input or output delay -An input delay is missing on dip_sw[8] relative to clock(s) clk -Related violations: - -TIMING-18#34 Warning -Missing input or output delay -An input delay is missing on dip_sw[9] relative to clock(s) clk -Related violations: - -TIMING-18#35 Warning -Missing input or output delay -An input delay is missing on touch_btn[0] relative to clock(s) clk -Related violations: - -TIMING-18#36 Warning -Missing input or output delay -An input delay is missing on touch_btn[1] relative to clock(s) clk -Related violations: - -TIMING-18#37 Warning -Missing input or output delay -An input delay is missing on touch_btn[2] relative to clock(s) clk -Related violations: - -TIMING-18#38 Warning -Missing input or output delay -An input delay is missing on touch_btn[3] relative to clock(s) clk -Related violations: - -TIMING-18#39 Warning -Missing input or output delay -An output delay is missing on dpy0[0] relative to clock(s) clk -Related violations: - -TIMING-18#40 Warning -Missing input or output delay -An output delay is missing on dpy0[1] relative to clock(s) clk -Related violations: - -TIMING-18#41 Warning -Missing input or output delay -An output delay is missing on dpy0[2] relative to clock(s) clk -Related violations: - -TIMING-18#42 Warning -Missing input or output delay -An output delay is missing on dpy0[3] relative to clock(s) clk -Related violations: - -TIMING-18#43 Warning -Missing input or output delay -An output delay is missing on dpy0[4] relative to clock(s) clk -Related violations: - -TIMING-18#44 Warning -Missing input or output delay -An output delay is missing on dpy0[5] relative to clock(s) clk -Related violations: - -TIMING-18#45 Warning -Missing input or output delay -An output delay is missing on dpy0[6] relative to clock(s) clk -Related violations: - -TIMING-18#46 Warning -Missing input or output delay -An output delay is missing on dpy0[7] relative to clock(s) clk -Related violations: - -TIMING-18#47 Warning -Missing input or output delay -An output delay is missing on dpy1[0] relative to clock(s) clk -Related violations: - -TIMING-18#48 Warning -Missing input or output delay -An output delay is missing on dpy1[1] relative to clock(s) clk -Related violations: - -TIMING-18#49 Warning -Missing input or output delay -An output delay is missing on dpy1[2] relative to clock(s) clk -Related violations: - -TIMING-18#50 Warning -Missing input or output delay -An output delay is missing on dpy1[3] relative to clock(s) clk -Related violations: - -TIMING-18#51 Warning -Missing input or output delay -An output delay is missing on dpy1[4] relative to clock(s) clk -Related violations: - -TIMING-18#52 Warning -Missing input or output delay -An output delay is missing on dpy1[5] relative to clock(s) clk -Related violations: - -TIMING-18#53 Warning -Missing input or output delay -An output delay is missing on dpy1[6] relative to clock(s) clk -Related violations: - -TIMING-18#54 Warning -Missing input or output delay -An output delay is missing on dpy1[7] relative to clock(s) clk -Related violations: - -TIMING-18#55 Warning -Missing input or output delay -An output delay is missing on leds[0] relative to clock(s) clk -Related violations: - -TIMING-18#56 Warning -Missing input or output delay -An output delay is missing on leds[10] relative to clock(s) clk -Related violations: - -TIMING-18#57 Warning -Missing input or output delay -An output delay is missing on leds[11] relative to clock(s) clk -Related violations: - -TIMING-18#58 Warning -Missing input or output delay -An output delay is missing on leds[12] relative to clock(s) clk -Related violations: - -TIMING-18#59 Warning -Missing input or output delay -An output delay is missing on leds[13] relative to clock(s) clk -Related violations: - -TIMING-18#60 Warning -Missing input or output delay -An output delay is missing on leds[14] relative to clock(s) clk -Related violations: - -TIMING-18#61 Warning -Missing input or output delay -An output delay is missing on leds[15] relative to clock(s) clk -Related violations: - -TIMING-18#62 Warning -Missing input or output delay -An output delay is missing on leds[1] relative to clock(s) clk -Related violations: - -TIMING-18#63 Warning -Missing input or output delay -An output delay is missing on leds[2] relative to clock(s) clk -Related violations: - -TIMING-18#64 Warning -Missing input or output delay -An output delay is missing on leds[3] relative to clock(s) clk -Related violations: - -TIMING-18#65 Warning -Missing input or output delay -An output delay is missing on leds[4] relative to clock(s) clk -Related violations: - -TIMING-18#66 Warning -Missing input or output delay -An output delay is missing on leds[5] relative to clock(s) clk -Related violations: - -TIMING-18#67 Warning -Missing input or output delay -An output delay is missing on leds[6] relative to clock(s) clk -Related violations: - -TIMING-18#68 Warning -Missing input or output delay -An output delay is missing on leds[7] relative to clock(s) clk -Related violations: - -TIMING-18#69 Warning -Missing input or output delay -An output delay is missing on leds[8] relative to clock(s) clk -Related violations: - -TIMING-18#70 Warning -Missing input or output delay -An output delay is missing on leds[9] relative to clock(s) clk -Related violations: - -TIMING-18#71 Warning -Missing input or output delay -An output delay is missing on video_de relative to clock(s) clk -Related violations: - -TIMING-18#72 Warning -Missing input or output delay -An output delay is missing on video_hsync relative to clock(s) clk -Related violations: - -TIMING-18#73 Warning -Missing input or output delay -An output delay is missing on video_red[0] relative to clock(s) clk -Related violations: - -TIMING-18#74 Warning -Missing input or output delay -An output delay is missing on video_red[1] relative to clock(s) clk -Related violations: - -TIMING-18#75 Warning -Missing input or output delay -An output delay is missing on video_red[2] relative to clock(s) clk -Related violations: - -TIMING-18#76 Warning -Missing input or output delay -An output delay is missing on video_vsync relative to clock(s) clk -Related violations: - -TIMING-47#1 Warning -False path or asynchronous clock group between synchronous clocks -A Clock Group timing constraint is set between synchronous clocks cpu_clk and sys_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. -Related violations: - -TIMING-47#2 Warning -False path or asynchronous clock group between synchronous clocks -A Clock Group timing constraint is set between synchronous clocks sys_clk and cpu_clk (see constraint position 6 in the Timing Constraint window in Vivado IDE). It is not recommended to cover synchronous clock domains with constraints that prevent timing analysis as the design could fail in hardware. -Related violations: - -XDCC-1#1 Warning -Scoped Clock constraint overwritten with the same name -A new clock constraint create_clock overrides a previous scoped clock constraint with the same name. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors. -New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4)) -Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56)) -Related violations: - -XDCC-7#1 Warning -Scoped Clock constraint overwritten on the same source -A new clock constraint create_clock overrides a previous scoped clock constraint defined on the same source. It is not recommended to override a scoped (typically an IP) clock constraint and could result in unexpected behaviors. -New: create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/constraints/soc.xdc (Line: 4)) -Previous: create_clock -period 20.000 [get_ports clk] (Source: /home/fallensigh/Dev/ciciec2026_loongson_regional/fpga/project/ipgen/clk_pll/clk_pll.xdc (Line: 56)) -Related violations: - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/mlkem_clk_timing.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/mlkem_clk_timing.rpt deleted file mode 100644 index 2fdd8cd..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/mlkem_clk_timing.rpt +++ /dev/null @@ -1,5216 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_timing -from [get_clocks mlkem_clk_clk_pll] -to [get_clocks mlkem_clk_clk_pll] -delay_type max -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/mlkem_clk_timing.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Timing Report - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - - - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt deleted file mode 100644 index 851e855..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/power.rpt +++ /dev/null @@ -1,180 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:25 2026 -| Host : fedora running 64-bit unknown -| Command : report_power -file /home/fallensigh/vivado_reports_nodsp/power.rpt -| Design : soc_top -| Device : xc7a200tfbg676-1 -| Design State : routed -| Grade : commercial -| Process : typical -| Characterization : Production ------------------------------------------------------------------------------------------------- - -Power Report - -Table of Contents ------------------ -1. Summary -1.1 On-Chip Components -1.2 Power Supply Summary -1.3 Confidence Level -2. Settings -2.1 Environment -2.2 Clock Constraints -3. Detailed Reports -3.1 By Hierarchy - -1. Summary ----------- - -+--------------------------+--------------+ -| Total On-Chip Power (W) | 0.549 | -| Design Power Budget (W) | Unspecified* | -| Power Budget Margin (W) | NA | -| Dynamic (W) | 0.409 | -| Device Static (W) | 0.141 | -| Effective TJA (C/W) | 1.9 | -| Max Ambient (C) | 84.0 | -| Junction Temperature (C) | 26.0 | -| Confidence Level | Low | -| Setting File | --- | -| Simulation Activity File | --- | -| Design Nets Matched | NA | -+--------------------------+--------------+ -* Specify Design Power Budget using, set_operating_conditions -design_power_budget - - -1.1 On-Chip Components ----------------------- - -+--------------------------+-----------+----------+-----------+-----------------+ -| On-Chip | Power (W) | Used | Available | Utilization (%) | -+--------------------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.042 | 7 | --- | --- | -| Slice Logic | 0.069 | 120086 | --- | --- | -| LUT as Logic | 0.064 | 63754 | 133800 | 47.65 | -| CARRY4 | 0.002 | 2859 | 33450 | 8.55 | -| LUT as Distributed RAM | <0.001 | 740 | 46200 | 1.60 | -| Register | <0.001 | 39931 | 267600 | 14.92 | -| LUT as Shift Register | <0.001 | 1175 | 46200 | 2.54 | -| F7/F8 Muxes | <0.001 | 6036 | 133800 | 4.51 | -| Others | 0.000 | 318 | --- | --- | -| Signals | 0.115 | 85084 | --- | --- | -| Block RAM | 0.019 | 23.5 | 365 | 6.44 | -| PLL | 0.132 | 1 | 10 | 10.00 | -| DSPs | 0.009 | 16 | 740 | 2.16 | -| I/O | 0.023 | 202 | 400 | 50.50 | -| Static Power | 0.141 | | | | -| Total | 0.549 | | | | -+--------------------------+-----------+----------+-----------+-----------------+ - - -1.2 Power Supply Summary ------------------------- - -+-----------+-------------+-----------+-------------+------------+ -| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | -+-----------+-------------+-----------+-------------+------------+ -| Vccint | 1.000 | 0.294 | 0.262 | 0.032 | -| Vccaux | 1.800 | 0.099 | 0.069 | 0.031 | -| Vcco33 | 3.300 | 0.011 | 0.006 | 0.005 | -| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | -| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | -| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | -| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | -| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 1.000 | 0.003 | 0.001 | 0.001 | -| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | -| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | -+-----------+-------------+-----------+-------------+------------+ - - -1.3 Confidence Level --------------------- - -+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | High | User specified more than 95% of clocks | | -| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Low | | | -+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ - - -2. Settings ------------ - -2.1 Environment ---------------- - -+-----------------------+--------------------------+ -| Ambient Temp (C) | 25.0 | -| ThetaJA (C/W) | 1.9 | -| Airflow (LFM) | 250 | -| Heat Sink | medium (Medium Profile) | -| ThetaSA (C/W) | 3.4 | -| Board Selection | medium (10"x10") | -| # of Board Layers | 12to15 (12 to 15 Layers) | -| Board Temperature (C) | 25.0 | -+-----------------------+--------------------------+ - - -2.2 Clock Constraints ---------------------- - -+-------------------+------------------------------------------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------------------+------------------------------------------+-----------------+ -| clk | clk | 20.0 | -| clkfbout_clk_pll | pll_clk.u_clk_pll/inst/clkfbout_clk_pll | 20.0 | -| cpu_clk | pll_clk.u_clk_pll/inst/cpu_clk_clk_pll | 30.3 | -| mlkem_clk_clk_pll | pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll | 40.0 | -| sys_clk | pll_clk.u_clk_pll/inst/sys_clk_clk_pll | 20.0 | -+-------------------+------------------------------------------+-----------------+ - - -3. Detailed Reports -------------------- - -3.1 By Hierarchy ----------------- - -+----------------------------+-----------+ -| Name | Power (W) | -+----------------------------+-----------+ -| soc_top | 0.409 | -| pll_clk.u_clk_pll | 0.133 | -| inst | 0.133 | -| u_Axi_CDC | 0.002 | -| u_axi_uart_controller | 0.001 | -| uart0 | 0.001 | -| regs | 0.001 | -| u_cdma_matmul_bridge | 0.001 | -| u_cpu | 0.018 | -| addr_trans | 0.002 | -| tlb_entry | 0.002 | -| btb | 0.002 | -| dcache | 0.004 | -| icache | 0.005 | -| u_csr | 0.002 | -| u_fft_mlkem_axi_slave | 0.148 | -| u_fft_controller | 0.032 | -| u_FFT | 0.029 | -| u_mlkem_axi_cdc | 0.002 | -| u_mlkem_axi_slave | 0.115 | -| u_mlkem | 0.113 | -| u_matmul_axi_slave | 0.065 | -| u_snix_axil_cdma_mux_8ch | 0.009 | -| u_core_engine | 0.004 | -| axis_fifo_u0 | 0.003 | -+----------------------------+-----------+ - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt deleted file mode 100644 index a98697c..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/route_status.rpt +++ /dev/null @@ -1,12 +0,0 @@ -Design Route Status - : # nets : - ------------------------------------------- : ----------- : - # of logical nets.......................... : 128919 : - # of nets not needing routing.......... : 43824 : - # of internally routed nets........ : 43359 : - # of nets with no loads............ : 465 : - # of routable nets..................... : 85095 : - # of fully routed nets............. : 85095 : - # of nets with routing errors.......... : 0 : - ------------------------------------------- : ----------- : - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_hold_paths.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_hold_paths.rpt deleted file mode 100644 index fefd31f..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_hold_paths.rpt +++ /dev/null @@ -1,17094 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:13 2026 -| Host : fedora running 64-bit unknown -| Command : report_timing -delay_type min -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_hold_paths.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Timing Report - -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 - ------------------------------------------------------------------- - slack 0.032 - -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.595 -0.352 - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 - ------------------------------------------------------------------- - slack 0.032 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.049ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 - ------------------------------------------------------------------- - slack 0.049 - -Slack (MET) : 0.049ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y34 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 - ------------------------------------------------------------------- - slack 0.049 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 - ------------------------------------------------------------------- - slack 0.054 - -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.269 -0.579 - SLICE_X20Y72 RAMD32 0.000 -0.579 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 - ------------------------------------------------------------------- - slack 0.054 - -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.353 -0.496 - SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.353 -0.496 - SLICE_X17Y49 FDRE 0.000 -0.496 r u_cpu/axi_bridge/awaddr_reg[10]/C - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 f u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.153 -0.695 - SLICE_X84Y144 FDRE 0.000 -0.695 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/I0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.472 -0.475 - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[0]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.342 -0.507 - SLICE_X37Y38 FDRE 0.000 -0.507 r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 f u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.674 -0.273 - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.554 -0.393 - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X86Y154 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/I0 - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.478 -0.469 - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.282 -0.566 - SLICE_X18Y50 SRLC32E 0.000 -0.566 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.687 -0.260 - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X43Y35 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X4Y57 FDRE 0.000 -0.541 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 f u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.177 -0.672 - SLICE_X138Y154 FDCE 0.000 -0.672 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/I3 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.508 -0.439 - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X62Y75 FDCE 0.000 -0.626 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 f u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.357 - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X23Y49 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[1]/C - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X20Y76 RAMD32 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X85Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/I1 - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/S[0] - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.165 -0.683 - SLICE_X73Y148 FDCE 0.000 -0.683 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.483 -0.464 - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X20Y50 SRLC32E 0.000 -0.568 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.685 -0.262 - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[14]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X85Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/I0 - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/S[2] - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.352 -0.497 - SLICE_X21Y48 FDRE 0.000 -0.497 r u_cpu/axi_bridge/awaddr_reg[3]/C - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 f u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 f u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.271 -0.577 - SLICE_X18Y78 RAMD32 0.000 -0.577 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.598 -0.349 - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X83Y155 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/I0 - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.471 -0.476 - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[1]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.214 -0.634 - SLICE_X14Y104 FDRE 0.000 -0.634 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[2] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[2] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[2] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[2] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.156 -0.693 - SLICE_X89Y154 FDCE 0.000 -0.693 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/I3 - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.489 -0.458 - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.222 -0.626 - SLICE_X64Y76 RAMD32 0.000 -0.626 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.268 -0.580 - SLICE_X22Y71 RAMD32 0.000 -0.580 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.215 -0.633 - SLICE_X14Y102 FDRE 0.000 -0.633 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 f u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE f u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.146 -0.703 - SLICE_X84Y160 FDCE 0.000 -0.703 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/I0 - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/S[0] - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.468 -0.479 - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y157 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/I1 - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/S[0] - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y158 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/I1 - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/S[0] - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.147 -0.702 - SLICE_X84Y159 FDCE 0.000 -0.702 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/I1 - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/S[0] - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.469 -0.478 - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.148 -0.701 - SLICE_X84Y156 FDCE 0.000 -0.701 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/I1 - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/S[0] - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.470 -0.477 - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.298 -0.550 - SLICE_X2Y75 FDCE 0.000 -0.550 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 f axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.625 -0.322 - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.305 -0.543 - SLICE_X6Y62 FDRE 0.000 -0.543 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 f u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X7Y48 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[15]/C - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.221 -0.627 - SLICE_X64Y75 RAMD32 0.000 -0.627 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.555 -0.392 - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.272 -0.576 - SLICE_X15Y70 FDCE 0.000 -0.576 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE f u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.276 -0.572 - SLICE_X15Y66 FDCE 0.000 -0.572 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.603 -0.344 - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X17Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE f u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.539 - SLICE_X1Y61 FDSE 0.000 -0.539 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE f u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.639 -0.308 - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.245 -0.603 - SLICE_X117Y61 FDCE 0.000 -0.603 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE f u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.573 -0.374 - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.266 -0.582 - SLICE_X27Y78 FDCE 0.000 -0.582 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.593 -0.354 - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.261 -0.587 - SLICE_X29Y74 FDCE 0.000 -0.587 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.295 -0.553 - SLICE_X5Y75 FDCE 0.000 -0.553 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.623 -0.324 - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y34 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y36 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.382 -0.467 - SLICE_X5Y47 FDRE 0.000 -0.467 r u_cpu/axi_bridge/wdata_reg[22]/C - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 f u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X15Y69 FDCE 0.000 -0.575 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.600 -0.347 - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.280 -0.568 - SLICE_X19Y59 FDCE 0.000 -0.568 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.296 -0.552 - SLICE_X5Y76 FDCE 0.000 -0.552 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.624 -0.323 - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.339 -0.510 - SLICE_X41Y37 FDRE 0.000 -0.510 r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 f u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.308 -0.541 - SLICE_X47Y35 FDRE 0.000 -0.541 r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 f u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.638 -0.309 - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.602 -0.345 - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.542 - SLICE_X43Y32 FDRE 0.000 -0.542 r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 f u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.637 -0.310 - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[0]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.340 -0.509 - SLICE_X39Y39 FDRE 0.000 -0.509 r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 f u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.672 -0.275 - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB - ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X28Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[2]/C - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB - ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y45 FDRE 0.000 -0.468 r u_cpu/axi_bridge/wdata_reg[12]/C - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.349 -0.500 - SLICE_X29Y48 FDRE 0.000 -0.500 r u_cpu/axi_bridge/araddr_reg[0]/C - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 f u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 f u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.599 -0.348 - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.306 -0.543 - SLICE_X48Y32 FDRE 0.000 -0.543 r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 f u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.635 -0.312 - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y48 FDRE 0.000 -0.465 r u_cpu/axi_bridge/wdata_reg[28]/C - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 f u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.381 -0.468 - SLICE_X5Y43 FDRE 0.000 -0.468 r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 f u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE f u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.715 -0.232 - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.309 -0.540 - SLICE_X45Y36 FDRE 0.000 -0.540 r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 f u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 f u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.347 -0.502 - SLICE_X31Y41 FDRE 0.000 -0.502 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE f u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.679 -0.268 - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns - Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns - Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.345 -0.504 - SLICE_X32Y40 FDRE 0.000 -0.504 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 f u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE f u_cpu/u_csr/lladdr_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.678 -0.269 - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.336 -0.513 - SLICE_X27Y26 FDRE 0.000 -0.513 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 f u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE f u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.665 -0.282 - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X3Y49 FDCE 0.000 -0.465 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 f u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.606 -0.341 - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.524ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.192 -0.534 - SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.626 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.524 - -Slack (MET) : 0.548ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.605 -0.342 - clock pessimism -0.214 -0.556 - SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.648 - arrival time -0.101 - ------------------------------------------------------------------- - slack 0.548 - -Slack (MET) : 0.558ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.620 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.592 -0.355 - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.594 -0.353 - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.650ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.278 -0.570 - SLICE_X13Y87 FDCE 0.000 -0.570 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/I0 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.608 -0.339 - clock pessimism -0.192 -0.531 - SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.598 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.650 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.640 -0.307 - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.384 -0.465 - SLICE_X0Y48 FDCE 0.000 -0.465 r pll_clk.u_rst_cpu/delay_reg[1]/C - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 r pll_clk.u_rst_cpu/reset_i_1/I0 - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.718 -0.229 - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.591 -0.356 - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.566 -0.381 - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.824ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.824 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.267 -0.581 - SLICE_X25Y79 FDCE 0.000 -0.581 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/I0 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.587 -0.360 - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.307 -0.541 - SLICE_X7Y59 FDCE 0.000 -0.541 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 r u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/I0 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.716 -0.231 - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0] - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[2] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.565 -0.382 - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[3] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[1] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.881ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X120Y70 FDCE (Remov_fdce_C_CLR) -0.067 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[2] - ------------------------------------------------------------------- - required time 0.642 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.881 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.273 -0.575 - SLICE_X30Y58 FDCE 0.000 -0.575 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 r u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/I0 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.609 -0.338 - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[13] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[21] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[29] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - -Slack (MET) : 0.906ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.846ns (logic 0.186ns (21.984%) route 0.660ns (78.016%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.032ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.848 -1.848 - propagated clock network latency - 1.241 -0.607 - SLICE_X118Y67 FDCE 0.000 -0.607 r pll_clk.u_rst_mlkem/delay_reg[1]/C - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 r pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/I0 - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.363 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -1.947 -1.947 - propagated clock network latency - 1.564 -0.383 - clock pessimism -0.192 -0.575 - SLICE_X121Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[5] - ------------------------------------------------------------------- - required time 0.667 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.906 - - - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_setup_paths.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_setup_paths.rpt deleted file mode 100644 index 090a5ca..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_setup_paths.rpt +++ /dev/null @@ -1,31976 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:12 2026 -| Host : fedora running 64-bit unknown -| Command : report_timing -delay_type max -sort_by group -max_paths 100 -nworst 10 -path_type full -input_pins -file /home/fallensigh/vivado_reports_nodsp/timing_setup_paths.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Timing Report - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/I0 - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/I4 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/I0 - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 r ext_ram_data_IOBUF[18]_inst/OBUFT/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/I5 - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 f u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/RADR0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/I0 - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/I4 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/I0 - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 r ext_ram_data_IOBUF[22]_inst/OBUFT/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 f ext_ram_data_IOBUF[21]_inst/OBUFT/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 f ext_ram_data_IOBUF[16]_inst/OBUFT/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 f u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/RADR1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/I1 - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/I2 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 r base_ram_data_IOBUF[1]_inst/OBUFT/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 f u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/RADR1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/I1 - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/I4 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/I0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 r ext_ram_data_IOBUF[20]_inst/OBUFT/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/I2 - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 f ext_ram_data_IOBUF[25]_inst/OBUFT/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.858 -2.418 - SLICE_X33Y70 FDRE 0.000 -2.418 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 f u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/I2 - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/I1 - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/I4 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/I3 - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 f u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 f u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/RADR1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/I0 - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/I3 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/I0 - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 r base_ram_data_IOBUF[28]_inst/OBUFT/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 f base_ram_data_IOBUF[21]_inst/OBUFT/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.954 -2.322 - SLICE_X7Y63 FDCE 0.000 -2.322 r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 f u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/I0 - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/I1 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/DI[3] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CI - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CI - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CI - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CI - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/CI - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 f u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/I5 - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 f u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/S[1] - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/I5 - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/I1 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/I2 - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 f base_ram_data_IOBUF[30]_inst/OBUFT/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 0.000 14.326 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 f u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 f u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/I0 - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/I2 - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/I3 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/I2 - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 f u_cpu/mem_stage/request_buffer_icacop_i_2/I2 - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 f u_cpu/exe_stage/request_buffer_dcacop_i_1/I0 - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_37__1/I0 - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 f u_cpu/exe_stage/mem_reg_reg_i_36__0/I2 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/I4 - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/I2 - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 r u_cpu/exe_stage/btb_add_entry_r_i_3/I2 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 r u_cpu/id_stage/btb_counter[15][1]_i_4/I1 - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 r u_cpu/btb/btb_pc[13][29]_i_1/I2 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.566 28.214 - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 f u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/I0 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/I0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/I4 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.725 28.373 - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 f u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/I0 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/I4 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/I3 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.812 28.460 - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 f u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/I1 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/I2 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/I3 - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.821 28.469 - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 r u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.774 -2.502 - SLICE_X65Y51 FDRE 0.000 -2.502 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/I3 - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/S[1] - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/I4 - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/I3 - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/I0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/I0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 r u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/S - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/I0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/I0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/I5 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/I5 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/I3 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/I2 - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/S[0] - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CI - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/I0 - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/I2 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/I0 - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/I2 - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 r u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/I5 - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 r u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/I5 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 r u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/I2 - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/S[0] - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 f u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/CI - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/I0 - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/I1 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/I3 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/I5 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/I4 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 f u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/I1 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/I4 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/I3 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - clock source latency -5.674 24.648 - propagated clock network latency - 3.731 28.379 - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 4.581ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.151ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.542 17.868 - clock pessimism -0.507 17.361 - clock uncertainty -0.071 17.290 - SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2] - ------------------------------------------------------------------- - required time 16.681 - arrival time -12.101 - ------------------------------------------------------------------- - slack 4.581 - -Slack (MET) : 5.171ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.547 17.873 - clock pessimism -0.507 17.366 - clock uncertainty -0.071 17.295 - SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0] - ------------------------------------------------------------------- - required time 16.686 - arrival time -11.515 - ------------------------------------------------------------------- - slack 5.171 - -Slack (MET) : 5.624ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2] - ------------------------------------------------------------------- - required time 16.782 - arrival time -11.158 - ------------------------------------------------------------------- - slack 5.624 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.835 18.160 - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 - ------------------------------------------------------------------- - slack 6.650 - -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 - ------------------------------------------------------------------- - slack 6.650 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5] - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.559 17.885 - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.558 17.884 - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.143ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.926 - ------------------------------------------------------------------- - slack 7.143 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[2] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.560 17.886 - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[3] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[28] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[29] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[30] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.262ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.919ns (logic 0.606ns (5.085%) route 11.313ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.121ns = ( 17.879 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.806 9.431 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y69 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.553 17.879 - clock pessimism -0.507 17.372 - clock uncertainty -0.071 17.301 - SLICE_X51Y69 FDCE (Recov_fdce_C_CLR) -0.609 16.692 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[31] - ------------------------------------------------------------------- - required time 16.692 - arrival time -9.431 - ------------------------------------------------------------------- - slack 7.262 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[24] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[25] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[26] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[27] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[28] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[29] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[30] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.267ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.917ns (logic 0.606ns (5.085%) route 11.311ns (94.915%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.804 9.429 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X53Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[31] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.429 - ------------------------------------------------------------------- - slack 7.267 - -Slack (MET) : 7.288ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.027 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[3] - ------------------------------------------------------------------- - required time 17.027 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.288 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[0] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[2] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[4] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.330ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.227ns (logic 0.606ns (4.956%) route 11.621ns (95.044%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.114 9.740 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X8Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.844 18.169 - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X8Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/bf2_count_reg[5] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.740 - ------------------------------------------------------------------- - slack 7.330 - -Slack (MET) : 7.345ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X3Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.924 18.249 - clock pessimism -0.507 17.743 - clock uncertainty -0.071 17.672 - SLICE_X3Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.063 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[1] - ------------------------------------------------------------------- - required time 17.063 - arrival time -9.718 - ------------------------------------------------------------------- - slack 7.345 - -Slack (MET) : 7.388ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.160ns (logic 0.606ns (4.983%) route 11.554ns (95.017%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.227ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.754ns = ( 18.246 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.047 9.673 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X5Y8 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.921 18.246 - clock pessimism -0.507 17.740 - clock uncertainty -0.071 17.669 - SLICE_X5Y8 FDCE (Recov_fdce_C_CLR) -0.609 17.060 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/bf1_count_reg[0] - ------------------------------------------------------------------- - required time 17.060 - arrival time -9.673 - ------------------------------------------------------------------- - slack 7.388 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[24] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[25] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[26] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.401ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.780ns (logic 0.606ns (5.144%) route 11.174ns (94.856%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.139ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.120ns = ( 17.880 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.667 9.293 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y68 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.554 17.880 - clock pessimism -0.507 17.373 - clock uncertainty -0.071 17.302 - SLICE_X51Y68 FDCE (Recov_fdce_C_CLR) -0.609 16.693 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[27] - ------------------------------------------------------------------- - required time 16.693 - arrival time -9.293 - ------------------------------------------------------------------- - slack 7.401 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[20] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[21] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[22] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.407ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.777ns (logic 0.606ns (5.146%) route 11.171ns (94.854%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.137ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.118ns = ( 17.882 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.664 9.289 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y67 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.556 17.882 - clock pessimism -0.507 17.375 - clock uncertainty -0.071 17.304 - SLICE_X51Y67 FDCE (Recov_fdce_C_CLR) -0.609 16.695 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[23] - ------------------------------------------------------------------- - required time 16.695 - arrival time -9.289 - ------------------------------------------------------------------- - slack 7.407 - -Slack (MET) : 7.431ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.206ns (logic 0.606ns (4.965%) route 11.600ns (95.035%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.751ns = ( 18.249 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.093 9.718 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X2Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.924 18.249 - clock pessimism -0.507 17.743 - clock uncertainty -0.071 17.672 - SLICE_X2Y3 FDCE (Recov_fdce_C_CLR) -0.523 17.149 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[4] - ------------------------------------------------------------------- - required time 17.149 - arrival time -9.718 - ------------------------------------------------------------------- - slack 7.431 - -Slack (MET) : 7.510ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.038ns (logic 0.606ns (5.034%) route 11.432ns (94.966%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.925 9.551 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/p_0_in - SLICE_X5Y3 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y3 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/mu_do_en_reg - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.551 - ------------------------------------------------------------------- - slack 7.510 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[16] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[17] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[18] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.574ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.610ns (logic 0.606ns (5.220%) route 11.004ns (94.780%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.497 9.122 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y66 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.557 17.883 - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X51Y66 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[19] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.122 - ------------------------------------------------------------------- - slack 7.574 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[2] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[3] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[8] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.609ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.942ns (logic 0.606ns (5.074%) route 11.336ns (94.926%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.829 9.455 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X1Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y0 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_count_reg[9] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.455 - ------------------------------------------------------------------- - slack 7.609 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[5] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[6] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[7] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[8] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.637ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.915ns (logic 0.606ns (5.086%) route 11.309ns (94.914%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.802 9.428 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X0Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X0Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[9] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.428 - ------------------------------------------------------------------- - slack 7.637 - -Slack (MET) : 7.638ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/p_0_in - SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/bf2_sp_en_reg - ------------------------------------------------------------------- - required time 17.108 - arrival time -9.470 - ------------------------------------------------------------------- - slack 7.638 - -Slack (MET) : 7.638ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.958ns (logic 0.606ns (5.068%) route 11.352ns (94.932%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.845 9.470 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X2Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X2Y1 FDCE (Recov_fdce_C_CLR) -0.565 17.108 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[3] - ------------------------------------------------------------------- - required time 17.108 - arrival time -9.470 - ------------------------------------------------------------------- - slack 7.638 - -Slack (MET) : 7.641ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.911ns (logic 0.606ns (5.088%) route 11.305ns (94.912%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns = ( 18.250 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.798 9.423 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/p_0_in - SLICE_X1Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.925 18.250 - clock pessimism -0.507 17.744 - clock uncertainty -0.071 17.673 - SLICE_X1Y1 FDCE (Recov_fdce_C_CLR) -0.609 17.064 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU5/di_count_reg[4] - ------------------------------------------------------------------- - required time 17.064 - arrival time -9.423 - ------------------------------------------------------------------- - slack 7.641 - -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[0] - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 - ------------------------------------------------------------------- - slack 7.668 - -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[1] - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 - ------------------------------------------------------------------- - slack 7.668 - -Slack (MET) : 7.668ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.881ns (logic 0.606ns (5.101%) route 11.275ns (94.899%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.753ns = ( 18.247 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.788 -2.488 - SLICE_X1Y101 FDCE 0.000 -2.488 r pll_clk.u_rst_sys/delay_reg[1]/C - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 r pll_clk.u_rst_sys/bf2_do_en_i_1/I0 - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.768 9.393 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X5Y6 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - clock source latency -5.674 14.326 - propagated clock network latency - 3.922 18.247 - clock pessimism -0.507 17.741 - clock uncertainty -0.071 17.670 - SLICE_X5Y6 FDCE (Recov_fdce_C_CLR) -0.609 17.061 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/di_count_reg[2] - ------------------------------------------------------------------- - required time 17.061 - arrival time -9.393 - ------------------------------------------------------------------- - slack 7.668 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.144ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.692ns (logic 0.704ns (2.454%) route 27.988ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 25.899 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.023 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.023 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.023 - ------------------------------------------------------------------- - slack 11.144 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.241ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.646ns (logic 0.704ns (2.458%) route 27.942ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 25.854 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/I1 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.978 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 25.978 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.978 - ------------------------------------------------------------------- - slack 11.241 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/I1 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.255ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.629ns (logic 0.704ns (2.459%) route 27.925ns (97.541%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 25.836 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/I1 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.960 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 25.960 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.960 - ------------------------------------------------------------------- - slack 11.255 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/I1 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.467ns (logic 0.704ns (2.473%) route 27.763ns (97.527%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 25.674 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/I1 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.798 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 25.798 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -25.798 - ------------------------------------------------------------------- - slack 11.371 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.396ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.488ns (logic 0.704ns (2.471%) route 27.784ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 25.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.819 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 25.819 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -25.819 - ------------------------------------------------------------------- - slack 11.396 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.485ns (logic 0.704ns (2.472%) route 27.781ns (97.528%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 25.692 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/I1 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.816 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 25.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.396 37.721 - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -25.816 - ------------------------------------------------------------------- - slack 11.403 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/I1 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.499ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.335ns (logic 0.704ns (2.485%) route 27.631ns (97.515%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.669ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.607 -2.669 - SLICE_X107Y119 FDCE 0.000 -2.669 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/C - SLICE_X107Y119 FDCE (Prop_fdce_C_Q) 0.456 -2.213 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep/Q - net (fo=109, routed) 5.879 3.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[2]_rep_n_0 - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I3 - SLICE_X157Y96 LUT5 (Prop_lut5_I3_O) 0.124 3.791 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.542 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/I1 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.666 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 25.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.394 37.719 - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.666 - ------------------------------------------------------------------- - slack 11.499 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/I1 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.395 37.720 - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/I1 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.391 37.716 - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - clock source latency -6.275 -6.275 - propagated clock network latency - 3.586 -2.690 - SLICE_X91Y121 FDCE 0.000 -2.690 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/I0 - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/I1 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - clock source latency -5.674 34.326 - propagated clock network latency - 3.393 37.718 - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - - - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_full.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_full.rpt deleted file mode 100644 index ef11c9c..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_full.rpt +++ /dev/null @@ -1,38485 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:10 2026 -| Host : fedora running 64-bit unknown -| Command : report_timing_summary -delay_type max -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_full.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Timing Summary Report - ------------------------------------------------------------------------------------------------- -| Timer Settings -| -------------- ------------------------------------------------------------------------------------------------- - - Enable Multi Corner Analysis : Yes - Enable Pessimism Removal : Yes - Pessimism Removal Resolution : Nearest Common Node - Enable Input Delay Default Clock : No - Enable Preset / Clear Arcs : No - Disable Flight Delays : No - Ignore I/O Paths : No - Timing Early Launch at Borrowing Latches : No - Borrow Time for Max Delay Exceptions : Yes - Merge Timing Exceptions : Yes - - Corner Analyze Analyze - Name Max Paths Min Paths - ------ --------- --------- - Slow Yes Yes - Fast Yes Yes - - - -check_timing report - -Table of Contents ------------------ -1. checking no_clock -2. checking constant_clock -3. checking pulse_width_clock -4. checking unconstrained_internal_endpoints -5. checking no_input_delay -6. checking no_output_delay -7. checking multiple_clock -8. checking generated_clocks -9. checking loops -10. checking partial_input_delay -11. checking partial_output_delay -12. checking latch_loops - -1. checking no_clock --------------------- - There are 0 register/latch pins with no clock. - - -2. checking constant_clock --------------------------- - There are 0 register/latch pins with constant_clock. - - -3. checking pulse_width_clock ------------------------------ - There are 0 register/latch pins which need pulse_width check - - -4. checking unconstrained_internal_endpoints --------------------------------------------- - There are 0 pins that are not constrained for maximum delay. - - There are 0 pins that are not constrained for maximum delay due to constant clock. - - -5. checking no_input_delay --------------------------- - There are 38 input ports with no input delay specified. (HIGH) - -UART_RX -UART_TX -dip_sw[0] -dip_sw[10] -dip_sw[11] -dip_sw[12] -dip_sw[13] -dip_sw[14] -dip_sw[15] -dip_sw[16] -dip_sw[17] -dip_sw[18] -dip_sw[19] -dip_sw[1] -dip_sw[20] -dip_sw[21] -dip_sw[22] -dip_sw[23] -dip_sw[24] -dip_sw[25] -dip_sw[26] -dip_sw[27] -dip_sw[28] -dip_sw[29] -dip_sw[2] -dip_sw[30] -dip_sw[31] -dip_sw[3] -dip_sw[4] -dip_sw[5] -dip_sw[6] -dip_sw[7] -dip_sw[8] -dip_sw[9] -touch_btn[0] -touch_btn[1] -touch_btn[2] -touch_btn[3] - - There are 0 input ports with no input delay but user has a false path constraint. - - -6. checking no_output_delay ---------------------------- - There are 40 ports with no output delay specified. (HIGH) - -UART_RX -UART_TX -dpy0[0] -dpy0[1] -dpy0[2] -dpy0[3] -dpy0[4] -dpy0[5] -dpy0[6] -dpy0[7] -dpy1[0] -dpy1[1] -dpy1[2] -dpy1[3] -dpy1[4] -dpy1[5] -dpy1[6] -dpy1[7] -leds[0] -leds[10] -leds[11] -leds[12] -leds[13] -leds[14] -leds[15] -leds[1] -leds[2] -leds[3] -leds[4] -leds[5] -leds[6] -leds[7] -leds[8] -leds[9] -video_de -video_hsync -video_red[0] -video_red[1] -video_red[2] -video_vsync - - There are 0 ports with no output delay but user has a false path constraint - - There are 0 ports with no output delay but with a timing clock defined on it or propagating through it - - -7. checking multiple_clock --------------------------- - There are 0 register/latch pins with multiple clocks. - - -8. checking generated_clocks ----------------------------- - There are 0 generated clocks that are not connected to a clock source. - - -9. checking loops ------------------ - There are 0 combinational loops in the design. - - -10. checking partial_input_delay --------------------------------- - There are 0 input ports with partial input delay specified. - - -11. checking partial_output_delay ---------------------------------- - There are 0 ports with partial output delay specified. - - -12. checking latch_loops ------------------------- - There are 0 combinational latch loops in the design through latch input - - - ------------------------------------------------------------------------------------------------- -| Design Timing Summary -| --------------------- ------------------------------------------------------------------------------------------------- - - WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints - ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 0.167 0.000 0 115177 7.000 0.000 0 42610 - - -All user specified timing constraints are met. - - ------------------------------------------------------------------------------------------------- -| Clock Summary -| ------------- ------------------------------------------------------------------------------------------------- - -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk {0.000 10.000} 20.000 50.000 - clkfbout_clk_pll {0.000 10.000} 20.000 50.000 - cpu_clk {0.000 15.161} 30.323 32.979 - mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 - sys_clk {0.000 10.000} 20.000 50.000 - - ------------------------------------------------------------------------------------------------- -| Intra Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk 7.000 0.000 0 1 - clkfbout_clk_pll 17.845 0.000 0 3 - cpu_clk 2.716 0.000 0 17197 13.911 0.000 0 6486 - mlkem_clk_clk_pll 10.807 0.000 0 48474 18.750 0.000 0 26131 - sys_clk 0.167 0.000 0 22818 8.750 0.000 0 9989 - - ------------------------------------------------------------------------------------------------- -| Inter Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- -sys_clk mlkem_clk_clk_pll 14.363 0.000 0 108 -mlkem_clk_clk_pll sys_clk 16.175 0.000 0 59 - - ------------------------------------------------------------------------------------------------- -| Other Path Groups Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints ----------- ---------- -------- ------- ------- --------------------- ------------------- -**async_default** cpu_clk cpu_clk 25.793 0.000 0 67 -**async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 23.497 0.000 0 25694 -**async_default** sys_clk mlkem_clk_clk_pll 9.156 0.000 0 4 -**async_default** mlkem_clk_clk_pll sys_clk 11.249 0.000 0 2 -**async_default** sys_clk sys_clk 4.581 0.000 0 886 - - ------------------------------------------------------------------------------------------------- -| User Ignored Path Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock ----------- ---------- -------- -(none) sys_clk cpu_clk -(none) cpu_clk sys_clk - - ------------------------------------------------------------------------------------------------- -| Unconstrained Path Table -| ------------------------ ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock ----------- ---------- -------- -(none) clkfbout_clk_pll -(none) sys_clk -(none) sys_clk - - ------------------------------------------------------------------------------------------------- -| Timing Details -| -------------- ------------------------------------------------------------------------------------------------- - - ---------------------------------------------------------------------------------------------------- -From Clock: clk - To Clock: clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clk -Waveform(ns): { 0.000 10.000 } -Period(ns): 20.000 -Sources: { clk } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 - - - ---------------------------------------------------------------------------------------------------- -From Clock: clkfbout_clk_pll - To Clock: clkfbout_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clkfbout_clk_pll -Waveform(ns): { 0.000 10.000 } -Period(ns): 20.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I -Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT -Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN -Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN -Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT - - - ---------------------------------------------------------------------------------------------------- -From Clock: cpu_clk - To Clock: cpu_clk - -Setup : 0 Failing Endpoints, Worst Slack 2.716ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][13]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][13] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][14]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][14]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][14] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][15]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][15] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][16]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][16]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][16] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][1]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][1]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.716ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][28]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.258ns (logic 5.748ns (21.087%) route 21.510ns (78.913%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 1.481 24.757 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X98Y50 FDRE r u_cpu/btb/btb_pc_reg[13][28]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X98Y50 FDRE (Setup_fdre_C_CE) -0.169 27.473 u_cpu/btb/btb_pc_reg[13][28] - ------------------------------------------------------------------- - required time 27.473 - arrival time -24.757 - ------------------------------------------------------------------- - slack 2.716 - -Slack (MET) : 2.751ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.628ns (logic 6.845ns (24.775%) route 20.783ns (75.225%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=6 LUT6=16 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.497 23.244 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y24 LUT6 (Prop_lut6_I0_O) 0.124 23.368 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_9/O - net (fo=1, routed) 0.954 24.322 u_cpu/id_stage/ds_to_es_bus_r[170]_i_9_n_0 - SLICE_X47Y22 LUT6 (Prop_lut6_I0_O) 0.124 24.446 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_5/O - net (fo=1, routed) 0.557 25.003 u_cpu/id_stage/ds_to_es_bus_r[170]_i_5_n_0 - SLICE_X46Y24 LUT6 (Prop_lut6_I4_O) 0.124 25.127 r u_cpu/id_stage/ds_to_es_bus_r[170]_i_1/O - net (fo=1, routed) 0.000 25.127 u_cpu/exe_stage/ds_to_es_bus[120] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[170]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.077 27.878 u_cpu/exe_stage/ds_to_es_bus_r_reg[170] - ------------------------------------------------------------------- - required time 27.878 - arrival time -25.127 - ------------------------------------------------------------------- - slack 2.751 - -Slack (MET) : 2.754ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.666ns (logic 6.845ns (24.741%) route 20.821ns (75.259%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.323 23.087 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X50Y22 LUT4 (Prop_lut4_I0_O) 0.124 23.211 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_11/O - net (fo=1, routed) 0.816 24.026 u_cpu/id_stage/ds_to_es_bus_r[177]_i_11_n_0 - SLICE_X46Y22 LUT5 (Prop_lut5_I4_O) 0.124 24.150 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_4/O - net (fo=1, routed) 0.890 25.041 u_cpu/id_stage/ds_to_es_bus_r[177]_i_4_n_0 - SLICE_X41Y26 LUT6 (Prop_lut6_I3_O) 0.124 25.165 r u_cpu/id_stage/ds_to_es_bus_r[177]_i_1/O - net (fo=1, routed) 0.000 25.165 u_cpu/exe_stage/ds_to_es_bus[127] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[177]/C - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.031 27.919 u_cpu/exe_stage/ds_to_es_bus_r_reg[177] - ------------------------------------------------------------------- - required time 27.919 - arrival time -25.165 - ------------------------------------------------------------------- - slack 2.754 - -Slack (MET) : 2.789ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.640ns (logic 7.062ns (25.550%) route 20.578ns (74.450%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.005 22.823 u_cpu/u_csr/ds_to_es_bus_r[184]_i_4_2 - SLICE_X44Y27 LUT2 (Prop_lut2_I1_O) 0.117 22.940 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_11/O - net (fo=1, routed) 0.956 23.896 u_cpu/u_csr/ds_to_es_bus_r[184]_i_11_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.348 24.244 r u_cpu/u_csr/ds_to_es_bus_r[184]_i_4/O - net (fo=1, routed) 0.771 25.014 u_cpu/id_stage/ds_to_es_bus_r_reg[184] - SLICE_X39Y34 LUT6 (Prop_lut6_I3_O) 0.124 25.138 r u_cpu/id_stage/ds_to_es_bus_r[184]_i_1/O - net (fo=1, routed) 0.000 25.138 u_cpu/exe_stage/ds_to_es_bus[134] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[184]/C - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.031 27.928 u_cpu/exe_stage/ds_to_es_bus_r_reg[184] - ------------------------------------------------------------------- - required time 27.928 - arrival time -25.138 - ------------------------------------------------------------------- - slack 2.789 - -Slack (MET) : 2.822ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.515ns (logic 7.073ns (25.706%) route 20.442ns (74.294%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/u_csr/ds_to_es_bus_r[164]_i_4 - SLICE_X44Y31 LUT2 (Prop_lut2_I1_O) 0.148 23.213 r u_cpu/u_csr/ds_to_es_bus_r[164]_i_15/O - net (fo=1, routed) 0.855 24.068 u_cpu/id_stage/ds_to_es_bus_r_reg[164]_1 - SLICE_X44Y29 LUT6 (Prop_lut6_I4_O) 0.328 24.396 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_4/O - net (fo=1, routed) 0.493 24.889 u_cpu/id_stage/ds_to_es_bus_r[164]_i_4_n_0 - SLICE_X45Y29 LUT6 (Prop_lut6_I3_O) 0.124 25.013 r u_cpu/id_stage/ds_to_es_bus_r[164]_i_1/O - net (fo=1, routed) 0.000 25.013 u_cpu/exe_stage/ds_to_es_bus[114] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[164]/C - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.029 27.836 u_cpu/exe_stage/ds_to_es_bus_r_reg[164] - ------------------------------------------------------------------- - required time 27.836 - arrival time -25.013 - ------------------------------------------------------------------- - slack 2.822 - -Slack (MET) : 2.959ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.468ns (logic 7.073ns (25.750%) route 20.395ns (74.250%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.854ns = ( 28.469 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O - net (fo=27, routed) 1.068 23.412 u_cpu/id_stage/fs_to_ds_bus_r_reg[47]_3 - SLICE_X45Y35 LUT4 (Prop_lut4_I2_O) 0.150 23.562 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_2/O - net (fo=1, routed) 1.078 24.640 u_cpu/id_stage/ds_to_es_bus_r[168]_i_2_n_0 - SLICE_X39Y34 LUT6 (Prop_lut6_I1_O) 0.326 24.966 r u_cpu/id_stage/ds_to_es_bus_r[168]_i_1/O - net (fo=1, routed) 0.000 24.966 u_cpu/exe_stage/ds_to_es_bus[118] - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.975 28.469 u_cpu/exe_stage/cpu_clk - SLICE_X39Y34 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[168]/C - clock pessimism -0.498 27.971 - clock uncertainty -0.074 27.897 - SLICE_X39Y34 FDRE (Setup_fdre_C_D) 0.029 27.926 u_cpu/exe_stage/ds_to_es_bus_r_reg[168] - ------------------------------------------------------------------- - required time 27.926 - arrival time -24.966 - ------------------------------------------------------------------- - slack 2.959 - -Slack (MET) : 3.081ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.303ns (logic 7.073ns (25.905%) route 20.230ns (74.095%)) - Logic Levels: 32 (CARRY4=5 LUT3=2 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.059ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.945ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 1.096 21.904 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y31 LUT6 (Prop_lut6_I5_O) 0.124 22.028 f u_cpu/id_stage/ds_to_es_bus_r[188]_i_19/O - net (fo=4, routed) 0.942 22.969 u_cpu/id_stage/ds_to_es_bus_r[188]_i_19_n_0 - SLICE_X43Y28 LUT3 (Prop_lut3_I2_O) 0.150 23.119 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_11/O - net (fo=1, routed) 0.652 23.771 u_cpu/id_stage/ds_to_es_bus_r[181]_i_11_n_0 - SLICE_X43Y28 LUT6 (Prop_lut6_I5_O) 0.326 24.097 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_4/O - net (fo=1, routed) 0.581 24.678 u_cpu/id_stage/ds_to_es_bus_r[181]_i_4_n_0 - SLICE_X46Y28 LUT6 (Prop_lut6_I3_O) 0.124 24.802 r u_cpu/id_stage/ds_to_es_bus_r[181]_i_1/O - net (fo=1, routed) 0.000 24.802 u_cpu/exe_stage/ds_to_es_bus[131] - SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_cpu/exe_stage/cpu_clk - SLICE_X46Y28 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[181]/C - clock pessimism -0.498 27.880 - clock uncertainty -0.074 27.806 - SLICE_X46Y28 FDRE (Setup_fdre_C_D) 0.077 27.883 u_cpu/exe_stage/ds_to_es_bus_r_reg[181] - ------------------------------------------------------------------- - required time 27.883 - arrival time -24.802 - ------------------------------------------------------------------- - slack 3.081 - -Slack (MET) : 3.101ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.282ns (logic 6.845ns (25.090%) route 20.437ns (74.910%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O - net (fo=15, routed) 1.068 23.250 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 - SLICE_X43Y32 LUT4 (Prop_lut4_I2_O) 0.124 23.374 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_2/O - net (fo=1, routed) 1.282 24.656 u_cpu/id_stage/ds_to_es_bus_r[176]_i_2_n_0 - SLICE_X46Y24 LUT6 (Prop_lut6_I1_O) 0.124 24.780 r u_cpu/id_stage/ds_to_es_bus_r[176]_i_1/O - net (fo=1, routed) 0.000 24.780 u_cpu/exe_stage/ds_to_es_bus[126] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[176]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.081 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[176] - ------------------------------------------------------------------- - required time 27.882 - arrival time -24.780 - ------------------------------------------------------------------- - slack 3.101 - -Slack (MET) : 3.107ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.229ns (logic 6.845ns (25.138%) route 20.384ns (74.862%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 1.277 23.041 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X51Y27 LUT4 (Prop_lut4_I2_O) 0.124 23.165 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_12/O - net (fo=1, routed) 0.649 23.814 u_cpu/id_stage/ds_to_es_bus_r[186]_i_12_n_0 - SLICE_X47Y27 LUT5 (Prop_lut5_I0_O) 0.124 23.938 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_5/O - net (fo=1, routed) 0.666 24.604 u_cpu/id_stage/ds_to_es_bus_r[186]_i_5_n_0 - SLICE_X45Y27 LUT6 (Prop_lut6_I4_O) 0.124 24.728 r u_cpu/id_stage/ds_to_es_bus_r[186]_i_1/O - net (fo=1, routed) 0.000 24.728 u_cpu/exe_stage/ds_to_es_bus[136] - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[186]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[186] - ------------------------------------------------------------------- - required time 27.835 - arrival time -24.728 - ------------------------------------------------------------------- - slack 3.107 - -Slack (MET) : 3.111ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.278ns (logic 6.845ns (25.094%) route 20.433ns (74.906%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.886 21.694 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.818 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_15/O - net (fo=32, routed) 1.127 22.946 u_cpu/id_stage/fs_to_ds_bus_r_reg[46]_0 - SLICE_X48Y33 LUT4 (Prop_lut4_I0_O) 0.124 23.070 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_12/O - net (fo=1, routed) 0.656 23.726 u_cpu/id_stage/ds_to_es_bus_r[167]_i_12_n_0 - SLICE_X46Y30 LUT6 (Prop_lut6_I1_O) 0.124 23.850 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_5/O - net (fo=1, routed) 0.803 24.652 u_cpu/id_stage/ds_to_es_bus_r[167]_i_5_n_0 - SLICE_X44Y33 LUT6 (Prop_lut6_I4_O) 0.124 24.776 r u_cpu/id_stage/ds_to_es_bus_r[167]_i_1/O - net (fo=1, routed) 0.000 24.776 u_cpu/exe_stage/ds_to_es_bus[117] - SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk - SLICE_X44Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[167]/C - clock pessimism -0.498 27.885 - clock uncertainty -0.074 27.811 - SLICE_X44Y33 FDRE (Setup_fdre_C_D) 0.077 27.888 u_cpu/exe_stage/ds_to_es_bus_r_reg[167] - ------------------------------------------------------------------- - required time 27.888 - arrival time -24.776 - ------------------------------------------------------------------- - slack 3.111 - -Slack (MET) : 3.117ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.301ns (logic 7.095ns (25.988%) route 20.206ns (74.012%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.863ns = ( 28.460 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.780 22.220 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X42Y31 LUT6 (Prop_lut6_I0_O) 0.124 22.344 f u_cpu/id_stage/ds_to_es_bus_r[189]_i_9/O - net (fo=27, routed) 0.883 23.227 u_cpu/u_csr/ds_to_es_bus_r_reg[162]_0 - SLICE_X44Y32 LUT2 (Prop_lut2_I1_O) 0.150 23.377 r u_cpu/u_csr/ds_to_es_bus_r[171]_i_3/O - net (fo=1, routed) 1.075 24.452 u_cpu/id_stage/ds_to_es_bus_r_reg[171] - SLICE_X41Y26 LUT6 (Prop_lut6_I2_O) 0.348 24.800 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_1/O - net (fo=1, routed) 0.000 24.800 u_cpu/exe_stage/ds_to_es_bus[121] - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.966 28.460 u_cpu/exe_stage/cpu_clk - SLICE_X41Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[171]/C - clock pessimism -0.498 27.962 - clock uncertainty -0.074 27.888 - SLICE_X41Y26 FDRE (Setup_fdre_C_D) 0.029 27.917 u_cpu/exe_stage/ds_to_es_bus_r_reg[171] - ------------------------------------------------------------------- - required time 27.917 - arrival time -24.800 - ------------------------------------------------------------------- - slack 3.117 - -Slack (MET) : 3.132ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.293ns (logic 7.073ns (25.915%) route 20.220ns (74.085%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.858ns = ( 28.465 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 0.818 22.446 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X40Y24 LUT5 (Prop_lut5_I0_O) 0.326 22.772 r u_cpu/u_csr/ds_to_es_bus_r[187]_i_11/O - net (fo=1, routed) 0.976 23.747 u_cpu/id_stage/ds_to_es_bus_r_reg[187]_0 - SLICE_X40Y30 LUT4 (Prop_lut4_I2_O) 0.124 23.871 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_5/O - net (fo=1, routed) 0.796 24.668 u_cpu/id_stage/ds_to_es_bus_r[187]_i_5_n_0 - SLICE_X41Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.792 r u_cpu/id_stage/ds_to_es_bus_r[187]_i_1/O - net (fo=1, routed) 0.000 24.792 u_cpu/exe_stage/ds_to_es_bus[137] - SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.971 28.465 u_cpu/exe_stage/cpu_clk - SLICE_X41Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[187]/C - clock pessimism -0.498 27.967 - clock uncertainty -0.074 27.893 - SLICE_X41Y31 FDRE (Setup_fdre_C_D) 0.031 27.924 u_cpu/exe_stage/ds_to_es_bus_r_reg[187] - ------------------------------------------------------------------- - required time 27.924 - arrival time -24.792 - ------------------------------------------------------------------- - slack 3.132 - -Slack (MET) : 3.146ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.188ns (logic 6.949ns (25.559%) route 20.239ns (74.441%)) - Logic Levels: 31 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.847 20.893 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y30 LUT5 (Prop_lut5_I2_O) 0.124 21.017 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_15/O - net (fo=8, routed) 1.169 22.186 u_cpu/id_stage/fs_to_ds_bus_r_reg[49]_1 - SLICE_X44Y30 LUT2 (Prop_lut2_I1_O) 0.148 22.334 f u_cpu/id_stage/ds_to_es_bus_r[183]_i_12/O - net (fo=6, routed) 0.893 23.226 u_cpu/id_stage/ds_to_es_bus_r[183]_i_12_n_0 - SLICE_X41Y29 LUT6 (Prop_lut6_I3_O) 0.328 23.554 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_3/O - net (fo=1, routed) 1.008 24.562 u_cpu/id_stage/ds_to_es_bus_r[180]_i_3_n_0 - SLICE_X43Y26 LUT6 (Prop_lut6_I2_O) 0.124 24.686 r u_cpu/id_stage/ds_to_es_bus_r[180]_i_1/O - net (fo=1, routed) 0.000 24.686 u_cpu/exe_stage/ds_to_es_bus[130] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[180]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.032 27.833 u_cpu/exe_stage/ds_to_es_bus_r_reg[180] - ------------------------------------------------------------------- - required time 27.833 - arrival time -24.686 - ------------------------------------------------------------------- - slack 3.146 - -Slack (MET) : 3.154ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.182ns (logic 6.845ns (25.182%) route 20.337ns (74.818%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O - net (fo=32, routed) 1.325 23.002 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 - SLICE_X46Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.126 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_10/O - net (fo=1, routed) 0.502 23.627 u_cpu/id_stage/ds_to_es_bus_r[185]_i_10_n_0 - SLICE_X46Y27 LUT6 (Prop_lut6_I5_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_4/O - net (fo=1, routed) 0.805 24.556 u_cpu/id_stage/ds_to_es_bus_r[185]_i_4_n_0 - SLICE_X45Y27 LUT6 (Prop_lut6_I3_O) 0.124 24.680 r u_cpu/id_stage/ds_to_es_bus_r[185]_i_1/O - net (fo=1, routed) 0.000 24.680 u_cpu/exe_stage/ds_to_es_bus[135] - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X45Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[185]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X45Y27 FDRE (Setup_fdre_C_D) 0.031 27.835 u_cpu/exe_stage/ds_to_es_bus_r_reg[185] - ------------------------------------------------------------------- - required time 27.835 - arrival time -24.680 - ------------------------------------------------------------------- - slack 3.154 - -Slack (MET) : 3.179ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.162ns (logic 6.845ns (25.201%) route 20.317ns (74.799%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.064ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns = ( 28.383 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.745 21.553 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I3_O) 0.124 21.677 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_18/O - net (fo=32, routed) 1.184 22.860 u_cpu/id_stage/ds_to_es_bus_r[193]_i_18_n_0 - SLICE_X46Y31 LUT4 (Prop_lut4_I0_O) 0.124 22.984 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_13/O - net (fo=1, routed) 0.785 23.769 u_cpu/id_stage/ds_to_es_bus_r[189]_i_13_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.893 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_4/O - net (fo=1, routed) 0.643 24.536 u_cpu/id_stage/ds_to_es_bus_r[189]_i_4_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I3_O) 0.124 24.660 r u_cpu/id_stage/ds_to_es_bus_r[189]_i_1/O - net (fo=1, routed) 0.000 24.660 u_cpu/exe_stage/ds_to_es_bus[139] - SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.889 28.383 u_cpu/exe_stage/cpu_clk - SLICE_X47Y33 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[189]/C - clock pessimism -0.498 27.885 - clock uncertainty -0.074 27.811 - SLICE_X47Y33 FDRE (Setup_fdre_C_D) 0.029 27.840 u_cpu/exe_stage/ds_to_es_bus_r_reg[189] - ------------------------------------------------------------------- - required time 27.840 - arrival time -24.660 - ------------------------------------------------------------------- - slack 3.179 - -Slack (MET) : 3.179ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.160ns (logic 7.073ns (26.042%) route 20.087ns (73.958%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.060ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.379 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.194 22.822 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X50Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.148 r u_cpu/u_csr/ds_to_es_bus_r[190]_i_6/O - net (fo=1, routed) 0.700 23.848 u_cpu/id_stage/ds_to_es_bus_r_reg[190] - SLICE_X47Y30 LUT6 (Prop_lut6_I2_O) 0.124 23.972 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_2/O - net (fo=1, routed) 0.562 24.534 u_cpu/id_stage/ds_to_es_bus_r[190]_i_2_n_0 - SLICE_X45Y29 LUT5 (Prop_lut5_I1_O) 0.124 24.658 r u_cpu/id_stage/ds_to_es_bus_r[190]_i_1/O - net (fo=1, routed) 0.000 24.658 u_cpu/exe_stage/ds_to_es_bus[140] - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.885 28.379 u_cpu/exe_stage/cpu_clk - SLICE_X45Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[190]/C - clock pessimism -0.498 27.881 - clock uncertainty -0.074 27.807 - SLICE_X45Y29 FDRE (Setup_fdre_C_D) 0.031 27.838 u_cpu/exe_stage/ds_to_es_bus_r_reg[190] - ------------------------------------------------------------------- - required time 27.838 - arrival time -24.658 - ------------------------------------------------------------------- - slack 3.179 - -Slack (MET) : 3.222ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.251ns (logic 6.845ns (25.118%) route 20.406ns (74.882%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=6 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.831 21.640 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.764 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_17/O - net (fo=32, routed) 0.885 22.649 u_cpu/id_stage/fs_to_ds_bus_r_reg[42]_2 - SLICE_X39Y35 LUT4 (Prop_lut4_I2_O) 0.124 22.773 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_9/O - net (fo=1, routed) 1.128 23.901 u_cpu/id_stage/ds_to_es_bus_r[162]_i_9_n_0 - SLICE_X39Y33 LUT6 (Prop_lut6_I2_O) 0.124 24.025 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_4/O - net (fo=1, routed) 0.600 24.625 u_cpu/id_stage/ds_to_es_bus_r[162]_i_4_n_0 - SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.749 r u_cpu/id_stage/ds_to_es_bus_r[162]_i_1/O - net (fo=1, routed) 0.000 24.749 u_cpu/exe_stage/ds_to_es_bus[112] - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[162]/C - clock pessimism -0.498 27.969 - clock uncertainty -0.074 27.895 - SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.077 27.972 u_cpu/exe_stage/ds_to_es_bus_r_reg[162] - ------------------------------------------------------------------- - required time 27.972 - arrival time -24.749 - ------------------------------------------------------------------- - slack 3.222 - -Slack (MET) : 3.225ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.158ns (logic 6.845ns (25.204%) route 20.313ns (74.796%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.058ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O - net (fo=12, routed) 1.248 22.679 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_6 - SLICE_X48Y34 LUT4 (Prop_lut4_I2_O) 0.124 22.803 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_8/O - net (fo=1, routed) 0.983 23.787 u_cpu/id_stage/ds_to_es_bus_r[163]_i_8_n_0 - SLICE_X42Y34 LUT6 (Prop_lut6_I0_O) 0.124 23.911 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_4/O - net (fo=1, routed) 0.622 24.533 u_cpu/id_stage/ds_to_es_bus_r[163]_i_4_n_0 - SLICE_X42Y29 LUT6 (Prop_lut6_I3_O) 0.124 24.657 r u_cpu/id_stage/ds_to_es_bus_r[163]_i_1/O - net (fo=1, routed) 0.000 24.657 u_cpu/exe_stage/ds_to_es_bus[113] - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[163]/C - clock pessimism -0.498 27.879 - clock uncertainty -0.074 27.805 - SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.077 27.882 u_cpu/exe_stage/ds_to_es_bus_r_reg[163] - ------------------------------------------------------------------- - required time 27.882 - arrival time -24.657 - ------------------------------------------------------------------- - slack 3.225 - -Slack (MET) : 3.228ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.103ns (logic 7.041ns (25.978%) route 20.062ns (74.021%)) - Logic Levels: 32 (CARRY4=5 LUT2=1 LUT3=1 LUT4=2 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.499 21.307 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT5 (Prop_lut5_I4_O) 0.124 21.431 r u_cpu/id_stage/ds_to_es_bus_r[171]_i_9/O - net (fo=12, routed) 0.831 22.262 u_cpu/u_csr/ds_to_es_bus_r[166]_i_4_0 - SLICE_X45Y31 LUT2 (Prop_lut2_I1_O) 0.118 22.380 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_8/O - net (fo=1, routed) 0.965 23.345 u_cpu/u_csr/ds_to_es_bus_r[165]_i_8_n_0 - SLICE_X42Y28 LUT6 (Prop_lut6_I0_O) 0.326 23.671 r u_cpu/u_csr/ds_to_es_bus_r[165]_i_4/O - net (fo=1, routed) 0.806 24.478 u_cpu/id_stage/ds_to_es_bus_r_reg[165] - SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.602 r u_cpu/id_stage/ds_to_es_bus_r[165]_i_1/O - net (fo=1, routed) 0.000 24.602 u_cpu/exe_stage/ds_to_es_bus[115] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[165]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[165] - ------------------------------------------------------------------- - required time 27.830 - arrival time -24.602 - ------------------------------------------------------------------- - slack 3.228 - -Slack (MET) : 3.306ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.027ns (logic 6.845ns (25.326%) route 20.182ns (74.674%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.269 23.016 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X50Y27 LUT4 (Prop_lut4_I0_O) 0.124 23.140 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_11/O - net (fo=1, routed) 0.487 23.627 u_cpu/id_stage/ds_to_es_bus_r[174]_i_11_n_0 - SLICE_X45Y26 LUT5 (Prop_lut5_I4_O) 0.124 23.751 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_4/O - net (fo=1, routed) 0.651 24.402 u_cpu/id_stage/ds_to_es_bus_r[174]_i_4_n_0 - SLICE_X43Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.526 r u_cpu/id_stage/ds_to_es_bus_r[174]_i_1/O - net (fo=1, routed) 0.000 24.526 u_cpu/exe_stage/ds_to_es_bus[124] - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X43Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[174]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X43Y26 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[174] - ------------------------------------------------------------------- - required time 27.832 - arrival time -24.526 - ------------------------------------------------------------------- - slack 3.306 - -Slack (MET) : 3.315ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.066ns (logic 6.845ns (25.290%) route 20.221ns (74.710%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.056ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.948ns = ( 28.375 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.101 22.527 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X46Y22 LUT5 (Prop_lut5_I2_O) 0.124 22.651 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_10/O - net (fo=1, routed) 0.985 23.636 u_cpu/id_stage/ds_to_es_bus_r[178]_i_10_n_0 - SLICE_X46Y26 LUT6 (Prop_lut6_I2_O) 0.124 23.760 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_4/O - net (fo=1, routed) 0.680 24.440 u_cpu/id_stage/ds_to_es_bus_r[178]_i_4_n_0 - SLICE_X46Y26 LUT6 (Prop_lut6_I3_O) 0.124 24.564 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_1/O - net (fo=1, routed) 0.000 24.564 u_cpu/exe_stage/ds_to_es_bus[128] - SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.881 28.375 u_cpu/exe_stage/cpu_clk - SLICE_X46Y26 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[178]/C - clock pessimism -0.498 27.877 - clock uncertainty -0.074 27.803 - SLICE_X46Y26 FDRE (Setup_fdre_C_D) 0.077 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[178] - ------------------------------------------------------------------- - required time 27.880 - arrival time -24.564 - ------------------------------------------------------------------- - slack 3.315 - -Slack (MET) : 3.348ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.129ns (logic 6.845ns (25.231%) route 20.284ns (74.769%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.856ns = ( 28.467 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.814 21.623 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X40Y29 LUT6 (Prop_lut6_I4_O) 0.124 21.747 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_12/O - net (fo=32, routed) 1.318 23.065 u_cpu/id_stage/fs_to_ds_bus_r_reg[43]_5 - SLICE_X44Y31 LUT4 (Prop_lut4_I0_O) 0.124 23.189 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_7/O - net (fo=1, routed) 0.553 23.742 u_cpu/id_stage/ds_to_es_bus_r[166]_i_7_n_0 - SLICE_X40Y31 LUT5 (Prop_lut5_I0_O) 0.124 23.866 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_3/O - net (fo=1, routed) 0.638 24.504 u_cpu/id_stage/ds_to_es_bus_r[166]_i_3_n_0 - SLICE_X40Y32 LUT6 (Prop_lut6_I2_O) 0.124 24.628 r u_cpu/id_stage/ds_to_es_bus_r[166]_i_1/O - net (fo=1, routed) 0.000 24.628 u_cpu/exe_stage/ds_to_es_bus[116] - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.973 28.467 u_cpu/exe_stage/cpu_clk - SLICE_X40Y32 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[166]/C - clock pessimism -0.498 27.969 - clock uncertainty -0.074 27.895 - SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.081 27.976 u_cpu/exe_stage/ds_to_es_bus_r_reg[166] - ------------------------------------------------------------------- - required time 27.976 - arrival time -24.628 - ------------------------------------------------------------------- - slack 3.348 - -Slack (MET) : 3.380ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 27.001ns (logic 6.845ns (25.351%) route 20.156ns (74.649%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=7 LUT6=15 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.508 21.316 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X39Y30 LUT6 (Prop_lut6_I2_O) 0.124 21.440 f u_cpu/id_stage/ds_to_es_bus_r[192]_i_14/O - net (fo=20, routed) 0.619 22.058 u_cpu/id_stage/ds_to_es_bus_r[192]_i_14_n_0 - SLICE_X41Y30 LUT6 (Prop_lut6_I0_O) 0.124 22.182 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_10/O - net (fo=15, routed) 1.094 23.277 u_cpu/id_stage/ds_to_es_bus_r[193]_i_10_n_0 - SLICE_X47Y33 LUT6 (Prop_lut6_I5_O) 0.124 23.401 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_2/O - net (fo=1, routed) 0.974 24.375 u_cpu/id_stage/ds_to_es_bus_r[179]_i_2_n_0 - SLICE_X46Y24 LUT5 (Prop_lut5_I1_O) 0.124 24.499 r u_cpu/id_stage/ds_to_es_bus_r[179]_i_1/O - net (fo=1, routed) 0.000 24.499 u_cpu/exe_stage/ds_to_es_bus[129] - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X46Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[179]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X46Y24 FDRE (Setup_fdre_C_D) 0.079 27.880 u_cpu/exe_stage/ds_to_es_bus_r_reg[179] - ------------------------------------------------------------------- - required time 27.880 - arrival time -24.499 - ------------------------------------------------------------------- - slack 3.380 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][10]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][10]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][10] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][18]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][18]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][18] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][23]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][23]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][23] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.393ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][27]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.741ns (logic 5.748ns (21.495%) route 20.993ns (78.505%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.963 24.239 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X115Y43 FDRE r u_cpu/btb/btb_pc_reg[13][27]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X115Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][27] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.239 - ------------------------------------------------------------------- - slack 3.393 - -Slack (MET) : 3.408ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.974ns (logic 7.073ns (26.222%) route 19.901ns (73.778%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.057ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.947ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.025 22.652 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X45Y28 LUT5 (Prop_lut5_I0_O) 0.326 22.978 r u_cpu/u_csr/ds_to_es_bus_r[182]_i_8/O - net (fo=1, routed) 0.653 23.631 u_cpu/id_stage/ds_to_es_bus_r_reg[182] - SLICE_X44Y28 LUT6 (Prop_lut6_I1_O) 0.124 23.755 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_2/O - net (fo=1, routed) 0.593 24.348 u_cpu/id_stage/ds_to_es_bus_r[182]_i_2_n_0 - SLICE_X44Y27 LUT6 (Prop_lut6_I1_O) 0.124 24.472 r u_cpu/id_stage/ds_to_es_bus_r[182]_i_1/O - net (fo=1, routed) 0.000 24.472 u_cpu/exe_stage/ds_to_es_bus[132] - SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_cpu/exe_stage/cpu_clk - SLICE_X44Y27 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[182]/C - clock pessimism -0.498 27.878 - clock uncertainty -0.074 27.804 - SLICE_X44Y27 FDRE (Setup_fdre_C_D) 0.077 27.881 u_cpu/exe_stage/ds_to_es_bus_r_reg[182] - ------------------------------------------------------------------- - required time 27.881 - arrival time -24.472 - ------------------------------------------------------------------- - slack 3.408 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][29]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][29]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][29] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][2]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][2]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][2] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][4]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][4]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][4] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.421ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][7]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.712ns (logic 5.748ns (21.519%) route 20.964ns (78.481%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.090ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.914ns = ( 28.409 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.934 24.210 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.915 28.409 u_cpu/btb/cpu_clk - SLICE_X114Y43 FDRE r u_cpu/btb/btb_pc_reg[13][7]/C - clock pessimism -0.498 27.911 - clock uncertainty -0.074 27.837 - SLICE_X114Y43 FDRE (Setup_fdre_C_CE) -0.205 27.632 u_cpu/btb/btb_pc_reg[13][7] - ------------------------------------------------------------------- - required time 27.632 - arrival time -24.210 - ------------------------------------------------------------------- - slack 3.421 - -Slack (MET) : 3.432ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.954ns (logic 7.073ns (26.241%) route 19.881ns (73.759%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=7 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.061ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.943ns = ( 28.380 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 1.175 22.803 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X47Y31 LUT4 (Prop_lut4_I3_O) 0.326 23.129 r u_cpu/u_csr/ds_to_es_bus_r[188]_i_12/O - net (fo=1, routed) 0.667 23.796 u_cpu/id_stage/ds_to_es_bus_r_reg[188] - SLICE_X47Y31 LUT6 (Prop_lut6_I1_O) 0.124 23.920 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_5/O - net (fo=1, routed) 0.409 24.329 u_cpu/id_stage/ds_to_es_bus_r[188]_i_5_n_0 - SLICE_X48Y31 LUT6 (Prop_lut6_I4_O) 0.124 24.453 r u_cpu/id_stage/ds_to_es_bus_r[188]_i_1/O - net (fo=1, routed) 0.000 24.453 u_cpu/exe_stage/ds_to_es_bus[138] - SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.886 28.380 u_cpu/exe_stage/cpu_clk - SLICE_X48Y31 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[188]/C - clock pessimism -0.498 27.882 - clock uncertainty -0.074 27.808 - SLICE_X48Y31 FDRE (Setup_fdre_C_D) 0.077 27.885 u_cpu/exe_stage/ds_to_es_bus_r_reg[188] - ------------------------------------------------------------------- - required time 27.885 - arrival time -24.453 - ------------------------------------------------------------------- - slack 3.432 - -Slack (MET) : 3.450ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.937ns (logic 7.073ns (26.257%) route 19.864ns (73.743%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=3 LUT5=8 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.058ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.377 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.669 21.478 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y29 LUT5 (Prop_lut5_I2_O) 0.150 21.628 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_26/O - net (fo=20, routed) 0.952 22.579 u_cpu/u_csr/ds_to_es_bus_r[193]_i_2 - SLICE_X42Y24 LUT5 (Prop_lut5_I1_O) 0.326 22.905 r u_cpu/u_csr/ds_to_es_bus_r[192]_i_9/O - net (fo=1, routed) 0.483 23.388 u_cpu/id_stage/ds_to_es_bus_r_reg[192] - SLICE_X42Y27 LUT4 (Prop_lut4_I3_O) 0.124 23.512 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_3/O - net (fo=1, routed) 0.800 24.312 u_cpu/id_stage/ds_to_es_bus_r[192]_i_3_n_0 - SLICE_X42Y29 LUT6 (Prop_lut6_I2_O) 0.124 24.436 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_1/O - net (fo=1, routed) 0.000 24.436 u_cpu/exe_stage/ds_to_es_bus[142] - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.883 28.377 u_cpu/exe_stage/cpu_clk - SLICE_X42Y29 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[192]/C - clock pessimism -0.498 27.879 - clock uncertainty -0.074 27.805 - SLICE_X42Y29 FDRE (Setup_fdre_C_D) 0.081 27.886 u_cpu/exe_stage/ds_to_es_bus_r_reg[192] - ------------------------------------------------------------------- - required time 27.886 - arrival time -24.436 - ------------------------------------------------------------------- - slack 3.450 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][13]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][13]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][13] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][15]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][15]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][15] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][17]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][17]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][17] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][21]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][21]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][21] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][3]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][3]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][3] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][4]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][4]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][4] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][6]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][6]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][6] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.466ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[21][7]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.271ns (logic 5.742ns (21.857%) route 20.529ns (78.143%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 28.214 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.748 19.761 u_cpu/btb/btb_operate_en - SLICE_X44Y12 LUT5 (Prop_lut5_I3_O) 0.116 19.877 f u_cpu/btb/btb_counter[23][1]_i_4/O - net (fo=26, routed) 0.927 20.805 u_cpu/btb/btb_counter[23][1]_i_4_n_0 - SLICE_X51Y16 LUT4 (Prop_lut4_I0_O) 0.322 21.127 r u_cpu/btb/btb_pc[21][29]_i_1/O - net (fo=30, routed) 2.643 23.769 u_cpu/btb/btb_pc[21][29]_i_1_n_0 - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.720 28.214 u_cpu/btb/cpu_clk - SLICE_X97Y50 FDRE r u_cpu/btb/btb_pc_reg[21][7]/C - clock pessimism -0.498 27.716 - clock uncertainty -0.074 27.642 - SLICE_X97Y50 FDRE (Setup_fdre_C_CE) -0.407 27.235 u_cpu/btb/btb_pc_reg[21][7] - ------------------------------------------------------------------- - required time 27.235 - arrival time -23.769 - ------------------------------------------------------------------- - slack 3.466 - -Slack (MET) : 3.472ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.266 22.692 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X45Y19 LUT5 (Prop_lut5_I4_O) 0.124 22.816 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_7/O - net (fo=1, routed) 0.650 23.467 u_cpu/id_stage/ds_to_es_bus_r[169]_i_7_n_0 - SLICE_X45Y24 LUT5 (Prop_lut5_I2_O) 0.124 23.591 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_3/O - net (fo=1, routed) 0.643 24.234 u_cpu/id_stage/ds_to_es_bus_r[169]_i_3_n_0 - SLICE_X45Y24 LUT6 (Prop_lut6_I2_O) 0.124 24.358 r u_cpu/id_stage/ds_to_es_bus_r[169]_i_1/O - net (fo=1, routed) 0.000 24.358 u_cpu/exe_stage/ds_to_es_bus[119] - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[169]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.029 27.830 u_cpu/exe_stage/ds_to_es_bus_r_reg[169] - ------------------------------------------------------------------- - required time 27.830 - arrival time -24.358 - ------------------------------------------------------------------- - slack 3.472 - -Slack (MET) : 3.473ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.860ns (logic 6.845ns (25.484%) route 20.015ns (74.516%)) - Logic Levels: 32 (CARRY4=5 LUT3=1 LUT4=2 LUT5=8 LUT6=14 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.054ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.950ns = ( 28.373 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.674 11.614 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X25Y39 LUT3 (Prop_lut3_I0_O) 0.313 11.927 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8/O - net (fo=32, routed) 0.707 12.634 u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[46]_i_8_n_0 - SLICE_X24Y34 LUT6 (Prop_lut6_I2_O) 0.124 12.758 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_44/O - net (fo=3, routed) 1.195 13.953 u_cpu/dcache/tagv_ram_way[0].u/data_rdata[7] - SLICE_X23Y32 LUT6 (Prop_lut6_I0_O) 0.124 14.077 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[63]_i_22/O - net (fo=3, routed) 0.466 14.543 u_cpu/dcache/tagv_ram_way[0].u/p_5_in6_in[0] - SLICE_X23Y29 LUT5 (Prop_lut5_I2_O) 0.124 14.667 f u_cpu/dcache/tagv_ram_way[0].u/ms_to_ws_bus_r[39]_i_15/O - net (fo=1, routed) 0.433 15.100 u_cpu/u_div/mem_result[0] - SLICE_X23Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.224 f u_cpu/u_div/ms_to_ws_bus_r[39]_i_4/O - net (fo=1, routed) 0.633 15.857 u_cpu/mem_stage/ms_to_ws_bus_r_reg[39]_0 - SLICE_X25Y29 LUT6 (Prop_lut6_I5_O) 0.124 15.981 f u_cpu/mem_stage/ms_to_ws_bus_r[39]_i_1/O - net (fo=5, routed) 0.715 16.695 u_cpu/id_stage/ms_to_ds_forward_bus[7] - SLICE_X29Y27 LUT5 (Prop_lut5_I2_O) 0.124 16.819 r u_cpu/id_stage/ds_to_es_bus_r[192]_i_21/O - net (fo=1, routed) 0.000 16.819 u_cpu/id_stage/ds_to_es_bus_r[192]_i_21_n_0 - SLICE_X29Y27 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 17.351 r u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16/CO[3] - net (fo=1, routed) 0.000 17.351 u_cpu/id_stage/ds_to_es_bus_r_reg[192]_i_16_n_0 - SLICE_X29Y28 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 17.685 f u_cpu/id_stage/ds_to_es_bus_r_reg[193]_i_60/O[1] - net (fo=1, routed) 0.630 18.315 u_cpu/id_stage/rd_csr_addr0[12] - SLICE_X28Y28 LUT5 (Prop_lut5_I0_O) 0.303 18.618 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_59/O - net (fo=1, routed) 0.724 19.342 u_cpu/id_stage/ds_to_es_bus_r[193]_i_59_n_0 - SLICE_X30Y28 LUT5 (Prop_lut5_I1_O) 0.124 19.466 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_53/O - net (fo=3, routed) 0.456 19.922 u_cpu/id_stage/ds_to_es_bus_r[193]_i_53_n_0 - SLICE_X34Y29 LUT4 (Prop_lut4_I3_O) 0.124 20.046 f u_cpu/id_stage/ds_to_es_bus_r[191]_i_14/O - net (fo=7, routed) 0.638 20.684 u_cpu/id_stage/ds_to_es_bus_r[191]_i_14_n_0 - SLICE_X37Y29 LUT6 (Prop_lut6_I5_O) 0.124 20.808 f u_cpu/id_stage/ds_to_es_bus_r[193]_i_28/O - net (fo=19, routed) 0.494 21.302 u_cpu/id_stage/ds_to_es_bus_r[193]_i_28_n_0 - SLICE_X38Y28 LUT6 (Prop_lut6_I5_O) 0.124 21.426 r u_cpu/id_stage/ds_to_es_bus_r[178]_i_12/O - net (fo=11, routed) 1.155 22.581 u_cpu/id_stage/ds_to_es_bus_r[178]_i_12_n_0 - SLICE_X42Y20 LUT5 (Prop_lut5_I4_O) 0.124 22.705 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_9/O - net (fo=1, routed) 0.760 23.465 u_cpu/id_stage/ds_to_es_bus_r[175]_i_9_n_0 - SLICE_X42Y24 LUT5 (Prop_lut5_I0_O) 0.124 23.589 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_4/O - net (fo=1, routed) 0.646 24.235 u_cpu/id_stage/ds_to_es_bus_r[175]_i_4_n_0 - SLICE_X45Y24 LUT6 (Prop_lut6_I3_O) 0.124 24.359 r u_cpu/id_stage/ds_to_es_bus_r[175]_i_1/O - net (fo=1, routed) 0.000 24.359 u_cpu/exe_stage/ds_to_es_bus[125] - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.879 28.373 u_cpu/exe_stage/cpu_clk - SLICE_X45Y24 FDRE r u_cpu/exe_stage/ds_to_es_bus_r_reg[175]/C - clock pessimism -0.498 27.875 - clock uncertainty -0.074 27.801 - SLICE_X45Y24 FDRE (Setup_fdre_C_D) 0.031 27.832 u_cpu/exe_stage/ds_to_es_bus_r_reg[175] - ------------------------------------------------------------------- - required time 27.832 - arrival time -24.359 - ------------------------------------------------------------------- - slack 3.473 - -Slack (MET) : 3.482ns (required time - arrival time) - Source: u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/btb/btb_pc_reg[13][26]/CE - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 26.650ns (logic 5.748ns (21.569%) route 20.902ns (78.431%)) - Logic Levels: 28 (CARRY4=3 LUT3=1 LUT4=2 LUT5=7 LUT6=13 MUXF7=1 MUXF8=1) - Clock Path Skew: 0.089ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.915ns = ( 28.408 - 30.323 ) - Source Clock Delay (SCD): -2.502ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.840 -2.502 u_cpu/addr_trans/tlb_entry/cpu_clk - SLICE_X65Y51 FDRE r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X65Y51 FDRE (Prop_fdre_C_Q) 0.419 -2.083 r u_cpu/addr_trans/tlb_entry/s1_asid_r_reg[5]/Q - net (fo=32, routed) 1.570 -0.512 u_cpu/addr_trans/tlb_entry/s1_asid_r[5] - SLICE_X59Y59 LUT6 (Prop_lut6_I3_O) 0.299 -0.213 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133/O - net (fo=1, routed) 0.000 -0.213 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_133_n_0 - SLICE_X59Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 0.337 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r_reg[174]_i_38/CO[3] - net (fo=1, routed) 1.393 1.730 u_cpu/addr_trans/tlb_entry/match12154_out - SLICE_X46Y56 LUT6 (Prop_lut6_I4_O) 0.124 1.854 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_10/O - net (fo=3, routed) 0.870 2.724 u_cpu/addr_trans/tlb_entry/match1[30] - SLICE_X43Y48 LUT4 (Prop_lut4_I3_O) 0.124 2.848 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2/O - net (fo=2, routed) 1.031 3.879 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[174]_i_2_n_0 - SLICE_X45Y45 LUT5 (Prop_lut5_I0_O) 0.124 4.003 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2/O - net (fo=2, routed) 0.584 4.587 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[175]_i_2_n_0 - SLICE_X45Y44 LUT6 (Prop_lut6_I0_O) 0.124 4.711 r u_cpu/addr_trans/tlb_entry/ms_to_ws_bus_r[173]_i_1/O - net (fo=89, routed) 0.941 5.652 u_cpu/addr_trans/tlb_entry/ms_to_ws_bus[8] - SLICE_X46Y39 MUXF7 (Prop_muxf7_S_O) 0.314 5.966 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65/O - net (fo=1, routed) 0.000 5.966 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_65_n_0 - SLICE_X46Y39 MUXF8 (Prop_muxf8_I0_O) 0.098 6.064 f u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0/O - net (fo=1, routed) 0.723 6.787 u_cpu/addr_trans/tlb_entry/request_buffer_tag_reg[9]_i_45__0_n_0 - SLICE_X41Y41 LUT5 (Prop_lut5_I0_O) 0.319 7.106 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20/O - net (fo=1, routed) 0.544 7.650 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_20_n_0 - SLICE_X37Y42 LUT6 (Prop_lut6_I5_O) 0.124 7.774 f u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7/O - net (fo=1, routed) 0.819 8.593 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_7_n_0 - SLICE_X34Y42 LUT6 (Prop_lut6_I5_O) 0.124 8.717 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0/O - net (fo=10, routed) 0.378 9.095 u_cpu/addr_trans/tlb_entry/request_buffer_tag[9]_i_2__0_n_0 - SLICE_X32Y42 LUT6 (Prop_lut6_I3_O) 0.124 9.219 r u_cpu/addr_trans/tlb_entry/request_buffer_tag[0]_i_1__0/O - net (fo=6, routed) 0.836 10.056 u_cpu/addr_trans/tlb_entry/data_vaddr_buffer_reg[12] - SLICE_X29Y44 LUT6 (Prop_lut6_I2_O) 0.124 10.180 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11/O - net (fo=1, routed) 0.000 10.180 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way[0]_i_11_n_0 - SLICE_X29Y44 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 10.712 r u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4/CO[3] - net (fo=1, routed) 0.000 10.712 u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_4_n_0 - SLICE_X29Y45 CARRY4 (Prop_carry4_CI_CO[2]) - 0.228 10.940 f u_cpu/addr_trans/tlb_entry/miss_buffer_replace_way_reg[0]_i_2/CO[2] - net (fo=5, routed) 0.647 11.586 u_cpu/dcache/tagv_ram_way[0].u/CO[0] - SLICE_X24Y42 LUT6 (Prop_lut6_I0_O) 0.313 11.899 f u_cpu/dcache/tagv_ram_way[0].u/write_buffer_way[1]_i_6/O - net (fo=4, routed) 0.458 12.357 u_cpu/addr_trans/tlb_entry/p_22_in - SLICE_X24Y42 LUT3 (Prop_lut3_I2_O) 0.124 12.481 f u_cpu/addr_trans/tlb_entry/main_state[0]_i_3/O - net (fo=3, routed) 0.502 12.983 u_cpu/dcache/main_state_reg[0]_2 - SLICE_X24Y42 LUT6 (Prop_lut6_I3_O) 0.124 13.107 f u_cpu/dcache/ds_to_es_bus_r[235]_i_10/O - net (fo=3, routed) 0.311 13.418 u_cpu/mem_stage/data_data_ok - SLICE_X25Y41 LUT6 (Prop_lut6_I2_O) 0.124 13.542 f u_cpu/mem_stage/ds_to_es_bus_r[235]_i_4/O - net (fo=9, routed) 0.347 13.889 u_cpu/mem_stage/ms_allowin - SLICE_X25Y39 LUT6 (Prop_lut6_I2_O) 0.124 14.013 f u_cpu/mem_stage/request_buffer_icacop_i_2/O - net (fo=6, routed) 0.493 14.506 u_cpu/exe_stage/p_13_in - SLICE_X24Y39 LUT5 (Prop_lut5_I0_O) 0.124 14.630 f u_cpu/exe_stage/request_buffer_dcacop_i_1/O - net (fo=6, routed) 0.651 15.281 u_cpu/exe_stage/dcacop_op_en - SLICE_X23Y39 LUT5 (Prop_lut5_I0_O) 0.124 15.405 f u_cpu/exe_stage/mem_reg_reg_i_37__1/O - net (fo=1, routed) 0.648 16.053 u_cpu/exe_stage/dcache/main_lookup2lookup3 - SLICE_X23Y39 LUT5 (Prop_lut5_I2_O) 0.124 16.177 r u_cpu/exe_stage/mem_reg_reg_i_36__0/O - net (fo=2, routed) 0.405 16.582 u_cpu/dcache/tagv_ram_way[1].u/p_23_in - SLICE_X24Y39 LUT5 (Prop_lut5_I4_O) 0.124 16.706 r u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg_i_32__1/O - net (fo=11, routed) 0.410 17.116 u_cpu/exe_stage/data_addr_ok - SLICE_X24Y39 LUT6 (Prop_lut6_I2_O) 0.124 17.240 r u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3/O - net (fo=6, routed) 0.650 17.890 u_cpu/exe_stage/ds_to_es_bus_r[235]_i_3_n_0 - SLICE_X29Y34 LUT6 (Prop_lut6_I2_O) 0.124 18.014 r u_cpu/exe_stage/btb_add_entry_r_i_3/O - net (fo=18, routed) 1.454 19.468 u_cpu/id_stage/btb_operate_en - SLICE_X43Y24 LUT5 (Prop_lut5_I1_O) 0.118 19.586 r u_cpu/id_stage/btb_counter[15][1]_i_4/O - net (fo=26, routed) 3.364 22.950 u_cpu/btb/btb_pc_reg[9][0]_0 - SLICE_X114Y33 LUT4 (Prop_lut4_I2_O) 0.326 23.276 r u_cpu/btb/btb_pc[13][29]_i_1/O - net (fo=30, routed) 0.872 24.148 u_cpu/btb/btb_pc[13][29]_i_1_n_0 - SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/CE - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.914 28.408 u_cpu/btb/cpu_clk - SLICE_X114Y41 FDRE r u_cpu/btb/btb_pc_reg[13][26]/C - clock pessimism -0.498 27.910 - clock uncertainty -0.074 27.836 - SLICE_X114Y41 FDRE (Setup_fdre_C_CE) -0.205 27.631 u_cpu/btb/btb_pc_reg[13][26] - ------------------------------------------------------------------- - required time 27.631 - arrival time -24.148 - ------------------------------------------------------------------- - slack 3.482 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: cpu_clk -Waveform(ns): { 0.000 15.161 } -Period(ns): 30.323 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I -Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C -Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 10.807ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 10.807ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.049ns (logic 0.704ns (2.423%) route 28.345ns (97.577%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.108 26.236 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.360 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[827]_i_1/O - net (fo=1, routed) 0.000 26.360 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_470 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[827] - ------------------------------------------------------------------- - required time 37.167 - arrival time -26.360 - ------------------------------------------------------------------- - slack 10.807 - -Slack (MET) : 10.904ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 29.004ns (logic 0.704ns (2.427%) route 28.300ns (97.573%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.063 26.191 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.315 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[780]_i_1/O - net (fo=1, routed) 0.000 26.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_912 - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X46Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X46Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[780] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.315 - ------------------------------------------------------------------- - slack 10.904 - -Slack (MET) : 10.918ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.987ns (logic 0.704ns (2.429%) route 28.283ns (97.571%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 22.045 26.173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y136 LUT6 (Prop_lut6_I1_O) 0.124 26.297 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[782]_i_1/O - net (fo=1, routed) 0.000 26.297 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_914 - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y136 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[782] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.297 - ------------------------------------------------------------------- - slack 10.918 - -Slack (MET) : 11.034ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.824ns (logic 0.704ns (2.442%) route 28.120ns (97.558%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.883 26.011 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[829]_i_1/O - net (fo=1, routed) 0.000 26.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_472 - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y135 FDCE (Setup_fdce_C_D) 0.031 37.169 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[829] - ------------------------------------------------------------------- - required time 37.169 - arrival time -26.135 - ------------------------------------------------------------------- - slack 11.034 - -Slack (MET) : 11.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.845ns (logic 0.704ns (2.441%) route 28.141ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.904 26.032 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.156 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[777]_i_1/O - net (fo=1, routed) 0.000 26.156 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_909 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.077 37.215 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[777] - ------------------------------------------------------------------- - required time 37.215 - arrival time -26.156 - ------------------------------------------------------------------- - slack 11.059 - -Slack (MET) : 11.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.842ns (logic 0.704ns (2.441%) route 28.138ns (97.559%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.901 26.029 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y135 LUT6 (Prop_lut6_I1_O) 0.124 26.153 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[969]_i_1/O - net (fo=1, routed) 0.000 26.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1143 - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X44Y135 FDCE (Setup_fdce_C_D) 0.081 37.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[969] - ------------------------------------------------------------------- - required time 37.219 - arrival time -26.153 - ------------------------------------------------------------------- - slack 11.066 - -Slack (MET) : 11.162ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.693ns (logic 0.704ns (2.454%) route 27.989ns (97.546%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.751 25.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y133 LUT6 (Prop_lut6_I1_O) 0.124 26.003 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[828]_i_1/O - net (fo=1, routed) 0.000 26.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_471 - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X45Y133 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[828] - ------------------------------------------------------------------- - required time 37.165 - arrival time -26.003 - ------------------------------------------------------------------- - slack 11.162 - -Slack (MET) : 11.217ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.639ns (logic 0.704ns (2.458%) route 27.935ns (97.542%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.697 25.825 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.949 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[906]_i_1/O - net (fo=1, routed) 0.000 25.949 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_917 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[906] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.949 - ------------------------------------------------------------------- - slack 11.217 - -Slack (MET) : 11.246ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.658ns (logic 0.704ns (2.457%) route 27.954ns (97.543%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.716 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.968 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[830]_i_1/O - net (fo=1, routed) 0.000 25.968 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_473 - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X44Y134 FDCE (Setup_fdce_C_D) 0.077 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[830] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.968 - ------------------------------------------------------------------- - slack 11.246 - -Slack (MET) : 11.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.534ns (logic 0.704ns (2.467%) route 27.830ns (97.533%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.592 25.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.844 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[953]_i_1/O - net (fo=1, routed) 0.000 25.844 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_475 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[953] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.844 - ------------------------------------------------------------------- - slack 11.322 - -Slack (MET) : 11.414ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.489ns (logic 0.704ns (2.471%) route 27.785ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.547 25.675 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[778]_i_1/O - net (fo=1, routed) 0.000 25.799 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_910 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[778] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.799 - ------------------------------------------------------------------- - slack 11.414 - -Slack (MET) : 11.421ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.486ns (logic 0.704ns (2.471%) route 27.782ns (97.529%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.544 25.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.796 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[826]_i_1/O - net (fo=1, routed) 0.000 25.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_469 - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X44Y133 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[826] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.796 - ------------------------------------------------------------------- - slack 11.421 - -Slack (MET) : 11.503ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.355ns (logic 0.704ns (2.483%) route 27.651ns (97.517%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.413 25.541 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.665 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[908]_i_1/O - net (fo=1, routed) 0.000 25.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_919 - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X45Y134 FDCE (Setup_fdce_C_D) 0.031 37.168 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[908] - ------------------------------------------------------------------- - required time 37.168 - arrival time -25.665 - ------------------------------------------------------------------- - slack 11.503 - -Slack (MET) : 11.505ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.347ns (logic 0.704ns (2.484%) route 27.643ns (97.516%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.405 25.533 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.657 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[909]_i_1/O - net (fo=1, routed) 0.000 25.657 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_920 - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X45Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[909] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.657 - ------------------------------------------------------------------- - slack 11.505 - -Slack (MET) : 11.519ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.387ns (logic 0.704ns (2.480%) route 27.683ns (97.520%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.445 25.573 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.697 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[956]_i_1/O - net (fo=1, routed) 0.000 25.697 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_478 - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X44Y132 FDCE (Setup_fdce_C_D) 0.081 37.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[956] - ------------------------------------------------------------------- - required time 37.216 - arrival time -25.697 - ------------------------------------------------------------------- - slack 11.519 - -Slack (MET) : 11.557ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.299ns (logic 0.704ns (2.488%) route 27.595ns (97.512%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.357 25.485 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.609 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[952]_i_1/O - net (fo=1, routed) 0.000 25.609 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_474 - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X45Y132 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[952] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.609 - ------------------------------------------------------------------- - slack 11.557 - -Slack (MET) : 11.686ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.168ns (logic 0.704ns (2.499%) route 27.464ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.100ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.283ns = ( 37.717 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.227 25.355 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y132 LUT6 (Prop_lut6_I1_O) 0.124 25.479 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[955]_i_1/O - net (fo=1, routed) 0.000 25.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_477 - SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.545 37.717 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y132 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955]/C - clock pessimism -0.507 37.210 - clock uncertainty -0.077 37.134 - SLICE_X43Y132 FDCE (Setup_fdce_C_D) 0.031 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[955] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.479 - ------------------------------------------------------------------- - slack 11.686 - -Slack (MET) : 11.688ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.252ns (logic 0.704ns (2.492%) route 27.548ns (97.508%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.013ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.196ns = ( 37.804 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.311 25.438 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X41Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1020]_i_1/O - net (fo=1, routed) 0.000 25.562 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1186 - SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.632 37.804 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X41Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020]/C - clock pessimism -0.507 37.297 - clock uncertainty -0.077 37.221 - SLICE_X41Y133 FDCE (Setup_fdce_C_D) 0.029 37.250 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1020] - ------------------------------------------------------------------- - required time 37.250 - arrival time -25.562 - ------------------------------------------------------------------- - slack 11.688 - -Slack (MET) : 11.690ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.161ns (logic 0.704ns (2.500%) route 27.457ns (97.500%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.220 25.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X47Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1016]_i_1/O - net (fo=1, routed) 0.000 25.471 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1182 - SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X47Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X47Y131 FDCE (Setup_fdce_C_D) 0.029 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1016] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.471 - ------------------------------------------------------------------- - slack 11.690 - -Slack (MET) : 11.731ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.172ns (logic 0.704ns (2.499%) route 27.468ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.230 25.358 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.482 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1005]_i_1/O - net (fo=1, routed) 0.000 25.482 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1171 - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.077 37.213 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1005] - ------------------------------------------------------------------- - required time 37.213 - arrival time -25.482 - ------------------------------------------------------------------- - slack 11.731 - -Slack (MET) : 11.735ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.114ns (logic 0.704ns (2.504%) route 27.410ns (97.496%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.173 25.301 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.425 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[653]_i_1/O - net (fo=1, routed) 0.000 25.425 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_906 - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[653] - ------------------------------------------------------------------- - required time 37.160 - arrival time -25.425 - ------------------------------------------------------------------- - slack 11.735 - -Slack (MET) : 11.764ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.140ns (logic 0.704ns (2.502%) route 27.436ns (97.498%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.284ns = ( 37.716 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.198 25.326 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X44Y131 LUT6 (Prop_lut6_I1_O) 0.124 25.450 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[880]_i_1/O - net (fo=1, routed) 0.000 25.450 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1117 - SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.544 37.716 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X44Y131 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880]/C - clock pessimism -0.507 37.209 - clock uncertainty -0.077 37.133 - SLICE_X44Y131 FDCE (Setup_fdce_C_D) 0.081 37.214 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[880] - ------------------------------------------------------------------- - required time 37.214 - arrival time -25.450 - ------------------------------------------------------------------- - slack 11.764 - -Slack (MET) : 11.777ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.166ns (logic 0.704ns (2.499%) route 27.462ns (97.501%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.012ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.195ns = ( 37.805 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.225 25.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X41Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.476 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[968]_i_1/O - net (fo=1, routed) 0.000 25.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1142 - SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.633 37.805 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X41Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968]/C - clock pessimism -0.507 37.298 - clock uncertainty -0.077 37.222 - SLICE_X41Y134 FDCE (Setup_fdce_C_D) 0.031 37.253 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[968] - ------------------------------------------------------------------- - required time 37.253 - arrival time -25.476 - ------------------------------------------------------------------- - slack 11.777 - -Slack (MET) : 11.846ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.007ns (logic 0.704ns (2.514%) route 27.303ns (97.486%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.066 25.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.318 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[825]_i_1/O - net (fo=1, routed) 0.000 25.318 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_468 - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.029 37.164 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[825] - ------------------------------------------------------------------- - required time 37.164 - arrival time -25.318 - ------------------------------------------------------------------- - slack 11.846 - -Slack (MET) : 11.849ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 28.006ns (logic 0.704ns (2.514%) route 27.302ns (97.486%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.065 25.193 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.317 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[921]_i_1/O - net (fo=1, routed) 0.000 25.317 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1006 - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X43Y133 FDCE (Setup_fdce_C_D) 0.031 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[921] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.317 - ------------------------------------------------------------------- - slack 11.849 - -Slack (MET) : 11.911ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.944ns (logic 0.704ns (2.519%) route 27.240ns (97.481%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.002 25.130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.254 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[794]_i_1/O - net (fo=1, routed) 0.000 25.254 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1000 - SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X43Y134 FDCE (Setup_fdce_C_D) 0.029 37.165 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[794] - ------------------------------------------------------------------- - required time 37.165 - arrival time -25.254 - ------------------------------------------------------------------- - slack 11.911 - -Slack (MET) : 11.944ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.955ns (logic 0.704ns (2.518%) route 27.251ns (97.482%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.102ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.285ns = ( 37.715 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.013 25.141 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X46Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.265 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[941]_i_1/O - net (fo=1, routed) 0.000 25.265 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_335 - SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.543 37.715 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X46Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941]/C - clock pessimism -0.507 37.208 - clock uncertainty -0.077 37.132 - SLICE_X46Y130 FDCE (Setup_fdce_C_D) 0.077 37.209 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[941] - ------------------------------------------------------------------- - required time 37.209 - arrival time -25.265 - ------------------------------------------------------------------- - slack 11.944 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1114] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1115] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1331] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1401] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1435] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[829] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[860] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.945ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.502ns (logic 1.594ns (5.796%) route 25.908ns (94.204%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.105ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.184ns = ( 37.816 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 8.126 24.917 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.644 37.816 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y116 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924]/C - clock pessimism -0.507 37.309 - clock uncertainty -0.077 37.233 - SLICE_X22Y116 FDCE (Setup_fdce_C_CE) -0.371 36.862 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[924] - ------------------------------------------------------------------- - required time 36.862 - arrival time -24.917 - ------------------------------------------------------------------- - slack 11.945 - -Slack (MET) : 11.947ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.960ns (logic 0.704ns (2.518%) route 27.256ns (97.482%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.098ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.281ns = ( 37.719 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 21.018 25.146 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y134 LUT6 (Prop_lut6_I1_O) 0.124 25.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1006]_i_1/O - net (fo=1, routed) 0.000 25.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1172 - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.547 37.719 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y134 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006]/C - clock pessimism -0.507 37.212 - clock uncertainty -0.077 37.136 - SLICE_X42Y134 FDCE (Setup_fdce_C_D) 0.081 37.217 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1006] - ------------------------------------------------------------------- - required time 37.217 - arrival time -25.270 - ------------------------------------------------------------------- - slack 11.947 - -Slack (MET) : 11.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[698]_i_1/O - net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_462 - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.029 37.160 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[698] - ------------------------------------------------------------------- - required time 37.160 - arrival time -25.202 - ------------------------------------------------------------------- - slack 11.958 - -Slack (MET) : 11.960ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.891ns (logic 0.704ns (2.524%) route 27.187ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.950 25.078 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X50Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[996]_i_1/O - net (fo=1, routed) 0.000 25.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_785 - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X50Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X50Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[996] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.202 - ------------------------------------------------------------------- - slack 11.960 - -Slack (MET) : 11.962ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.889ns (logic 0.704ns (2.524%) route 27.185ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.948 25.076 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X51Y129 LUT6 (Prop_lut6_I1_O) 0.124 25.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[997]_i_1/O - net (fo=1, routed) 0.000 25.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_786 - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X51Y129 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X51Y129 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[997] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.200 - ------------------------------------------------------------------- - slack 11.962 - -Slack (MET) : 11.975ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.867ns (logic 0.704ns (2.526%) route 27.163ns (97.474%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.110ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.293ns = ( 37.707 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.926 25.054 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X55Y125 LUT6 (Prop_lut6_I1_O) 0.124 25.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[713]_i_1/O - net (fo=1, routed) 0.000 25.178 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1029 - SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.535 37.707 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X55Y125 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713]/C - clock pessimism -0.507 37.200 - clock uncertainty -0.077 37.124 - SLICE_X55Y125 FDCE (Setup_fdce_C_D) 0.029 37.153 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[713] - ------------------------------------------------------------------- - required time 37.153 - arrival time -25.178 - ------------------------------------------------------------------- - slack 11.975 - -Slack (MET) : 12.001ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.895ns (logic 0.704ns (2.524%) route 27.191ns (97.476%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.104ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.287ns = ( 37.713 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.954 25.082 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X52Y128 LUT6 (Prop_lut6_I1_O) 0.124 25.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[714]_i_1/O - net (fo=1, routed) 0.000 25.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1030 - SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.541 37.713 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X52Y128 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714]/C - clock pessimism -0.507 37.206 - clock uncertainty -0.077 37.130 - SLICE_X52Y128 FDCE (Setup_fdce_C_D) 0.077 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[714] - ------------------------------------------------------------------- - required time 37.207 - arrival time -25.206 - ------------------------------------------------------------------- - slack 12.001 - -Slack (MET) : 12.017ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.835ns (logic 0.704ns (2.529%) route 27.131ns (97.471%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.103ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.286ns = ( 37.714 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.894 25.021 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X53Y130 LUT6 (Prop_lut6_I1_O) 0.124 25.145 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[701]_i_1/O - net (fo=1, routed) 0.000 25.145 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_465 - SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.542 37.714 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X53Y130 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701]/C - clock pessimism -0.507 37.207 - clock uncertainty -0.077 37.131 - SLICE_X53Y130 FDCE (Setup_fdce_C_D) 0.031 37.162 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[701] - ------------------------------------------------------------------- - required time 37.162 - arrival time -25.145 - ------------------------------------------------------------------- - slack 12.017 - -Slack (MET) : 12.030ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.097ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.280ns = ( 37.720 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.884 25.012 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X43Y135 LUT6 (Prop_lut6_I1_O) 0.124 25.136 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[1002]_i_1/O - net (fo=1, routed) 0.000 25.136 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1168 - SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.548 37.720 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X43Y135 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002]/C - clock pessimism -0.507 37.213 - clock uncertainty -0.077 37.137 - SLICE_X43Y135 FDCE (Setup_fdce_C_D) 0.029 37.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[1002] - ------------------------------------------------------------------- - required time 37.166 - arrival time -25.136 - ------------------------------------------------------------------- - slack 12.030 - -Slack (MET) : 12.046ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.810ns (logic 0.704ns (2.531%) route 27.106ns (97.469%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.096ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.279ns = ( 37.721 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.869 24.997 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X45Y136 LUT6 (Prop_lut6_I1_O) 0.124 25.121 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[781]_i_1/O - net (fo=1, routed) 0.000 25.121 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_913 - SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.549 37.721 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X45Y136 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781]/C - clock pessimism -0.507 37.214 - clock uncertainty -0.077 37.138 - SLICE_X45Y136 FDCE (Setup_fdce_C_D) 0.029 37.167 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[781] - ------------------------------------------------------------------- - required time 37.167 - arrival time -25.121 - ------------------------------------------------------------------- - slack 12.046 - -Slack (MET) : 12.066ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.826ns (logic 0.704ns (2.530%) route 27.122ns (97.470%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.885 25.013 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[712]_i_1/O - net (fo=1, routed) 0.000 25.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1028 - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712]/C - clock pessimism -0.507 37.202 - clock uncertainty -0.077 37.126 - SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.077 37.203 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[712] - ------------------------------------------------------------------- - required time 37.203 - arrival time -25.137 - ------------------------------------------------------------------- - slack 12.066 - -Slack (MET) : 12.080ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.816ns (logic 0.704ns (2.531%) route 27.112ns (97.469%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.108ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.291ns = ( 37.709 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.875 25.003 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X56Y126 LUT6 (Prop_lut6_I1_O) 0.124 25.127 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[716]_i_1/O - net (fo=1, routed) 0.000 25.127 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1032 - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.537 37.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X56Y126 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716]/C - clock pessimism -0.507 37.202 - clock uncertainty -0.077 37.126 - SLICE_X56Y126 FDCE (Setup_fdce_C_D) 0.081 37.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[716] - ------------------------------------------------------------------- - required time 37.207 - arrival time -25.127 - ------------------------------------------------------------------- - slack 12.080 - -Slack (MET) : 12.098ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.803ns (logic 0.704ns (2.532%) route 27.099ns (97.468%)) - Logic Levels: 2 (LUT5=1 LUT6=1) - Clock Path Skew: -0.099ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.282ns = ( 37.718 - 40.000 ) - Source Clock Delay (SCD): -2.690ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.652 -2.690 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X91Y121 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X91Y121 FDCE (Prop_fdce_C_Q) 0.456 -2.234 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[4]/Q - net (fo=169, routed) 6.237 4.004 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st[4] - SLICE_X157Y96 LUT5 (Prop_lut5_I0_O) 0.124 4.128 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r[1086]_i_3/O - net (fo=936, routed) 20.862 24.990 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/sha3_mb_en0 - SLICE_X42Y133 LUT6 (Prop_lut6_I1_O) 0.124 25.114 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/h_block_r[920]_i_1/O - net (fo=1, routed) 0.000 25.114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram_n_1005 - SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.546 37.718 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X42Y133 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920]/C - clock pessimism -0.507 37.211 - clock uncertainty -0.077 37.135 - SLICE_X42Y133 FDCE (Setup_fdce_C_D) 0.077 37.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/h_block_r_reg[920] - ------------------------------------------------------------------- - required time 37.212 - arrival time -25.114 - ------------------------------------------------------------------- - slack 12.098 - -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1490] - ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 - ------------------------------------------------------------------- - slack 12.111 - -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1491] - ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 - ------------------------------------------------------------------- - slack 12.111 - -Slack (MET) : 12.111ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 27.340ns (logic 1.594ns (5.830%) route 25.746ns (94.170%)) - Logic Levels: 6 (LUT2=1 LUT3=1 LUT5=1 LUT6=3) - Clock Path Skew: -0.101ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.180ns = ( 37.820 - 40.000 ) - Source Clock Delay (SCD): -2.586ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.756 -2.586 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X145Y107 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/C - ------------------------------------------------------------------- ------------------- - SLICE_X145Y107 FDCE (Prop_fdce_C_Q) 0.419 -2.167 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/st_reg[0]_rep__4/Q - net (fo=117, routed) 5.212 3.045 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[0]_2 - SLICE_X106Y93 LUT5 (Prop_lut5_I3_O) 0.299 3.344 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_4/O - net (fo=121, routed) 1.227 4.571 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/st_reg[4] - SLICE_X104Y107 LUT2 (Prop_lut2_I1_O) 0.148 4.719 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/squeeze_state_r[1599]_i_1/O - net (fo=1608, routed) 4.784 9.503 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/E[0] - SLICE_X71Y130 LUT6 (Prop_lut6_I3_O) 0.328 9.831 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5/O - net (fo=1601, routed) 4.248 14.079 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[1599]_i_5_n_0 - SLICE_X95Y112 LUT6 (Prop_lut6_I2_O) 0.124 14.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4/O - net (fo=1, routed) 1.079 15.282 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_4_n_0 - SLICE_X104Y107 LUT6 (Prop_lut6_I0_O) 0.124 15.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/cnt_r[4]_i_3/O - net (fo=2, routed) 1.233 16.639 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_valid_i_mux - SLICE_X103Y100 LUT3 (Prop_lut3_I2_O) 0.152 16.791 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1/O - net (fo=1601, routed) 7.963 24.755 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[1599]_i_1_n_0 - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/CE - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.648 37.820 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X22Y111 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778]/C - clock pessimism -0.507 37.313 - clock uncertainty -0.077 37.237 - SLICE_X22Y111 FDCE (Setup_fdce_C_CE) -0.371 36.866 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[778] - ------------------------------------------------------------------- - required time 36.866 - arrival time -24.755 - ------------------------------------------------------------------- - slack 12.111 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: mlkem_clk_clk_pll -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I -Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C -Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 0.167ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.167ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.605ns (logic 5.343ns (34.236%) route 10.263ns (65.764%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 4.141 9.661 ext_ram_data_IOBUF[18]_inst/I - AB17 OBUFT (Prop_obuft_I_O) 3.527 13.188 r ext_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.188 ext_ram_data[18] - AB17 r ext_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.188 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.284ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.487ns (logic 5.350ns (34.543%) route 10.137ns (65.457%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.573 9.542 ext_ram_data_IOBUF[22]_inst/I - Y15 OBUFT (Prop_obuft_I_O) 3.528 13.070 r ext_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 13.070 ext_ram_data[22] - Y15 r ext_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -13.070 - ------------------------------------------------------------------- - slack 0.284 - -Slack (MET) : 0.377ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.299ns (logic 6.859ns (44.835%) route 8.440ns (55.165%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.637 9.431 ext_ram_data_IOBUF[21]_inst/T - AC16 OBUFT (TriStatE_obuft_T_O) - 3.546 12.977 r ext_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.977 ext_ram_data[21] - AC16 r ext_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.977 - ------------------------------------------------------------------- - slack 0.377 - -Slack (MET) : 0.414ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.262ns (logic 6.849ns (44.879%) route 8.413ns (55.121%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.610 9.404 ext_ram_data_IOBUF[16]_inst/T - AB16 OBUFT (TriStatE_obuft_T_O) - 3.536 12.940 r ext_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.940 ext_ram_data[16] - AB16 r ext_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.940 - ------------------------------------------------------------------- - slack 0.414 - -Slack (MET) : 0.424ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.348ns (logic 5.135ns (33.455%) route 10.213ns (66.545%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 3.472 9.382 base_ram_data_IOBUF[1]_inst/I - L25 OBUFT (Prop_obuft_I_O) 3.549 12.931 r base_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.931 base_ram_data[1] - L25 r base_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.931 - ------------------------------------------------------------------- - slack 0.424 - -Slack (MET) : 0.431ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.341ns (logic 5.382ns (35.085%) route 9.959ns (64.915%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 3.204 9.379 ext_ram_data_IOBUF[20]_inst/I - AD18 OBUFT (Prop_obuft_I_O) 3.544 12.923 r ext_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.923 ext_ram_data[20] - AD18 r ext_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.923 - ------------------------------------------------------------------- - slack 0.431 - -Slack (MET) : 0.455ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[25] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.221ns (logic 6.866ns (45.113%) route 8.354ns (54.887%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.551 9.346 ext_ram_data_IOBUF[25]_inst/T - AC17 OBUFT (TriStatE_obuft_T_O) - 3.553 12.899 r ext_ram_data_IOBUF[25]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.899 ext_ram_data[25] - AC17 r ext_ram_data[25] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.899 - ------------------------------------------------------------------- - slack 0.455 - -Slack (MET) : 0.477ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.295ns (logic 5.343ns (34.930%) route 9.952ns (65.070%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 3.219 9.357 base_ram_data_IOBUF[28]_inst/I - N22 OBUFT (Prop_obuft_I_O) 3.521 12.877 r base_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.877 base_ram_data[28] - N22 r base_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.877 - ------------------------------------------------------------------- - slack 0.477 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[21] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.121ns (logic 6.857ns (45.346%) route 8.264ns (54.654%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.726 9.256 base_ram_data_IOBUF[21]_inst/T - M20 OBUFT (TriStatE_obuft_T_O) - 3.544 12.799 r base_ram_data_IOBUF[21]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[21] - M20 r base_ram_data[21] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.555ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.120ns (logic 6.872ns (45.452%) route 8.248ns (54.548%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.710 9.239 base_ram_data_IOBUF[30]_inst/T - M24 OBUFT (TriStatE_obuft_T_O) - 3.559 12.799 r base_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.799 base_ram_data[30] - M24 r base_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.799 - ------------------------------------------------------------------- - slack 0.555 - -Slack (MET) : 0.558ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[24] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.118ns (logic 6.871ns (45.448%) route 8.247ns (54.552%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.444 9.239 ext_ram_data_IOBUF[24]_inst/T - AD17 OBUFT (TriStatE_obuft_T_O) - 3.558 12.797 r ext_ram_data_IOBUF[24]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.797 ext_ram_data[24] - AD17 r ext_ram_data[24] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.797 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.584ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[17] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.092ns (logic 6.859ns (45.448%) route 8.233ns (54.552%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.694 9.224 base_ram_data_IOBUF[17]_inst/T - M21 OBUFT (TriStatE_obuft_T_O) - 3.546 12.770 r base_ram_data_IOBUF[17]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.770 base_ram_data[17] - M21 r base_ram_data[17] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.770 - ------------------------------------------------------------------- - slack 0.584 - -Slack (MET) : 0.597ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[23] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.079ns (logic 6.848ns (45.415%) route 8.231ns (54.585%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.693 9.222 base_ram_data_IOBUF[23]_inst/T - N21 OBUFT (TriStatE_obuft_T_O) - 3.535 12.757 r base_ram_data_IOBUF[23]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.757 base_ram_data[23] - N21 r base_ram_data[23] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.757 - ------------------------------------------------------------------- - slack 0.597 - -Slack (MET) : 0.647ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[19] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.124ns (logic 5.128ns (33.905%) route 9.996ns (66.095%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.513 2.665 u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/ADDRB0 - SLICE_X36Y74 RAMD32 (Prop_ramd32_RADR0_O) - 0.124 2.789 r u_matmul_axi_slave/b0_c_reg_r2_0_15_48_53/RAMB_D1/O - net (fo=1, routed) 0.605 3.393 u_snix_axil_cdma_mux_8ch/ep_rd_c0[51] - SLICE_X34Y74 LUT6 (Prop_lut6_I1_O) 0.124 3.517 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_14__0/O - net (fo=2, routed) 0.775 4.293 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1_0 - SLICE_X30Y77 LUT5 (Prop_lut5_I3_O) 0.124 4.417 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_7__0/O - net (fo=2, routed) 1.453 5.869 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[19] - SLICE_X6Y79 LUT3 (Prop_lut3_I0_O) 0.124 5.993 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[19]_inst_i_1/O - net (fo=2, routed) 3.172 9.165 ext_ram_data_IOBUF[19]_inst/I - AC18 OBUFT (Prop_obuft_I_O) 3.542 12.707 r ext_ram_data_IOBUF[19]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.707 ext_ram_data[19] - AC18 r ext_ram_data[19] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.707 - ------------------------------------------------------------------- - slack 0.647 - -Slack (MET) : 0.675ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[2] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.000ns (logic 6.848ns (45.654%) route 8.152ns (54.346%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 2.270 7.078 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] - SLICE_X11Y127 LUT6 (Prop_lut6_I5_O) 0.124 7.202 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[2]_inst_i_1/O - net (fo=1, routed) 1.941 9.143 base_ram_be_n_OBUF[2] - L23 OBUF (Prop_obuf_I_O) 3.535 12.679 r base_ram_be_n_OBUF[2]_inst/O - net (fo=0) 0.000 12.679 base_ram_be_n[2] - L23 r base_ram_be_n[2] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.679 - ------------------------------------------------------------------- - slack 0.675 - -Slack (MET) : 0.680ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.996ns (logic 6.840ns (45.614%) route 8.156ns (54.386%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.617 9.147 base_ram_data_IOBUF[16]_inst/T - P21 OBUFT (TriStatE_obuft_T_O) - 3.527 12.674 r base_ram_data_IOBUF[16]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.674 base_ram_data[16] - P21 r base_ram_data[16] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.674 - ------------------------------------------------------------------- - slack 0.680 - -Slack (MET) : 0.681ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[22] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.090ns (logic 5.359ns (35.512%) route 9.732ns (64.488%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.303 2.455 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRC0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.153 2.608 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMC/O - net (fo=1, routed) 0.646 3.253 u_snix_axil_cdma_mux_8ch/ep_rd_c1[22] - SLICE_X39Y72 LUT6 (Prop_lut6_I0_O) 0.331 3.584 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_30__0/O - net (fo=2, routed) 0.954 4.538 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1_1 - SLICE_X25Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.662 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_12__0/O - net (fo=2, routed) 1.183 5.845 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[22] - SLICE_X1Y72 LUT3 (Prop_lut3_I0_O) 0.124 5.969 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[22]_inst_i_1/O - net (fo=2, routed) 3.167 9.136 base_ram_data_IOBUF[22]_inst/I - N24 OBUFT (Prop_obuft_I_O) 3.537 12.673 r base_ram_data_IOBUF[22]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.673 base_ram_data[22] - N24 r base_ram_data[22] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.673 - ------------------------------------------------------------------- - slack 0.681 - -Slack (MET) : 0.682ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.993ns (logic 6.873ns (45.840%) route 8.120ns (54.160%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.582 9.112 base_ram_data_IOBUF[0]_inst/T - L24 OBUFT (TriStatE_obuft_T_O) - 3.560 12.672 r base_ram_data_IOBUF[0]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.672 base_ram_data[0] - L24 r base_ram_data[0] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.672 - ------------------------------------------------------------------- - slack 0.682 - -Slack (MET) : 0.692ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[23] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.984ns (logic 6.855ns (45.753%) route 8.128ns (54.247%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 3.325 9.120 ext_ram_data_IOBUF[23]_inst/T - AA15 OBUFT (TriStatE_obuft_T_O) - 3.542 12.662 r ext_ram_data_IOBUF[23]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.662 ext_ram_data[23] - AA15 r ext_ram_data[23] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.662 - ------------------------------------------------------------------- - slack 0.692 - -Slack (MET) : 0.697ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[29] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.075ns (logic 5.121ns (33.974%) route 9.953ns (66.026%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 - SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O - net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] - SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O - net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 - SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O - net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 - SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O - net (fo=2, routed) 2.916 9.122 base_ram_data_IOBUF[29]_inst/I - N23 OBUFT (Prop_obuft_I_O) 3.535 12.657 r base_ram_data_IOBUF[29]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.657 base_ram_data[29] - N23 r base_ram_data[29] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.657 - ------------------------------------------------------------------- - slack 0.697 - -Slack (MET) : 0.700ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[3] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.976ns (logic 6.883ns (45.959%) route 8.093ns (54.041%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.555 9.084 base_ram_data_IOBUF[3]_inst/T - M25 OBUFT (TriStatE_obuft_T_O) - 3.570 12.654 r base_ram_data_IOBUF[3]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.654 base_ram_data[3] - M25 r base_ram_data[3] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.654 - ------------------------------------------------------------------- - slack 0.700 - -Slack (MET) : 0.717ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[31] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.959ns (logic 6.859ns (45.853%) route 8.100ns (54.147%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.562 9.091 base_ram_data_IOBUF[31]_inst/T - M22 OBUFT (TriStatE_obuft_T_O) - 3.546 12.638 r base_ram_data_IOBUF[31]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.638 base_ram_data[31] - M22 r base_ram_data[31] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.638 - ------------------------------------------------------------------- - slack 0.717 - -Slack (MET) : 0.724ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[20] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.048ns (logic 5.340ns (35.487%) route 9.708ns (64.513%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.427 2.759 u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/ADDRB1 - SLICE_X40Y74 RAMD32 (Prop_ramd32_RADR1_O) - 0.152 2.911 r u_matmul_axi_slave/b0_c_reg_r2_0_15_18_23/RAMB/O - net (fo=1, routed) 0.587 3.498 u_snix_axil_cdma_mux_8ch/ep_rd_c0[20] - SLICE_X35Y74 LUT6 (Prop_lut6_I1_O) 0.348 3.846 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_24__0/O - net (fo=2, routed) 0.666 4.512 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][20]_i_3_1 - SLICE_X30Y74 LUT5 (Prop_lut5_I4_O) 0.124 4.636 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_10__0/O - net (fo=7, routed) 1.415 6.051 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[20] - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.175 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[20]_inst_i_1/O - net (fo=2, routed) 2.954 9.128 base_ram_data_IOBUF[20]_inst/I - N19 OBUFT (Prop_obuft_I_O) 3.502 12.630 r base_ram_data_IOBUF[20]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.630 base_ram_data[20] - N19 r base_ram_data[20] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.630 - ------------------------------------------------------------------- - slack 0.724 - -Slack (MET) : 0.737ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[18] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 15.035ns (logic 5.349ns (35.580%) route 9.685ns (64.420%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.490 1.027 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X35Y71 LUT6 (Prop_lut6_I5_O) 0.124 1.151 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_4/O - net (fo=196, routed) 1.449 2.600 u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/ADDRA0 - SLICE_X40Y72 RAMD32 (Prop_ramd32_RADR0_O) - 0.150 2.750 r u_matmul_axi_slave/b1_c_reg_r2_0_15_18_23/RAMA/O - net (fo=1, routed) 1.044 3.794 u_snix_axil_cdma_mux_8ch/ep_rd_c1[18] - SLICE_X37Y75 LUT6 (Prop_lut6_I0_O) 0.328 4.122 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_18_23_i_18__0/O - net (fo=2, routed) 0.829 4.951 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1_1 - SLICE_X33Y77 LUT5 (Prop_lut5_I4_O) 0.124 5.075 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_18_23_i_8__0/O - net (fo=2, routed) 0.321 5.396 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[18] - SLICE_X30Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.520 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[18]_inst_i_1/O - net (fo=2, routed) 3.564 9.084 base_ram_data_IOBUF[18]_inst/I - P23 OBUFT (Prop_obuft_I_O) 3.533 12.617 r base_ram_data_IOBUF[18]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.617 base_ram_data[18] - P23 r base_ram_data[18] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.617 - ------------------------------------------------------------------- - slack 0.737 - -Slack (MET) : 0.793ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[28] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.978ns (logic 5.374ns (35.881%) route 9.604ns (64.119%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.262 2.594 u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/ADDRC1 - SLICE_X40Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.747 r u_matmul_axi_slave/b1_c_reg_r2_0_15_24_29/RAMC/O - net (fo=1, routed) 0.613 3.361 u_snix_axil_cdma_mux_8ch/ep_rd_c1[28] - SLICE_X34Y70 LUT6 (Prop_lut6_I0_O) 0.331 3.692 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_30__0/O - net (fo=1, routed) 0.780 4.472 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][28]_i_2_1 - SLICE_X34Y73 LUT4 (Prop_lut4_I3_O) 0.124 4.596 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_12__0/O - net (fo=6, routed) 1.419 6.014 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[28] - SLICE_X2Y72 LUT3 (Prop_lut3_I0_O) 0.124 6.138 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[28]_inst_i_1/O - net (fo=2, routed) 2.870 9.008 ext_ram_data_IOBUF[28]_inst/I - AD21 OBUFT (Prop_obuft_I_O) 3.552 12.561 r ext_ram_data_IOBUF[28]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.561 ext_ram_data[28] - AD21 r ext_ram_data[28] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.561 - ------------------------------------------------------------------- - slack 0.793 - -Slack (MET) : 0.827ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[26] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.945ns (logic 5.374ns (35.959%) route 9.571ns (64.041%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 0.957 2.289 u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/ADDRC1 - SLICE_X36Y70 RAMD32 (Prop_ramd32_RADR1_O) - 0.153 2.442 r u_matmul_axi_slave/b1_c_reg_r2_0_15_54_59/RAMC/O - net (fo=1, routed) 0.739 3.181 u_snix_axil_cdma_mux_8ch/ep_rd_c1[58] - SLICE_X39Y71 LUT6 (Prop_lut6_I0_O) 0.331 3.512 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_23__0/O - net (fo=1, routed) 0.706 4.218 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][26]_i_2_0 - SLICE_X35Y73 LUT4 (Prop_lut4_I2_O) 0.124 4.342 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_10__0/O - net (fo=6, routed) 1.406 5.748 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[26] - SLICE_X2Y73 LUT3 (Prop_lut3_I0_O) 0.124 5.872 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[26]_inst_i_1/O - net (fo=2, routed) 3.104 8.975 ext_ram_data_IOBUF[26]_inst/I - AD20 OBUFT (Prop_obuft_I_O) 3.552 12.527 r ext_ram_data_IOBUF[26]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.527 ext_ram_data[26] - AD20 r ext_ram_data[26] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.527 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.830ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[19] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.845ns (logic 6.831ns (46.012%) route 8.015ns (53.988%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.476 9.006 base_ram_data_IOBUF[19]_inst/T - P19 OBUFT (TriStatE_obuft_T_O) - 3.518 12.524 r base_ram_data_IOBUF[19]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.524 base_ram_data[19] - P19 r base_ram_data[19] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.524 - ------------------------------------------------------------------- - slack 0.830 - -Slack (MET) : 0.836ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[2]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.109ns (logic 5.382ns (28.164%) route 13.727ns (71.836%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT3=1 LUT4=4 LUT5=2 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 1.005 16.243 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X71Y60 LUT3 (Prop_lut3_I1_O) 0.331 16.574 r u_matmul_axi_slave/crc_reg[2]_i_1/O - net (fo=1, routed) 0.000 16.574 u_matmul_axi_slave/crc32_word_next1_return[2] - SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X71Y60 FDSE r u_matmul_axi_slave/crc_reg_reg[2]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X71Y60 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[2] - ------------------------------------------------------------------- - required time 17.410 - arrival time -16.574 - ------------------------------------------------------------------- - slack 0.836 - -Slack (MET) : 0.845ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.830ns (logic 6.844ns (46.150%) route 7.986ns (53.850%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 1.799 6.608 u_snix_axil_cdma_mux_8ch/u_core_engine/soc_sram_addr[0] - SLICE_X0Y112 LUT6 (Prop_lut6_I5_O) 0.124 6.732 r u_snix_axil_cdma_mux_8ch/u_core_engine/base_ram_be_n_OBUF[0]_inst_i_1/O - net (fo=1, routed) 2.246 8.977 base_ram_be_n_OBUF[0] - L20 OBUF (Prop_obuf_I_O) 3.531 12.509 r base_ram_be_n_OBUF[0]_inst/O - net (fo=0) 0.000 12.509 base_ram_be_n[0] - L20 r base_ram_be_n[0] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.509 - ------------------------------------------------------------------- - slack 0.845 - -Slack (MET) : 0.860ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[17] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.912ns (logic 5.126ns (34.375%) route 9.786ns (65.625%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.285 2.617 u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/ADDRA1 - SLICE_X40Y73 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.741 r u_matmul_axi_slave/b1_c_reg_r2_0_15_48_53/RAMA_D1/O - net (fo=1, routed) 0.600 3.341 u_snix_axil_cdma_mux_8ch/ep_rd_c1[49] - SLICE_X35Y74 LUT6 (Prop_lut6_I0_O) 0.124 3.465 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_12_17_i_6__0/O - net (fo=2, routed) 0.596 4.061 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1_0 - SLICE_X34Y73 LUT5 (Prop_lut5_I3_O) 0.124 4.185 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_12_17_i_3__0/O - net (fo=2, routed) 1.313 5.498 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[17] - SLICE_X8Y69 LUT3 (Prop_lut3_I0_O) 0.124 5.622 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[17]_inst_i_1/O - net (fo=2, routed) 3.333 8.954 ext_ram_data_IOBUF[17]_inst/I - AC19 OBUFT (Prop_obuft_I_O) 3.540 12.494 r ext_ram_data_IOBUF[17]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.494 ext_ram_data[17] - AC19 r ext_ram_data[17] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.494 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.862ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[29] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.910ns (logic 5.133ns (34.429%) route 9.777ns (65.571%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.174 2.506 u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/ADDRA1 - SLICE_X36Y75 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.630 r u_matmul_axi_slave/b0_c_reg_r2_0_15_60_65/RAMA_D1/O - net (fo=1, routed) 0.969 3.598 u_snix_axil_cdma_mux_8ch/ep_rd_c0[61] - SLICE_X35Y72 LUT6 (Prop_lut6_I1_O) 0.124 3.722 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_26__0/O - net (fo=1, routed) 0.767 4.489 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[10][29]_i_2 - SLICE_X34Y70 LUT4 (Prop_lut4_I2_O) 0.124 4.613 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_11__0/O - net (fo=7, routed) 1.469 6.082 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_3 - SLICE_X6Y65 LUT3 (Prop_lut3_I0_O) 0.124 6.206 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[29]_inst_i_1/O - net (fo=2, routed) 2.740 8.945 ext_ram_data_IOBUF[29]_inst/I - AC21 OBUFT (Prop_obuft_I_O) 3.547 12.492 r ext_ram_data_IOBUF[29]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.492 ext_ram_data[29] - AC21 r ext_ram_data[29] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.492 - ------------------------------------------------------------------- - slack 0.862 - -Slack (MET) : 0.870ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[19]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.071ns (logic 5.382ns (28.221%) route 13.689ns (71.779%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.018ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.967 16.204 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X71Y64 LUT6 (Prop_lut6_I3_O) 0.331 16.535 r u_matmul_axi_slave/crc_reg[19]_i_1/O - net (fo=1, routed) 0.000 16.535 u_matmul_axi_slave/crc32_word_next1_return[19] - SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.701 17.873 u_matmul_axi_slave/sys_clk - SLICE_X71Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[19]/C - clock pessimism -0.426 17.446 - clock uncertainty -0.071 17.376 - SLICE_X71Y64 FDSE (Setup_fdse_C_D) 0.029 17.405 u_matmul_axi_slave/crc_reg_reg[19] - ------------------------------------------------------------------- - required time 17.405 - arrival time -16.535 - ------------------------------------------------------------------- - slack 0.870 - -Slack (MET) : 0.875ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[27] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.896ns (logic 5.131ns (34.446%) route 9.765ns (65.554%)) - Logic Levels: 9 (LUT3=1 LUT4=2 LUT5=2 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.268 2.600 u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/ADDRB1 - SLICE_X36Y69 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.724 r u_matmul_axi_slave/b0_c_reg_r2_0_15_24_29/RAMB_D1/O - net (fo=1, routed) 0.724 3.448 u_snix_axil_cdma_mux_8ch/ep_rd_c0[27] - SLICE_X34Y71 LUT6 (Prop_lut6_I1_O) 0.124 3.572 r u_snix_axil_cdma_mux_8ch/ram_reg_0_7_24_29_i_21__0/O - net (fo=1, routed) 0.977 4.549 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/b1_b[0][27]_i_2_1 - SLICE_X23Y72 LUT4 (Prop_lut4_I3_O) 0.124 4.673 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0_7_24_29_i_9__0/O - net (fo=6, routed) 1.188 5.861 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/dma_m_wdata[27] - SLICE_X0Y75 LUT3 (Prop_lut3_I0_O) 0.124 5.985 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[27]_inst_i_1/O - net (fo=2, routed) 2.949 8.934 ext_ram_data_IOBUF[27]_inst/I - AB21 OBUFT (Prop_obuft_I_O) 3.545 12.479 r ext_ram_data_IOBUF[27]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.479 ext_ram_data[27] - AB21 r ext_ram_data[27] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.479 - ------------------------------------------------------------------- - slack 0.875 - -Slack (MET) : 0.883ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[0] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.888ns (logic 5.398ns (36.257%) route 9.490ns (63.743%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.146 2.991 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA/O - net (fo=1, routed) 0.751 3.742 u_snix_axil_cdma_mux_8ch/ep_rd_c0[0] - SLICE_X34Y76 LUT6 (Prop_lut6_I1_O) 0.328 4.070 r u_snix_axil_cdma_mux_8ch/ram_reg_i_80/O - net (fo=1, routed) 0.416 4.485 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_0 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.609 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_48/O - net (fo=9, routed) 1.361 5.971 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_0 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 6.095 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[0]_inst_i_1/O - net (fo=2, routed) 2.790 8.885 ext_ram_data_IOBUF[0]_inst/I - AF24 OBUFT (Prop_obuft_I_O) 3.586 12.471 r ext_ram_data_IOBUF[0]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.471 ext_ram_data[0] - AF24 r ext_ram_data[0] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.471 - ------------------------------------------------------------------- - slack 0.883 - -Slack (MET) : 0.890ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_addr[16] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.786ns (logic 6.749ns (45.642%) route 8.037ns (54.358%)) - Logic Levels: 13 (CARRY4=7 LUT4=1 LUT5=1 LUT6=3 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.925 4.220 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X0Y70 LUT6 (Prop_lut6_I5_O) 0.313 4.533 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2/O - net (fo=2, routed) 0.648 5.181 u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_2_n_0 - SLICE_X0Y71 LUT6 (Prop_lut6_I1_O) 0.124 5.305 r u_axi_ram/u_axi_sram_sp/base_ram_addr_OBUF[16]_inst_i_1/O - net (fo=2, routed) 3.599 8.905 ext_ram_addr_OBUF[16] - AE17 OBUF (Prop_obuf_I_O) 3.560 12.464 r ext_ram_addr_OBUF[16]_inst/O - net (fo=0) 0.000 12.464 ext_ram_addr[16] - AE17 r ext_ram_addr[16] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.464 - ------------------------------------------------------------------- - slack 0.890 - -Slack (MET) : 0.905ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[18]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.087ns (logic 5.382ns (28.198%) route 13.705ns (71.802%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.983 16.220 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.551 r u_matmul_axi_slave/crc_reg[18]_i_1/O - net (fo=1, routed) 0.000 16.551 u_matmul_axi_slave/crc32_word_next1_return[18] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[18]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.077 17.456 u_matmul_axi_slave/crc_reg_reg[18] - ------------------------------------------------------------------- - required time 17.456 - arrival time -16.551 - ------------------------------------------------------------------- - slack 0.905 - -Slack (MET) : 0.911ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[25]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.085ns (logic 5.382ns (28.201%) route 13.703ns (71.799%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=2 LUT6=6) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.981 16.218 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT6 (Prop_lut6_I2_O) 0.331 16.549 r u_matmul_axi_slave/crc_reg[25]_i_1/O - net (fo=1, routed) 0.000 16.549 u_matmul_axi_slave/crc32_word_next1_return0[23] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[25]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.081 17.460 u_matmul_axi_slave/crc_reg_reg[25] - ------------------------------------------------------------------- - required time 17.460 - arrival time -16.549 - ------------------------------------------------------------------- - slack 0.911 - -Slack (MET) : 0.948ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.823ns (logic 5.154ns (34.770%) route 9.669ns (65.230%)) - Logic Levels: 9 (LUT3=1 LUT4=1 LUT5=3 LUT6=2 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.513 2.845 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRA1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.969 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMA_D1/O - net (fo=1, routed) 0.594 3.563 u_snix_axil_cdma_mux_8ch/ep_rd_c0[1] - SLICE_X33Y76 LUT6 (Prop_lut6_I1_O) 0.124 3.687 r u_snix_axil_cdma_mux_8ch/ram_reg_i_76/O - net (fo=1, routed) 0.580 4.267 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_3 - SLICE_X31Y76 LUT5 (Prop_lut5_I2_O) 0.124 4.391 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_i_47/O - net (fo=15, routed) 1.395 5.786 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg_1 - SLICE_X2Y77 LUT3 (Prop_lut3_I0_O) 0.124 5.910 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[1]_inst_i_1/O - net (fo=2, routed) 2.927 8.838 ext_ram_data_IOBUF[1]_inst/I - AE23 OBUFT (Prop_obuft_I_O) 3.568 12.406 r ext_ram_data_IOBUF[1]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.406 ext_ram_data[1] - AE23 r ext_ram_data[1] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.406 - ------------------------------------------------------------------- - slack 0.948 - -Slack (MET) : 0.949ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[26] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.726ns (logic 6.846ns (46.488%) route 7.880ns (53.512%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.342 8.872 base_ram_data_IOBUF[26]_inst/T - R21 OBUFT (TriStatE_obuft_T_O) - 3.533 12.405 r base_ram_data_IOBUF[26]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.405 base_ram_data[26] - R21 r base_ram_data[26] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.405 - ------------------------------------------------------------------- - slack 0.949 - -Slack (MET) : 0.959ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[13]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.035ns (logic 5.382ns (28.275%) route 13.653ns (71.725%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.931 16.168 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X68Y64 LUT4 (Prop_lut4_I1_O) 0.331 16.499 r u_matmul_axi_slave/crc_reg[13]_i_1/O - net (fo=1, routed) 0.000 16.499 u_matmul_axi_slave/crc32_word_next1_return[13] - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X68Y64 FDSE r u_matmul_axi_slave/crc_reg_reg[13]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X68Y64 FDSE (Setup_fdse_C_D) 0.079 17.458 u_matmul_axi_slave/crc_reg_reg[13] - ------------------------------------------------------------------- - required time 17.458 - arrival time -16.499 - ------------------------------------------------------------------- - slack 0.959 - -Slack (MET) : 0.962ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[29]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.029ns (logic 5.382ns (28.283%) route 13.647ns (71.717%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) - Clock Path Skew: -0.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X70Y62 LUT5 (Prop_lut5_I4_O) 0.331 16.493 r u_matmul_axi_slave/crc_reg[29]_i_1/O - net (fo=1, routed) 0.000 16.493 u_matmul_axi_slave/crc32_word_next1_return0[27] - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[29]/C - clock pessimism -0.426 17.447 - clock uncertainty -0.071 17.377 - SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.079 17.456 u_matmul_axi_slave/crc_reg_reg[29] - ------------------------------------------------------------------- - required time 17.456 - arrival time -16.493 - ------------------------------------------------------------------- - slack 0.962 - -Slack (MET) : 0.969ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[30]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 19.061ns (logic 5.414ns (28.404%) route 13.647ns (71.596%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=5 LUT5=2 LUT6=5) - Clock Path Skew: -0.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.126ns = ( 17.874 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.925 16.162 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X70Y62 LUT4 (Prop_lut4_I3_O) 0.363 16.525 r u_matmul_axi_slave/crc_reg[30]_i_1/O - net (fo=1, routed) 0.000 16.525 u_matmul_axi_slave/crc32_word_next1_return0[28] - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.702 17.874 u_matmul_axi_slave/sys_clk - SLICE_X70Y62 FDSE r u_matmul_axi_slave/crc_reg_reg[30]/C - clock pessimism -0.426 17.447 - clock uncertainty -0.071 17.377 - SLICE_X70Y62 FDSE (Setup_fdse_C_D) 0.118 17.495 u_matmul_axi_slave/crc_reg_reg[30] - ------------------------------------------------------------------- - required time 17.495 - arrival time -16.525 - ------------------------------------------------------------------- - slack 0.969 - -Slack (MET) : 0.971ns (required time - arrival time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/crc_reg_reg[27]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 18.975ns (logic 5.382ns (28.364%) route 13.593ns (71.636%)) - Logic Levels: 18 (CARRY4=3 LUT2=3 LUT4=4 LUT5=3 LUT6=5) - Clock Path Skew: -0.015ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.124ns = ( 17.876 - 20.000 ) - Source Clock Delay (SCD): -2.536ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.536 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X78Y70 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X78Y70 FDRE (Prop_fdre_C_Q) 0.456 -2.080 r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[0]/Q - net (fo=1, routed) 0.813 -1.266 u_matmul_axi_slave/mult_inst[0].u_mult/Q[0] - SLICE_X77Y70 LUT2 (Prop_lut2_I1_O) 0.124 -1.142 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21/O - net (fo=1, routed) 0.000 -1.142 u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_21_n_0 - SLICE_X77Y70 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.424 -0.718 r u_matmul_axi_slave/mult_inst[0].u_mult/b1_c_reg_r1_0_15_0_5_i_8/O[1] - net (fo=2, routed) 1.003 0.284 u_matmul_axi_slave/calc_c_result02_out[1] - SLICE_X78Y59 LUT2 (Prop_lut2_I0_O) 0.303 0.587 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11/O - net (fo=1, routed) 0.000 0.587 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_11_n_0 - SLICE_X78Y59 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.550 1.137 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2/CO[3] - net (fo=1, routed) 0.000 1.137 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_2_n_0 - SLICE_X78Y60 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.471 r u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3/O[1] - net (fo=8, routed) 0.827 2.298 u_matmul_axi_slave/b1_c_reg_r1_0_15_0_5_i_3_n_6 - SLICE_X75Y60 LUT4 (Prop_lut4_I1_O) 0.297 2.595 r u_matmul_axi_slave/crc_reg[23]_i_43/O - net (fo=7, routed) 0.699 3.294 u_matmul_axi_slave/crc_reg[23]_i_43_n_0 - SLICE_X76Y61 LUT5 (Prop_lut5_I1_O) 0.352 3.646 r u_matmul_axi_slave/crc_reg[27]_i_17/O - net (fo=10, routed) 0.677 4.322 u_matmul_axi_slave/crc32_word_next_return7[3] - SLICE_X77Y60 LUT6 (Prop_lut6_I3_O) 0.348 4.670 r u_matmul_axi_slave/crc_reg[12]_i_83/O - net (fo=7, routed) 1.059 5.729 u_matmul_axi_slave/crc32_word_next_return4[4] - SLICE_X79Y56 LUT4 (Prop_lut4_I2_O) 0.152 5.881 r u_matmul_axi_slave/crc_reg[20]_i_42/O - net (fo=1, routed) 0.408 6.289 u_matmul_axi_slave/crc32_word_next_return3[21] - SLICE_X79Y57 LUT6 (Prop_lut6_I0_O) 0.332 6.621 r u_matmul_axi_slave/crc_reg[20]_i_34/O - net (fo=1, routed) 1.157 7.779 u_matmul_axi_slave/crc_reg[20]_i_34_n_0 - SLICE_X79Y61 LUT6 (Prop_lut6_I5_O) 0.124 7.903 r u_matmul_axi_slave/crc_reg[20]_i_24/O - net (fo=8, routed) 1.078 8.980 u_matmul_axi_slave/crc32_word_next0_return7[4] - SLICE_X77Y62 LUT6 (Prop_lut6_I3_O) 0.124 9.104 r u_matmul_axi_slave/crc_reg[20]_i_16/O - net (fo=11, routed) 1.238 10.342 u_matmul_axi_slave/crc32_word_next0_return4[5] - SLICE_X75Y62 LUT2 (Prop_lut2_I0_O) 0.152 10.494 r u_matmul_axi_slave/crc_reg[23]_i_15/O - net (fo=6, routed) 0.667 11.161 u_matmul_axi_slave/crc_reg[23]_i_15_n_0 - SLICE_X76Y62 LUT6 (Prop_lut6_I4_O) 0.326 11.487 r u_matmul_axi_slave/crc_reg[30]_i_14/O - net (fo=1, routed) 1.194 12.681 u_matmul_axi_slave/p_0_in11_in[9] - SLICE_X73Y62 LUT4 (Prop_lut4_I1_O) 0.124 12.805 r u_matmul_axi_slave/crc_reg[30]_i_7/O - net (fo=10, routed) 0.845 13.650 u_matmul_axi_slave/crc32_word_next1_return7[1] - SLICE_X72Y61 LUT5 (Prop_lut5_I4_O) 0.152 13.802 r u_matmul_axi_slave/crc_reg[9]_i_2/O - net (fo=14, routed) 1.058 14.860 u_matmul_axi_slave/crc32_word_next1_return4[3] - SLICE_X70Y63 LUT4 (Prop_lut4_I3_O) 0.377 15.237 r u_matmul_axi_slave/crc_reg[31]_i_6/O - net (fo=15, routed) 0.871 16.108 u_matmul_axi_slave/crc32_word_next1_return1[1] - SLICE_X69Y63 LUT5 (Prop_lut5_I3_O) 0.331 16.439 r u_matmul_axi_slave/crc_reg[27]_i_1/O - net (fo=1, routed) 0.000 16.439 u_matmul_axi_slave/crc32_word_next1_return0[25] - SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.704 17.876 u_matmul_axi_slave/sys_clk - SLICE_X69Y63 FDSE r u_matmul_axi_slave/crc_reg_reg[27]/C - clock pessimism -0.426 17.449 - clock uncertainty -0.071 17.379 - SLICE_X69Y63 FDSE (Setup_fdse_C_D) 0.031 17.410 u_matmul_axi_slave/crc_reg_reg[27] - ------------------------------------------------------------------- - required time 17.410 - arrival time -16.439 - ------------------------------------------------------------------- - slack 0.971 - -Slack (MET) : 1.008ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[5] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.764ns (logic 5.026ns (34.045%) route 9.738ns (65.955%)) - Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O - net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] - SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O - net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 - SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O - net (fo=2, routed) 3.685 8.782 ext_ram_data_IOBUF[5]_inst/I - AE21 OBUFT (Prop_obuft_I_O) 3.564 12.347 r ext_ram_data_IOBUF[5]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.347 ext_ram_data[5] - AE21 r ext_ram_data[5] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.347 - ------------------------------------------------------------------- - slack 1.008 - -Slack (MET) : 1.012ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[27] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.664ns (logic 6.836ns (46.615%) route 7.828ns (53.385%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 f u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 f u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.598 5.406 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X0Y75 LUT3 (Prop_lut3_I2_O) 0.124 5.530 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/base_ram_data_IOBUF[31]_inst_i_3/O - net (fo=32, routed) 3.290 8.820 base_ram_data_IOBUF[27]_inst/T - P20 OBUFT (TriStatE_obuft_T_O) - 3.523 12.342 r base_ram_data_IOBUF[27]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.342 base_ram_data[27] - P20 r base_ram_data[27] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.342 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.016ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[3] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.660ns (logic 6.906ns (47.111%) route 7.753ns (52.889%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.950 8.745 ext_ram_data_IOBUF[3]_inst/T - AE22 OBUFT (TriStatE_obuft_T_O) - 3.593 12.338 r ext_ram_data_IOBUF[3]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.338 ext_ram_data[3] - AE22 r ext_ram_data[3] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.338 - ------------------------------------------------------------------- - slack 1.016 - -Slack (MET) : 1.017ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_be_n[1] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.659ns (logic 6.844ns (46.685%) route 7.815ns (53.314%)) - Logic Levels: 14 (CARRY4=7 LUT4=1 LUT5=1 LUT6=4 OBUF=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 1.983 6.791 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/soc_sram_addr[0] - SLICE_X0Y121 LUT6 (Prop_lut6_I5_O) 0.124 6.915 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_be_n_OBUF[1]_inst_i_1/O - net (fo=1, routed) 1.892 8.807 base_ram_be_n_OBUF[1] - L22 OBUF (Prop_obuf_I_O) 3.531 12.337 r base_ram_be_n_OBUF[1]_inst/O - net (fo=0) 0.000 12.337 base_ram_be_n[1] - L22 r base_ram_be_n[1] (OUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.337 - ------------------------------------------------------------------- - slack 1.017 - -Slack (MET) : 1.017ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[4] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.659ns (logic 6.905ns (47.105%) route 7.754ns (52.895%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.951 8.745 ext_ram_data_IOBUF[4]_inst/T - AF22 OBUFT (TriStatE_obuft_T_O) - 3.592 12.337 r ext_ram_data_IOBUF[4]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.337 ext_ram_data[4] - AF22 r ext_ram_data[4] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.337 - ------------------------------------------------------------------- - slack 1.017 - -Slack (MET) : 1.018ns (required time - arrival time) - Source: u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: base_ram_data[5] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.754ns (logic 5.001ns (33.893%) route 9.753ns (66.107%)) - Logic Levels: 8 (LUT4=1 LUT5=2 LUT6=3 OBUFT=1 RAMD32=1) - Output Delay: 0.300ns - Clock Path Skew: -3.858ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.418ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 -2.418 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X33Y70 FDRE r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y70 FDRE (Prop_fdre_C_Q) 0.419 -1.999 r u_snix_axil_cdma_mux_8ch/FSM_sequential_ext_wr_state_reg[1]/Q - net (fo=77, routed) 0.714 -1.284 u_snix_axil_cdma_mux_8ch/ext_wr_state__0[1] - SLICE_X34Y69 LUT4 (Prop_lut4_I2_O) 0.299 -0.985 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_6/O - net (fo=5, routed) 0.809 -0.176 u_snix_axil_cdma_mux_8ch/matmul_ep_rd_word_addr[5] - SLICE_X35Y70 LUT6 (Prop_lut6_I1_O) 0.124 -0.052 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9/O - net (fo=3, routed) 0.466 0.414 u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_9_n_0 - SLICE_X35Y72 LUT5 (Prop_lut5_I4_O) 0.124 0.538 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_1/O - net (fo=134, routed) 0.670 1.208 u_snix_axil_cdma_mux_8ch/ADDRA[3] - SLICE_X37Y72 LUT5 (Prop_lut5_I3_O) 0.124 1.332 r u_snix_axil_cdma_mux_8ch/b1_c_reg_r2_0_15_0_5_i_3/O - net (fo=132, routed) 1.515 2.847 u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/ADDRC1 - SLICE_X36Y78 RAMD32 (Prop_ramd32_RADR1_O) - 0.124 2.971 r u_matmul_axi_slave/b0_c_reg_r2_0_15_0_5/RAMC_D1/O - net (fo=1, routed) 0.999 3.970 u_snix_axil_cdma_mux_8ch/ep_rd_c0[5] - SLICE_X38Y78 LUT6 (Prop_lut6_I1_O) 0.124 4.094 r u_snix_axil_cdma_mux_8ch/ram_reg_i_37/O - net (fo=3, routed) 0.879 4.973 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/ram_reg_29 - SLICE_X43Y73 LUT6 (Prop_lut6_I3_O) 0.124 5.097 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/base_ram_data_IOBUF[5]_inst_i_1/O - net (fo=2, routed) 3.700 8.798 base_ram_data_IOBUF[5]_inst/I - P24 OBUFT (Prop_obuft_I_O) 3.539 12.336 r base_ram_data_IOBUF[5]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.336 base_ram_data[5] - P24 r base_ram_data[5] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.336 - ------------------------------------------------------------------- - slack 1.018 - -Slack (MET) : 1.019ns (required time - arrival time) - Source: u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: ext_ram_data[30] - (output port clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Max at Slow Process Corner - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.656ns (logic 6.857ns (46.787%) route 7.799ns (53.213%)) - Logic Levels: 14 (CARRY4=7 LUT3=1 LUT4=1 LUT5=1 LUT6=3 OBUFT=1) - Output Delay: 0.300ns - Clock Path Skew: -3.954ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -5.674ns = ( 14.326 - 20.000 ) - Source Clock Delay (SCD): -2.322ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.020 -2.322 u_axi_ram/u_axi_sram_sp/sys_clk - SLICE_X7Y63 FDCE r u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y63 FDCE (Prop_fdce_C_Q) 0.456 -1.866 f u_axi_ram/u_axi_sram_sp/ax_req_q_len_reg[0]/Q - net (fo=15, routed) 0.885 -0.981 u_axi_ram/u_axi_sram_sp/len[0] - SLICE_X4Y63 LUT4 (Prop_lut4_I0_O) 0.124 -0.857 r u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6/O - net (fo=4, routed) 0.710 -0.147 u_axi_ram/u_axi_sram_sp/state_d1_carry_i_6_n_0 - SLICE_X4Y63 LUT5 (Prop_lut5_I1_O) 0.124 -0.023 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_11/O - net (fo=2, routed) 0.497 0.475 u_axi_ram/u_axi_sram_sp/state_d2[7] - SLICE_X1Y63 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.385 0.860 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9/CO[3] - net (fo=1, routed) 0.000 0.860 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry_i_9_n_0 - SLICE_X1Y64 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 0.974 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10/CO[3] - net (fo=1, routed) 0.000 0.974 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_10_n_0 - SLICE_X1Y65 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.088 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9/CO[3] - net (fo=1, routed) 0.000 1.088 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__0_i_9_n_0 - SLICE_X1Y66 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.202 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11/CO[3] - net (fo=1, routed) 0.000 1.202 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_11_n_0 - SLICE_X1Y67 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.316 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10/CO[3] - net (fo=1, routed) 0.000 1.316 u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__1_i_10_n_0 - SLICE_X1Y68 CARRY4 (Prop_carry4_CI_O[1]) - 0.334 1.650 r u_axi_ram/u_axi_sram_sp/req_addr_d1_carry__2_i_9/O[1] - net (fo=3, routed) 0.773 2.422 u_axi_ram/u_axi_sram_sp/upper_wrap_boundary[27] - SLICE_X0Y67 LUT6 (Prop_lut6_I5_O) 0.303 2.725 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2/O - net (fo=1, routed) 0.000 2.725 u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1_i_2_n_0 - SLICE_X0Y67 CARRY4 (Prop_carry4_S[1]_CO[2]) - 0.570 3.295 r u_axi_ram/u_axi_sram_sp/req_addr_d1__15_carry__1/CO[2] - net (fo=23, routed) 0.751 4.046 u_axi_ram/u_axi_sram_sp/req_addr_d10_in - SLICE_X3Y73 LUT6 (Prop_lut6_I5_O) 0.313 4.359 r u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7/O - net (fo=2, routed) 0.325 4.684 u_axi_ram/u_axi_sram_sp/req_addr_q[22]_i_7_n_0 - SLICE_X5Y74 LUT6 (Prop_lut6_I1_O) 0.124 4.808 r u_axi_ram/u_axi_sram_sp/base_ram_be_n_OBUF[3]_inst_i_6/O - net (fo=80, routed) 0.862 5.670 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/soc_sram_addr[0] - SLICE_X3Y71 LUT3 (Prop_lut3_I2_O) 0.124 5.794 f u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdArbiter/ext_ram_data_IOBUF[31]_inst_i_2/O - net (fo=32, routed) 2.996 8.790 ext_ram_data_IOBUF[30]_inst/T - AA19 OBUFT (TriStatE_obuft_T_O) - 3.544 12.335 r ext_ram_data_IOBUF[30]_inst/OBUFT/O - net (fo=1, unset) 0.000 12.335 ext_ram_data[30] - AA19 r ext_ram_data[30] (INOUT) - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - clock pessimism -0.601 13.725 - clock uncertainty -0.071 13.654 - output delay -0.300 13.354 - ------------------------------------------------------------------- - required time 13.354 - arrival time -12.335 - ------------------------------------------------------------------- - slack 1.019 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: sys_clk -Waveform(ns): { 0.000 10.000 } -Period(ns): 20.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I -Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C -Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 14.363ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 14.363ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.986ns (logic 1.344ns (26.958%) route 3.642ns (73.042%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.827 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 3.642 22.469 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[12] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.260 36.832 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 36.832 - arrival time -22.469 - ------------------------------------------------------------------- - slack 14.363 - -Slack (MET) : 14.642ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.902ns (logic 1.317ns (26.864%) route 3.585ns (73.136%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.800 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 3.585 22.386 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[15] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.064 37.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 37.028 - arrival time -22.386 - ------------------------------------------------------------------- - slack 14.642 - -Slack (MET) : 14.889ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.419ns (logic 1.344ns (30.411%) route 3.075ns (69.589%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 3.075 21.905 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[18] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.299 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 36.794 - arrival time -21.905 - ------------------------------------------------------------------- - slack 14.889 - -Slack (MET) : 15.059ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.297ns (logic 1.336ns (31.089%) route 2.961ns (68.911%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 2.961 21.783 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[28] - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.252 36.842 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 36.842 - arrival time -21.783 - ------------------------------------------------------------------- - slack 15.059 - -Slack (MET) : 15.085ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.257ns (logic 1.344ns (31.570%) route 2.913ns (68.429%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.829 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 2.913 21.743 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[24] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.266 36.827 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 36.827 - arrival time -21.743 - ------------------------------------------------------------------- - slack 15.085 - -Slack (MET) : 15.131ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.202ns (logic 1.344ns (31.982%) route 2.858ns (68.018%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.511ns = ( 17.489 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.831 17.489 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/WCLK - SLICE_X56Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_36_36/RAMA/O - net (fo=1, routed) 2.858 21.692 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[36] - SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X110Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X110Y71 FDRE (Setup_fdre_C_D) -0.271 36.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 36.823 - arrival time -21.692 - ------------------------------------------------------------------- - slack 15.131 - -Slack (MET) : 15.149ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.015ns (logic 1.344ns (33.474%) route 2.671ns (66.526%)) - Logic Levels: 0 - Clock Path Skew: -0.327ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 2.671 21.597 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[6] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.313 36.746 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.746 - arrival time -21.597 - ------------------------------------------------------------------- - slack 15.149 - -Slack (MET) : 15.187ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.166ns (logic 1.336ns (32.067%) route 2.830ns (67.933%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.821 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 2.830 21.652 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[22] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.254 36.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 36.839 - arrival time -21.652 - ------------------------------------------------------------------- - slack 15.187 - -Slack (MET) : 15.190ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.336ns (logic 1.314ns (30.303%) route 3.022ns (69.697%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 3.022 21.822 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[23] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.081 37.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 37.012 - arrival time -21.822 - ------------------------------------------------------------------- - slack 15.190 - -Slack (MET) : 15.238ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.936ns (logic 1.344ns (34.149%) route 2.592ns (65.851%)) - Logic Levels: 0 - Clock Path Skew: -0.321ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) - Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.924 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 2.592 21.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[0] - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.260 - clock uncertainty -0.197 37.063 - SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.309 36.754 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.754 - arrival time -21.516 - ------------------------------------------------------------------- - slack 15.238 - -Slack (MET) : 15.346ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.027ns (logic 1.336ns (33.179%) route 2.691ns (66.821%)) - Logic Levels: 0 - Clock Path Skew: -0.193ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 2.691 21.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[16] - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X116Y76 FDRE (Setup_fdre_C_D) -0.238 36.856 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 36.856 - arrival time -21.510 - ------------------------------------------------------------------- - slack 15.346 - -Slack (MET) : 15.359ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.218ns (logic 1.317ns (31.224%) route 2.901ns (68.776%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.807 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 2.901 21.708 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[3] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.028 37.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 37.067 - arrival time -21.708 - ------------------------------------------------------------------- - slack 15.359 - -Slack (MET) : 15.360ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.008ns (logic 1.336ns (33.331%) route 2.672ns (66.669%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 2.672 21.499 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[4] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.237 36.858 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 36.858 - arrival time -21.499 - ------------------------------------------------------------------- - slack 15.360 - -Slack (MET) : 15.365ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.184ns (logic 1.309ns (31.283%) route 2.875ns (68.717%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.792 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 2.875 21.668 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[13] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.059 37.033 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 37.033 - arrival time -21.668 - ------------------------------------------------------------------- - slack 15.365 - -Slack (MET) : 15.371ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.144ns (logic 1.309ns (31.591%) route 2.835ns (68.409%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 2.835 21.629 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[19] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.093 37.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 37.000 - arrival time -21.629 - ------------------------------------------------------------------- - slack 15.371 - -Slack (MET) : 15.375ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.000ns (logic 1.309ns (32.724%) route 2.691ns (67.276%)) - Logic Levels: 0 - Clock Path Skew: -0.327ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.891 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 2.691 21.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[7] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.102 36.957 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 36.957 - arrival time -21.583 - ------------------------------------------------------------------- - slack 15.375 - -Slack (MET) : 15.382ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.988ns (logic 1.344ns (33.703%) route 2.644ns (66.297%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.834 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 2.644 21.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[0] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.860 - arrival time -21.478 - ------------------------------------------------------------------- - slack 15.382 - -Slack (MET) : 15.406ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.814ns (logic 1.344ns (35.240%) route 2.470ns (64.760%)) - Logic Levels: 0 - Clock Path Skew: -0.324ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 2.470 21.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[0] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.260 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 36.795 - arrival time -21.389 - ------------------------------------------------------------------- - slack 15.406 - -Slack (MET) : 15.426ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.896ns (logic 1.343ns (34.471%) route 2.553ns (65.529%)) - Logic Levels: 0 - Clock Path Skew: -0.195ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.826 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 2.553 21.379 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[14] - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 37.289 - clock uncertainty -0.197 37.092 - SLICE_X116Y74 FDRE (Setup_fdre_C_D) -0.287 36.805 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 36.805 - arrival time -21.379 - ------------------------------------------------------------------- - slack 15.426 - -Slack (MET) : 15.429ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.762ns (logic 1.343ns (35.695%) route 2.419ns (64.305%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.919 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 2.419 21.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[8] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.287 36.768 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 36.768 - arrival time -21.339 - ------------------------------------------------------------------- - slack 15.429 - -Slack (MET) : 15.440ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.128ns (logic 1.314ns (31.835%) route 2.814ns (68.165%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 2.814 21.613 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[29] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.040 37.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 37.053 - arrival time -21.613 - ------------------------------------------------------------------- - slack 15.440 - -Slack (MET) : 15.459ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.955ns (logic 1.317ns (33.302%) route 2.638ns (66.698%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.893 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMB_D1/O - net (fo=1, routed) 2.638 21.531 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[9] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.065 36.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 36.990 - arrival time -21.531 - ------------------------------------------------------------------- - slack 15.459 - -Slack (MET) : 15.477ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.733ns (logic 1.336ns (35.784%) route 2.397ns (64.216%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.147ns = ( 37.853 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.912 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 2.397 21.310 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[10] - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.681 37.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X84Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 37.252 - clock uncertainty -0.197 37.055 - SLICE_X84Y72 FDRE (Setup_fdre_C_D) -0.268 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 36.787 - arrival time -21.310 - ------------------------------------------------------------------- - slack 15.477 - -Slack (MET) : 15.480ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.063ns (logic 1.314ns (32.340%) route 2.749ns (67.660%)) - Logic Levels: 0 - Clock Path Skew: -0.194ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.517ns = ( 17.483 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.825 17.483 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X56Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.797 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 2.749 21.547 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[17] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.067 37.026 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 37.026 - arrival time -21.547 - ------------------------------------------------------------------- - slack 15.480 - -Slack (MET) : 15.482ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.864ns (logic 1.344ns (34.786%) route 2.520ns (65.214%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.822 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 2.520 21.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[30] - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.271 36.824 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 36.824 - arrival time -21.342 - ------------------------------------------------------------------- - slack 15.482 - -Slack (MET) : 15.506ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.864ns (logic 1.317ns (34.080%) route 2.547ns (65.920%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.900 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB_D1/O - net (fo=1, routed) 2.547 21.448 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[15] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.105 36.954 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 36.954 - arrival time -21.448 - ------------------------------------------------------------------- - slack 15.506 - -Slack (MET) : 15.550ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.822ns (logic 1.309ns (34.245%) route 2.513ns (65.755%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.143ns = ( 37.857 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMA_D1/O - net (fo=1, routed) 2.513 21.406 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[13] - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.685 37.857 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y66 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 37.256 - clock uncertainty -0.197 37.059 - SLICE_X78Y66 FDRE (Setup_fdre_C_D) -0.103 36.956 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 36.956 - arrival time -21.406 - ------------------------------------------------------------------- - slack 15.550 - -Slack (MET) : 15.552ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.834ns (logic 1.309ns (34.141%) route 2.525ns (65.859%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.884 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 2.525 21.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[1] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.093 36.961 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 36.961 - arrival time -21.410 - ------------------------------------------------------------------- - slack 15.552 - -Slack (MET) : 15.552ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 4.012ns (logic 1.317ns (32.824%) route 2.695ns (67.176%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 2.695 21.498 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[27] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.043 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 37.050 - arrival time -21.498 - ------------------------------------------------------------------- - slack 15.552 - -Slack (MET) : 15.555ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.961ns (logic 1.317ns (33.248%) route 2.644ns (66.752%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.802 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 2.644 21.447 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[21] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.092 37.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 37.001 - arrival time -21.447 - ------------------------------------------------------------------- - slack 15.555 - -Slack (MET) : 15.555ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.607ns (logic 1.343ns (37.237%) route 2.264ns (62.763%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 2.264 21.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[2] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.317 36.737 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 36.737 - arrival time -21.182 - ------------------------------------------------------------------- - slack 15.555 - -Slack (MET) : 15.654ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.719ns (logic 1.309ns (35.195%) route 2.410ns (64.805%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.150ns = ( 37.850 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.885 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 2.410 21.296 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[7] - SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.678 37.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X78Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 37.249 - clock uncertainty -0.197 37.052 - SLICE_X78Y72 FDRE (Setup_fdre_C_D) -0.103 36.949 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 36.949 - arrival time -21.296 - ------------------------------------------------------------------- - slack 15.654 - -Slack (MET) : 15.659ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.762ns (logic 1.317ns (35.012%) route 2.445ns (64.988%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.892 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 2.445 21.337 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[3] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.058 36.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 36.996 - arrival time -21.337 - ------------------------------------------------------------------- - slack 15.659 - -Slack (MET) : 15.683ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.690ns (logic 1.309ns (35.473%) route 2.381ns (64.527%)) - Logic Levels: 0 - Clock Path Skew: -0.328ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) - Source Clock Delay (SCD): -2.420ns = ( 17.580 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.922 17.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 2.381 21.271 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[1] - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.253 - clock uncertainty -0.197 37.056 - SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.103 36.953 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 36.953 - arrival time -21.271 - ------------------------------------------------------------------- - slack 15.683 - -Slack (MET) : 15.729ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.413ns (logic 1.343ns (39.347%) route 2.070ns (60.653%)) - Logic Levels: 0 - Clock Path Skew: -0.330ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.146ns = ( 37.854 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.925 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 2.070 20.996 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[8] - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.682 37.854 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X78Y68 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 37.253 - clock uncertainty -0.197 37.056 - SLICE_X78Y68 FDRE (Setup_fdre_C_D) -0.332 36.724 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 36.724 - arrival time -20.996 - ------------------------------------------------------------------- - slack 15.729 - -Slack (MET) : 15.768ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.779ns (logic 1.309ns (34.643%) route 2.470ns (65.357%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.794 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 2.470 21.264 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[25] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.061 37.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[25] - ------------------------------------------------------------------- - required time 37.032 - arrival time -21.264 - ------------------------------------------------------------------- - slack 15.768 - -Slack (MET) : 15.770ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.381ns (logic 1.343ns (39.723%) route 2.038ns (60.277%)) - Logic Levels: 0 - Clock Path Skew: -0.324ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.139ns = ( 37.861 - 40.000 ) - Source Clock Delay (SCD): -2.417ns = ( 17.583 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.925 17.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X36Y66 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y66 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.926 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 2.038 20.964 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[14] - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.689 37.861 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X77Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 37.260 - clock uncertainty -0.197 37.063 - SLICE_X77Y70 FDRE (Setup_fdre_C_D) -0.329 36.734 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 36.734 - arrival time -20.964 - ------------------------------------------------------------------- - slack 15.770 - -Slack (MET) : 15.794ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.497ns (logic 1.343ns (38.409%) route 2.154ns (61.591%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X56Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 2.154 20.982 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[20] - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X115Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X115Y76 FDRE (Setup_fdre_C_D) -0.317 36.776 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 36.776 - arrival time -20.982 - ------------------------------------------------------------------- - slack 15.794 - -Slack (MET) : 15.816ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.720ns (logic 1.309ns (35.188%) route 2.411ns (64.812%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.787 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 2.411 21.198 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[31] - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X117Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X117Y77 FDRE (Setup_fdre_C_D) -0.081 37.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time 37.014 - arrival time -21.198 - ------------------------------------------------------------------- - slack 15.816 - -Slack (MET) : 15.821ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.408ns (logic 1.336ns (39.197%) route 2.072ns (60.803%)) - Logic Levels: 0 - Clock Path Skew: -0.320ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.136ns = ( 37.864 - 40.000 ) - Source Clock Delay (SCD): -2.418ns = ( 17.582 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.924 17.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.918 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 2.072 20.991 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[10] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.692 37.864 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 37.263 - clock uncertainty -0.197 37.066 - SLICE_X76Y67 FDRE (Setup_fdre_C_D) -0.254 36.812 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 36.812 - arrival time -20.991 - ------------------------------------------------------------------- - slack 15.821 - -Slack (MET) : 15.826ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.590ns (logic 1.314ns (36.599%) route 2.276ns (63.401%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.889 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC_D1/O - net (fo=1, routed) 2.276 21.166 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[5] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.062 36.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 36.992 - arrival time -21.166 - ------------------------------------------------------------------- - slack 15.826 - -Slack (MET) : 15.830ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.395ns (logic 1.336ns (39.356%) route 2.059ns (60.644%)) - Logic Levels: 0 - Clock Path Skew: -0.325ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.425ns = ( 17.575 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.917 17.575 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X40Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y71 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.911 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 2.059 20.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[4] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.254 36.800 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 36.800 - arrival time -20.970 - ------------------------------------------------------------------- - slack 15.830 - -Slack (MET) : 15.834ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.501ns (logic 1.343ns (38.357%) route 2.158ns (61.643%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.833 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 2.158 20.992 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[2] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.269 36.826 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 36.826 - arrival time -20.992 - ------------------------------------------------------------------- - slack 15.834 - -Slack (MET) : 15.836ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.395ns (logic 1.344ns (39.592%) route 2.051ns (60.408%)) - Logic Levels: 0 - Clock Path Skew: -0.326ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.148ns = ( 37.852 - 40.000 ) - Source Clock Delay (SCD): -2.424ns = ( 17.576 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.918 17.576 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X40Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X40Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.920 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 2.051 20.971 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[6] - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.680 37.852 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X81Y71 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.251 - clock uncertainty -0.197 37.054 - SLICE_X81Y71 FDRE (Setup_fdre_C_D) -0.247 36.807 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.807 - arrival time -20.971 - ------------------------------------------------------------------- - slack 15.836 - -Slack (MET) : 15.842ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.469ns (logic 1.344ns (38.739%) route 2.125ns (61.261%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.525ns = ( 17.475 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.475 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 1.344 18.819 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 2.125 20.945 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[6] - SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 37.291 - clock uncertainty -0.197 37.094 - SLICE_X114Y72 FDRE (Setup_fdre_C_D) -0.307 36.787 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 36.787 - arrival time -20.945 - ------------------------------------------------------------------- - slack 15.842 - -Slack (MET) : 15.908ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.473ns (logic 1.336ns (38.463%) route 2.137ns (61.537%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.336 18.814 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 2.137 20.952 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[34] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.235 36.860 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 36.860 - arrival time -20.952 - ------------------------------------------------------------------- - slack 15.908 - -Slack (MET) : 15.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.613ns (logic 1.317ns (36.447%) route 2.296ns (63.553%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.522ns = ( 17.478 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.820 17.478 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.317 18.795 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 2.296 21.092 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[33] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X116Y77 FDRE (Setup_fdre_C_D) -0.045 37.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 37.050 - arrival time -21.092 - ------------------------------------------------------------------- - slack 15.958 - -Slack (MET) : 15.958ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.633ns (logic 1.314ns (36.165%) route 2.319ns (63.835%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.314 18.804 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 2.319 21.124 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[5] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.013 37.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 37.082 - arrival time -21.124 - ------------------------------------------------------------------- - slack 15.958 - -Slack (MET) : 15.961ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.365ns (logic 1.343ns (39.913%) route 2.022ns (60.087%)) - Logic Levels: 0 - Clock Path Skew: -0.196ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.515ns = ( 17.485 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.827 17.485 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X60Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X60Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 18.828 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 2.022 20.850 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[26] - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X113Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26]/C - clock pessimism -0.601 37.290 - clock uncertainty -0.197 37.093 - SLICE_X113Y76 FDRE (Setup_fdre_C_D) -0.282 36.811 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 36.811 - arrival time -20.850 - ------------------------------------------------------------------- - slack 15.961 - -Slack (MET) : 15.990ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 3.572ns (logic 1.309ns (36.651%) route 2.263ns (63.349%)) - Logic Levels: 0 - Clock Path Skew: -0.199ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.107ns = ( 37.893 - 40.000 ) - Source Clock Delay (SCD): -2.510ns = ( 17.490 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.832 17.490 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X56Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X56Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.309 18.799 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 2.263 21.062 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[1] - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.721 37.893 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X108Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 37.292 - clock uncertainty -0.197 37.095 - SLICE_X108Y70 FDRE (Setup_fdre_C_D) -0.043 37.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 37.052 - arrival time -21.062 - ------------------------------------------------------------------- - slack 15.990 - - - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 16.175ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 16.175ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.211ns (logic 1.343ns (41.819%) route 1.868ns (58.181%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.178 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 1.868 0.691 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[14] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.305 16.866 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 16.866 - arrival time -0.691 - ------------------------------------------------------------------- - slack 16.175 - -Slack (MET) : 16.288ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.133ns (logic 1.344ns (42.898%) route 1.789ns (57.102%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 1.789 0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[12] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 16.900 - arrival time -0.612 - ------------------------------------------------------------------- - slack 16.288 - -Slack (MET) : 16.322ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.253ns (logic 1.309ns (40.244%) route 1.944ns (59.756%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 1.944 0.738 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[7] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.109 17.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[7] - ------------------------------------------------------------------- - required time 17.060 - arrival time -0.738 - ------------------------------------------------------------------- - slack 16.322 - -Slack (MET) : 16.382ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.989ns (logic 1.343ns (44.934%) route 1.646ns (55.066%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.173 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 1.646 0.473 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[2] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.316 16.855 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 16.855 - arrival time -0.473 - ------------------------------------------------------------------- - slack 16.382 - -Slack (MET) : 16.446ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.152ns (logic 1.309ns (41.524%) route 1.843ns (58.476%)) - Logic Levels: 0 - Clock Path Skew: -0.112ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.212 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 1.843 0.632 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[13] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 17.078 - arrival time -0.632 - ------------------------------------------------------------------- - slack 16.446 - -Slack (MET) : 16.520ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.917ns (logic 1.336ns (45.800%) route 1.581ns (54.200%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 1.581 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[4] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.250 16.921 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 16.921 - arrival time -0.401 - ------------------------------------------------------------------- - slack 16.520 - -Slack (MET) : 16.587ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.822ns (logic 1.336ns (47.335%) route 1.486ns (52.665%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 1.486 0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[10] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.274 16.895 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[10] - ------------------------------------------------------------------- - required time 16.895 - arrival time -0.308 - ------------------------------------------------------------------- - slack 16.587 - -Slack (MET) : 16.599ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.995ns (logic 1.309ns (43.709%) route 1.686ns (56.291%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 1.686 0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[1] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.093 17.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[1] - ------------------------------------------------------------------- - required time 17.078 - arrival time -0.479 - ------------------------------------------------------------------- - slack 16.599 - -Slack (MET) : 16.680ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.736ns (logic 1.344ns (49.121%) route 1.392ns (50.879%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 1.392 0.221 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[0] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.271 16.900 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[0] - ------------------------------------------------------------------- - required time 16.900 - arrival time -0.221 - ------------------------------------------------------------------- - slack 16.680 - -Slack (MET) : 16.714ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.930ns (logic 1.314ns (44.850%) route 1.616ns (55.150%)) - Logic Levels: 0 - Clock Path Skew: -0.117ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 1.616 0.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.043 17.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time 17.128 - arrival time -0.414 - ------------------------------------------------------------------- - slack 16.714 - -Slack (MET) : 16.930ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.383ns (logic 1.343ns (56.369%) route 1.040ns (43.631%)) - Logic Levels: 0 - Clock Path Skew: -0.205ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.177 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 1.040 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.286 16.793 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 16.793 - arrival time 0.137 - ------------------------------------------------------------------- - slack 16.930 - -Slack (MET) : 16.970ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.472ns (logic 1.344ns (54.377%) route 1.128ns (45.623%)) - Logic Levels: 0 - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.171 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 1.128 -0.043 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X28Y76 FDRE (Setup_fdre_C_D) -0.244 16.927 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 16.927 - arrival time 0.043 - ------------------------------------------------------------------- - slack 16.970 - -Slack (MET) : 16.987ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.297ns (logic 1.343ns (58.459%) route 0.954ns (41.541%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.180 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.954 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.317 16.762 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 16.762 - arrival time 0.225 - ------------------------------------------------------------------- - slack 16.987 - -Slack (MET) : 16.991ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.542ns (logic 1.317ns (51.811%) route 1.225ns (48.189%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.097 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 1.225 0.128 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.061 17.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 17.119 - arrival time -0.128 - ------------------------------------------------------------------- - slack 16.991 - -Slack (MET) : 17.017ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.587ns (logic 1.317ns (50.909%) route 1.270ns (49.091%)) - Logic Levels: 0 - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.516ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.826 -2.516 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.199 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 1.270 0.071 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.081 17.088 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time 17.088 - arrival time -0.071 - ------------------------------------------------------------------- - slack 17.017 - -Slack (MET) : 17.045ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.595ns (logic 1.317ns (50.744%) route 1.278ns (49.256%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.198 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 1.278 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.043 17.126 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 17.126 - arrival time -0.081 - ------------------------------------------------------------------- - slack 17.045 - -Slack (MET) : 17.067ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.418ns (logic 0.456ns (18.857%) route 1.962ns (81.143%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.419ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.456 -1.963 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 1.962 -0.000 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X24Y73 FDCE (Setup_fdce_C_D) -0.105 17.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.067 - arrival time 0.000 - ------------------------------------------------------------------- - slack 17.067 - -Slack (MET) : 17.092ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.462ns (logic 1.314ns (53.376%) route 1.148ns (46.624%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 1.148 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.043 17.034 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 17.034 - arrival time 0.058 - ------------------------------------------------------------------- - slack 17.092 - -Slack (MET) : 17.095ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.436ns (logic 1.317ns (54.066%) route 1.119ns (45.934%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.092 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 1.119 0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.061 17.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time 17.122 - arrival time -0.027 - ------------------------------------------------------------------- - slack 17.095 - -Slack (MET) : 17.100ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.301ns (logic 1.343ns (58.359%) route 0.958ns (41.641%)) - Logic Levels: 0 - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.172 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.958 -0.213 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X31Y75 FDRE (Setup_fdre_C_D) -0.282 16.887 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 16.887 - arrival time 0.213 - ------------------------------------------------------------------- - slack 17.100 - -Slack (MET) : 17.150ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.212ns (logic 1.336ns (60.403%) route 0.876ns (39.597%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.876 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.238 16.839 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 16.839 - arrival time 0.311 - ------------------------------------------------------------------- - slack 17.150 - -Slack (MET) : 17.198ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.407ns (logic 1.314ns (54.587%) route 1.093ns (45.413%)) - Logic Levels: 0 - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.515ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.827 -2.515 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.201 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 1.093 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.081 17.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 17.090 - arrival time 0.107 - ------------------------------------------------------------------- - slack 17.198 - -Slack (MET) : 17.220ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.336ns (logic 1.317ns (56.385%) route 1.019ns (43.615%)) - Logic Levels: 0 - Clock Path Skew: -0.205ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.203 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 1.019 -0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.043 17.036 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 17.036 - arrival time 0.184 - ------------------------------------------------------------------- - slack 17.220 - -Slack (MET) : 17.264ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.241ns (logic 1.314ns (58.629%) route 0.927ns (41.371%)) - Logic Levels: 0 - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.927 -0.279 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.093 16.984 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 16.984 - arrival time 0.279 - ------------------------------------------------------------------- - slack 17.264 - -Slack (MET) : 17.264ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.063ns (logic 1.336ns (64.747%) route 0.727ns (35.253%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.184 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.727 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.269 16.808 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 16.808 - arrival time 0.456 - ------------------------------------------------------------------- - slack 17.264 - -Slack (MET) : 17.267ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.053ns (logic 1.336ns (65.060%) route 0.717ns (34.940%)) - Logic Levels: 0 - Clock Path Skew: -0.218ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK - SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.717 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X28Y72 FDRE (Setup_fdre_C_D) -0.265 16.907 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 16.907 - arrival time 0.360 - ------------------------------------------------------------------- - slack 17.267 - -Slack (MET) : 17.269ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.055ns (logic 1.336ns (65.010%) route 0.719ns (34.990%)) - Logic Levels: 0 - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.719 -0.466 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.274 16.803 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 16.803 - arrival time 0.466 - ------------------------------------------------------------------- - slack 17.269 - -Slack (MET) : 17.276ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.013ns (logic 1.343ns (66.730%) route 0.670ns (33.270%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.071 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.670 -0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.305 16.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 16.875 - arrival time 0.401 - ------------------------------------------------------------------- - slack 17.276 - -Slack (MET) : 17.295ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.030ns (logic 0.419ns (20.636%) route 1.611ns (79.364%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.419 -1.981 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 1.611 -0.369 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.265 16.926 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 16.926 - arrival time 0.369 - ------------------------------------------------------------------- - slack 17.295 - -Slack (MET) : 17.298ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.211ns (logic 1.309ns (59.215%) route 0.902ns (40.785%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.214 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.902 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.093 16.986 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 16.986 - arrival time 0.312 - ------------------------------------------------------------------- - slack 17.298 - -Slack (MET) : 17.298ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.200ns (logic 0.456ns (20.732%) route 1.744ns (79.268%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) - Source Clock Delay (SCD): -2.416ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.926 -2.416 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.456 -1.960 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 1.744 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.372 - clock uncertainty -0.197 17.175 - SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.093 17.082 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.082 - arrival time 0.216 - ------------------------------------------------------------------- - slack 17.298 - -Slack (MET) : 17.351ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.004ns (logic 0.419ns (20.911%) route 1.585ns (79.089%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.030ns = ( 17.970 - 20.000 ) - Source Clock Delay (SCD): -2.419ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.923 -2.419 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.419 -2.000 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 1.585 -0.415 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.798 17.970 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.369 - clock uncertainty -0.197 17.172 - SLICE_X26Y73 FDCE (Setup_fdce_C_D) -0.236 16.936 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 16.936 - arrival time 0.415 - ------------------------------------------------------------------- - slack 17.351 - -Slack (MET) : 17.368ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.159ns (logic 1.309ns (60.638%) route 0.850ns (39.362%)) - Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.031ns = ( 17.969 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.850 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.797 17.969 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C - clock pessimism -0.601 17.368 - clock uncertainty -0.197 17.171 - SLICE_X29Y76 FDRE (Setup_fdre_C_D) -0.058 17.113 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time 17.113 - arrival time 0.255 - ------------------------------------------------------------------- - slack 17.368 - -Slack (MET) : 17.377ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 1.652 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X15Y87 FDCE (Setup_fdce_C_D) -0.105 17.086 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.086 - arrival time 0.291 - ------------------------------------------------------------------- - slack 17.377 - -Slack (MET) : 17.380ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.944ns (logic 0.419ns (21.557%) route 1.525ns (78.443%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 17.891 - 20.000 ) - Source Clock Delay (SCD): -2.501ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.841 -2.501 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.419 -2.082 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 1.525 -0.557 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.719 17.891 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.290 - clock uncertainty -0.197 17.093 - SLICE_X114Y76 FDCE (Setup_fdce_C_D) -0.270 16.823 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 16.823 - arrival time 0.557 - ------------------------------------------------------------------- - slack 17.380 - -Slack (MET) : 17.388ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.108ns (logic 0.456ns (21.629%) route 1.652ns (78.371%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.027ns = ( 17.973 - 20.000 ) - Source Clock Delay (SCD): -2.417ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.925 -2.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.456 -1.961 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 1.652 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.801 17.973 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.372 - clock uncertainty -0.197 17.175 - SLICE_X27Y78 FDCE (Setup_fdce_C_D) -0.095 17.080 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.080 - arrival time 0.308 - ------------------------------------------------------------------- - slack 17.388 - -Slack (MET) : 17.399ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.106ns (logic 0.518ns (24.592%) route 1.588ns (75.408%)) - Logic Levels: 0 - Clock Path Skew: -0.203ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.096ns = ( 17.904 - 20.000 ) - Source Clock Delay (SCD): -2.495ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.847 -2.495 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.518 -1.977 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q - net (fo=2, routed) 1.588 -0.388 u_fft_mlkem_axi_slave/mlkem_intr_m - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.732 17.904 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - clock pessimism -0.601 17.303 - clock uncertainty -0.197 17.106 - SLICE_X117Y61 FDCE (Setup_fdce_C_D) -0.095 17.011 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] - ------------------------------------------------------------------- - required time 17.011 - arrival time 0.388 - ------------------------------------------------------------------- - slack 17.399 - -Slack (MET) : 17.403ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.095ns (logic 0.456ns (21.761%) route 1.639ns (78.239%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.425ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.917 -2.425 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.969 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 1.639 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X30Y74 FDCE (Setup_fdce_C_D) -0.095 17.074 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.074 - arrival time 0.329 - ------------------------------------------------------------------- - slack 17.403 - -Slack (MET) : 17.408ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.088ns (logic 0.456ns (21.835%) route 1.632ns (78.165%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 1.632 -0.311 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.601 17.389 - clock uncertainty -0.197 17.192 - SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.095 17.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 17.097 - arrival time 0.311 - ------------------------------------------------------------------- - slack 17.408 - -Slack (MET) : 17.411ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.087ns (logic 0.456ns (21.845%) route 1.631ns (78.155%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns = ( 17.990 - 20.000 ) - Source Clock Delay (SCD): -2.400ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.942 -2.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.456 -1.944 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 1.631 -0.312 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 17.990 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.601 17.389 - clock uncertainty -0.197 17.192 - SLICE_X15Y88 FDCE (Setup_fdce_C_D) -0.093 17.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 17.099 - arrival time 0.312 - ------------------------------------------------------------------- - slack 17.411 - -Slack (MET) : 17.415ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.084ns (logic 0.456ns (21.879%) route 1.628ns (78.121%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.033ns = ( 17.967 - 20.000 ) - Source Clock Delay (SCD): -2.423ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.919 -2.423 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.456 -1.967 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 1.628 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.795 17.967 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.601 17.366 - clock uncertainty -0.197 17.169 - SLICE_X29Y74 FDCE (Setup_fdce_C_D) -0.093 17.076 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 17.076 - arrival time 0.338 - ------------------------------------------------------------------- - slack 17.415 - -Slack (MET) : 17.422ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.877ns (logic 1.344ns (71.587%) route 0.533ns (28.413%)) - Logic Levels: 0 - Clock Path Skew: -0.207ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.520ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.822 -2.520 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.533 -0.642 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X61Y77 FDRE (Setup_fdre_C_D) -0.297 16.780 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 16.780 - arrival time 0.642 - ------------------------------------------------------------------- - slack 17.422 - -Slack (MET) : 17.426ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.860ns (logic 1.343ns (72.194%) route 0.517ns (27.806%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.343 -1.066 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.517 -0.548 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.305 16.878 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 16.878 - arrival time 0.548 - ------------------------------------------------------------------- - slack 17.426 - -Slack (MET) : 17.461ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.860ns (logic 1.344ns (72.269%) route 0.516ns (27.731%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.065 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O - net (fo=1, routed) 0.516 -0.549 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X17Y78 FDRE (Setup_fdre_C_D) -0.271 16.912 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 16.912 - arrival time 0.549 - ------------------------------------------------------------------- - slack 17.461 - -Slack (MET) : 17.463ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.069ns (logic 1.317ns (63.642%) route 0.752ns (36.358%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.521ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.821 -2.521 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.204 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.752 -0.451 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.067 17.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 17.012 - arrival time 0.451 - ------------------------------------------------------------------- - slack 17.463 - -Slack (MET) : 17.464ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.079ns (logic 1.317ns (63.334%) route 0.762ns (36.666%)) - Logic Levels: 0 - Clock Path Skew: -0.202ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.123ns = ( 17.877 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.317 -1.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.762 -0.443 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 17.877 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C - clock pessimism -0.601 17.276 - clock uncertainty -0.197 17.079 - SLICE_X57Y78 FDRE (Setup_fdre_C_D) -0.058 17.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 17.021 - arrival time 0.443 - ------------------------------------------------------------------- - slack 17.464 - -Slack (MET) : 17.494ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.834ns (logic 1.336ns (72.831%) route 0.498ns (27.169%)) - Logic Levels: 0 - Clock Path Skew: -0.210ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.022ns = ( 17.978 - 20.000 ) - Source Clock Delay (SCD): -2.414ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.928 -2.414 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.336 -1.078 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.498 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 17.978 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C - clock pessimism -0.601 17.377 - clock uncertainty -0.197 17.180 - SLICE_X19Y76 FDRE (Setup_fdre_C_D) -0.265 16.915 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 16.915 - arrival time 0.579 - ------------------------------------------------------------------- - slack 17.494 - -Slack (MET) : 17.513ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 2.042ns (logic 1.314ns (64.342%) route 0.728ns (35.658%)) - Logic Levels: 0 - Clock Path Skew: -0.204ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.125ns = ( 17.875 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.314 -1.209 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.728 -0.480 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.703 17.875 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C - clock pessimism -0.601 17.274 - clock uncertainty -0.197 17.077 - SLICE_X62Y81 FDRE (Setup_fdre_C_D) -0.045 17.032 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 17.032 - arrival time 0.480 - ------------------------------------------------------------------- - slack 17.513 - -Slack (MET) : 17.526ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.999ns (logic 1.309ns (65.487%) route 0.690ns (34.513%)) - Logic Levels: 0 - Clock Path Skew: -0.212ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.019ns = ( 17.981 - 20.000 ) - Source Clock Delay (SCD): -2.409ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.933 -2.409 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 1.309 -1.100 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.690 -0.410 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.809 17.981 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C - clock pessimism -0.601 17.380 - clock uncertainty -0.197 17.183 - SLICE_X15Y78 FDRE (Setup_fdre_C_D) -0.067 17.116 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time 17.116 - arrival time 0.410 - ------------------------------------------------------------------- - slack 17.526 - -Slack (MET) : 17.534ns (required time - arrival time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Setup (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.826ns (logic 1.344ns (73.607%) route 0.482ns (26.393%)) - Logic Levels: 0 - Clock Path Skew: -0.209ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.130ns = ( 17.870 - 20.000 ) - Source Clock Delay (SCD): -2.523ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.819 -2.523 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.344 -1.179 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.482 -0.697 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.698 17.870 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C - clock pessimism -0.601 17.269 - clock uncertainty -0.197 17.072 - SLICE_X62Y76 FDRE (Setup_fdre_C_D) -0.235 16.837 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 16.837 - arrival time 0.697 - ------------------------------------------------------------------- - slack 17.534 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: cpu_clk - To Clock: cpu_clk - -Setup : 0 Failing Endpoints, Worst Slack 25.793ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.793ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X15Y69 FDCE (Recov_fdce_C_CLR) -0.405 27.327 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.327 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.793 - -Slack (MET) : 25.837ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 27.371 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.837 - -Slack (MET) : 25.837ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.361 27.371 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 27.371 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.837 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.879ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.662ns (logic 0.580ns (15.838%) route 3.082ns (84.162%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.388ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.018ns = ( 28.304 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.424 1.534 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 28.304 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.498 27.806 - clock uncertainty -0.074 27.732 - SLICE_X14Y69 FDCE (Recov_fdce_C_CLR) -0.319 27.413 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 27.413 - arrival time -1.534 - ------------------------------------------------------------------- - slack 25.879 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.990ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.361 27.372 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.372 - arrival time -1.382 - ------------------------------------------------------------------- - slack 25.990 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 25.995ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.465ns (logic 0.580ns (16.740%) route 2.885ns (83.260%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.384ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.014ns = ( 28.308 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.227 1.336 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 28.308 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.498 27.810 - clock uncertainty -0.074 27.736 - SLICE_X17Y66 FDCE (Recov_fdce_C_CLR) -0.405 27.331 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 27.331 - arrival time -1.336 - ------------------------------------------------------------------- - slack 25.995 - -Slack (MET) : 26.032ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 - ------------------------------------------------------------------- - slack 26.032 - -Slack (MET) : 26.032ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 - ------------------------------------------------------------------- - slack 26.032 - -Slack (MET) : 26.032ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.511ns (logic 0.580ns (16.520%) route 2.931ns (83.480%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.387ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns = ( 28.305 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 2.273 1.382 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 28.305 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.498 27.807 - clock uncertainty -0.074 27.733 - SLICE_X14Y68 FDCE (Recov_fdce_C_CLR) -0.319 27.414 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 27.414 - arrival time -1.382 - ------------------------------------------------------------------- - slack 26.032 - -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 - ------------------------------------------------------------------- - slack 26.072 - -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 - ------------------------------------------------------------------- - slack 26.072 - -Slack (MET) : 26.072ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.804ns (logic 0.718ns (18.873%) route 3.086ns (81.127%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.455 1.401 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X4Y76 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/cpu_clk - SLICE_X4Y76 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[3]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X4Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.401 - ------------------------------------------------------------------- - slack 26.072 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.076ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.800ns (logic 0.718ns (18.894%) route 3.082ns (81.106%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.944ns = ( 28.378 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.450 1.396 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y76 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.884 28.378 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.426 27.952 - clock uncertainty -0.074 27.878 - SLICE_X5Y76 FDCE (Recov_fdce_C_CLR) -0.405 27.473 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.473 - arrival time -1.396 - ------------------------------------------------------------------- - slack 26.076 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.198ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.676ns (logic 0.718ns (19.530%) route 2.958ns (80.470%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.327 1.273 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X5Y74 FDCE f u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y74 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.273 - ------------------------------------------------------------------- - slack 26.198 - -Slack (MET) : 26.255ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.216 - ------------------------------------------------------------------- - slack 26.255 - -Slack (MET) : 26.255ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.620ns (logic 0.718ns (19.836%) route 2.902ns (80.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 2.270 1.216 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_1 - SLICE_X5Y75 FDCE f u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X5Y75 FDCE (Recov_fdce_C_CLR) -0.405 27.471 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 27.471 - arrival time -1.216 - ------------------------------------------------------------------- - slack 26.255 - -Slack (MET) : 26.639ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 3.322ns (logic 0.718ns (21.614%) route 2.604ns (78.386%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.946ns = ( 28.376 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.972 0.918 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 28.376 u_Axi_CDC/rFifo/cpu_clk - SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.426 27.950 - clock uncertainty -0.074 27.876 - SLICE_X6Y74 FDCE (Recov_fdce_C_CLR) -0.319 27.557 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 27.557 - arrival time -0.918 - ------------------------------------------------------------------- - slack 26.639 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.242ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.570ns (logic 0.718ns (27.941%) route 1.852ns (72.059%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.032ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns = ( 28.313 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.220 0.166 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 28.313 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.426 27.887 - clock uncertainty -0.074 27.813 - SLICE_X19Y59 FDCE (Recov_fdce_C_CLR) -0.405 27.408 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 27.408 - arrival time -0.166 - ------------------------------------------------------------------- - slack 27.242 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.248ns (required time - arrival time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.564ns (logic 0.718ns (27.999%) route 1.846ns (72.001%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.008ns = ( 28.314 - 30.323 ) - Source Clock Delay (SCD): -2.404ns - Clock Pessimism Removal (CPR): -0.426ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.938 -2.404 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.419 -1.985 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.632 -1.353 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.299 -1.054 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 1.215 0.161 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 28.314 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.426 27.888 - clock uncertainty -0.074 27.814 - SLICE_X17Y58 FDCE (Recov_fdce_C_CLR) -0.405 27.409 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 27.409 - arrival time -0.161 - ------------------------------------------------------------------- - slack 27.248 - -Slack (MET) : 27.338ns (required time - arrival time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 30.323ns (cpu_clk rise@30.323ns - cpu_clk rise@0.000ns) - Data Path Delay: 2.252ns (logic 0.580ns (25.756%) route 1.672ns (74.244%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.298ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.928ns = ( 28.394 - 30.323 ) - Source Clock Delay (SCD): -2.129ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.074ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.456 -1.673 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.658 -1.015 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.124 -0.891 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.014 0.123 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 30.323 30.323 r - K21 0.000 30.323 r clk (IN) - net (fo=0) 0.000 30.323 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 31.715 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 32.896 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 24.648 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 26.403 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 26.494 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.900 28.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.498 27.896 - clock uncertainty -0.074 27.822 - SLICE_X6Y50 FDCE (Recov_fdce_C_CLR) -0.361 27.461 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 27.461 - arrival time -0.123 - ------------------------------------------------------------------- - slack 27.338 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 23.497ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 23.497ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1324] - ------------------------------------------------------------------- - required time 36.621 - arrival time -13.124 - ------------------------------------------------------------------- - slack 23.497 - -Slack (MET) : 23.497ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.612ns (logic 0.609ns (3.901%) route 15.003ns (96.099%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.752 13.124 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X41Y101 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X41Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X41Y101 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[931] - ------------------------------------------------------------------- - required time 36.621 - arrival time -13.124 - ------------------------------------------------------------------- - slack 23.497 - -Slack (MET) : 23.954ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.155ns (logic 0.609ns (4.018%) route 14.546ns (95.982%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.206ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.188ns = ( 37.812 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.295 12.667 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X38Y100 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.640 37.812 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X38Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293]/C - clock pessimism -0.507 37.305 - clock uncertainty -0.077 37.229 - SLICE_X38Y100 FDCE (Recov_fdce_C_CLR) -0.608 36.621 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1293] - ------------------------------------------------------------------- - required time 36.621 - arrival time -12.667 - ------------------------------------------------------------------- - slack 23.954 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1365] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1461] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1542] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[732] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[805] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.240ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X37Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X37Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X37Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.796 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[893] - ------------------------------------------------------------------- - required time 36.796 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.240 - -Slack (MET) : 24.267ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[729] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.442 - ------------------------------------------------------------------- - slack 24.267 - -Slack (MET) : 24.267ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.931ns (logic 0.609ns (4.079%) route 14.322ns (95.921%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.071 12.442 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X45Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X45Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X45Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[730] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.442 - ------------------------------------------------------------------- - slack 24.267 - -Slack (MET) : 24.272ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1553] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.272 - -Slack (MET) : 24.272ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X49Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X49Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X49Y97 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1598] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.272 - -Slack (MET) : 24.284ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.564 36.840 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1269] - ------------------------------------------------------------------- - required time 36.840 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.284 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[652] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[715] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.316ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.564 36.753 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[718] - ------------------------------------------------------------------- - required time 36.753 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.316 - -Slack (MET) : 24.326ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 15.044ns (logic 0.609ns (4.048%) route 14.435ns (95.952%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.031ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.021ns = ( 37.979 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.185 12.556 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X36Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.807 37.979 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X36Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268]/C - clock pessimism -0.498 37.480 - clock uncertainty -0.077 37.404 - SLICE_X36Y99 FDCE (Recov_fdce_C_CLR) -0.522 36.882 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1268] - ------------------------------------------------------------------- - required time 36.882 - arrival time -12.556 - ------------------------------------------------------------------- - slack 24.326 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1372] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1373] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1396] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[864] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[886] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.341ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.856ns (logic 0.609ns (4.099%) route 14.247ns (95.901%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.996 12.367 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X47Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X47Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X47Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.709 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[887] - ------------------------------------------------------------------- - required time 36.709 - arrival time -12.367 - ------------------------------------------------------------------- - slack 24.341 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1301] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1525] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.358ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.926ns (logic 0.609ns (4.080%) route 14.317ns (95.920%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.118ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.108ns = ( 37.892 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 13.066 12.437 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X48Y97 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.720 37.892 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X48Y97 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557]/C - clock pessimism -0.498 37.393 - clock uncertainty -0.077 37.317 - SLICE_X48Y97 FDCE (Recov_fdce_C_CLR) -0.522 36.795 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1557] - ------------------------------------------------------------------- - required time 36.795 - arrival time -12.437 - ------------------------------------------------------------------- - slack 24.358 - -Slack (MET) : 24.441ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[650] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.441 - -Slack (MET) : 24.441ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X41Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X41Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X41Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[651] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.441 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1181] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1196] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.527ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.840ns (logic 0.609ns (4.104%) route 14.231ns (95.896%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.980 12.352 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X40Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X40Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X40Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.879 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1197] - ------------------------------------------------------------------- - required time 36.879 - arrival time -12.352 - ------------------------------------------------------------------- - slack 24.527 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1176] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1517] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1570] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.542ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X45Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X45Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X45Y95 FDCE (Recov_fdce_C_CLR) -0.608 36.708 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[730] - ------------------------------------------------------------------- - required time 36.708 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.542 - -Slack (MET) : 24.578ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1540] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.216 - ------------------------------------------------------------------- - slack 24.578 - -Slack (MET) : 24.578ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.705ns (logic 0.609ns (4.142%) route 14.096ns (95.858%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.845 12.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X38Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X38Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X38Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[733] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.216 - ------------------------------------------------------------------- - slack 24.578 - -Slack (MET) : 24.582ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1053] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.212 - ------------------------------------------------------------------- - slack 24.582 - -Slack (MET) : 24.582ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.700ns (logic 0.609ns (4.143%) route 14.091ns (95.857%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.033ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.023ns = ( 37.977 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.840 12.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1405]_0 - SLICE_X39Y99 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.805 37.977 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X39Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188]/C - clock pessimism -0.498 37.478 - clock uncertainty -0.077 37.402 - SLICE_X39Y99 FDCE (Recov_fdce_C_CLR) -0.608 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[1188] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.212 - ------------------------------------------------------------------- - slack 24.582 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1517] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1532] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.628ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.655ns (logic 0.609ns (4.156%) route 14.046ns (95.844%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.119ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.109ns = ( 37.891 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.795 12.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X44Y95 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.719 37.891 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X44Y95 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533]/C - clock pessimism -0.498 37.392 - clock uncertainty -0.077 37.316 - SLICE_X44Y95 FDCE (Recov_fdce_C_CLR) -0.522 36.794 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1533] - ------------------------------------------------------------------- - required time 36.794 - arrival time -12.166 - ------------------------------------------------------------------- - slack 24.628 - -Slack (MET) : 24.654ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.628ns (logic 0.609ns (4.163%) route 14.019ns (95.837%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.768 12.139 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X38Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X38Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X38Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1373] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.139 - ------------------------------------------------------------------- - slack 24.654 - -Slack (MET) : 24.658ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.624ns (logic 0.609ns (4.165%) route 14.015ns (95.835%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.024ns = ( 37.976 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.764 12.135 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/coeff_cnt_reg[1]_0 - SLICE_X39Y94 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.804 37.976 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/mlkem_clk - SLICE_X39Y94 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156]/C - clock pessimism -0.498 37.477 - clock uncertainty -0.077 37.401 - SLICE_X39Y94 FDCE (Recov_fdce_C_CLR) -0.608 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_cbd/keccak_state_r_reg[1156] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.135 - ------------------------------------------------------------------- - slack 24.658 - -Slack (MET) : 24.680ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533]/C - clock pessimism -0.498 37.391 - clock uncertainty -0.077 37.315 - SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.564 36.751 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1533] - ------------------------------------------------------------------- - required time 36.751 - arrival time -12.071 - ------------------------------------------------------------------- - slack 24.680 - -Slack (MET) : 24.722ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.559ns (logic 0.609ns (4.183%) route 13.950ns (95.817%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.120ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.110ns = ( 37.890 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.699 12.071 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X44Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.718 37.890 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X44Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532]/C - clock pessimism -0.498 37.391 - clock uncertainty -0.077 37.315 - SLICE_X44Y92 FDCE (Recov_fdce_C_CLR) -0.522 36.793 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1532] - ------------------------------------------------------------------- - required time 36.793 - arrival time -12.071 - ------------------------------------------------------------------- - slack 24.722 - -Slack (MET) : 25.212ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1204] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.580 - ------------------------------------------------------------------- - slack 25.212 - -Slack (MET) : 25.212ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.068ns (logic 0.609ns (4.329%) route 13.459ns (95.671%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.208 11.580 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/FSM_onehot_state_r_reg[0]_0 - SLICE_X38Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X38Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X38Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mb_state_r_reg[1205] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.580 - ------------------------------------------------------------------- - slack 25.212 - -Slack (MET) : 25.217ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 40.000ns (mlkem_clk_clk_pll rise@40.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 14.064ns (logic 0.609ns (4.330%) route 13.455ns (95.670%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.035ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.025ns = ( 37.975 - 40.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.498ns - Clock Uncertainty: 0.077ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 1.251 -0.782 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/valid_sr_reg[6][0] - SLICE_X114Y70 LUT5 (Prop_lut5_I0_O) 0.153 -0.629 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/p_s1[23]_i_9/O - net (fo=24598, routed) 12.204 11.575 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[584]_0 - SLICE_X39Y92 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.803 37.975 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X39Y92 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204]/C - clock pessimism -0.498 37.476 - clock uncertainty -0.077 37.400 - SLICE_X39Y92 FDCE (Recov_fdce_C_CLR) -0.608 36.792 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[1204] - ------------------------------------------------------------------- - required time 36.792 - arrival time -11.575 - ------------------------------------------------------------------- - slack 25.217 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : 0 Failing Endpoints, Worst Slack 9.156ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 9.156ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.215ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C - clock pessimism -0.601 37.298 - clock uncertainty -0.197 37.101 - SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[0] - ------------------------------------------------------------------- - required time 36.492 - arrival time -27.336 - ------------------------------------------------------------------- - slack 9.156 - -Slack (MET) : 9.156ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 9.823ns (logic 0.606ns (6.169%) route 9.217ns (93.831%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.215ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.101ns = ( 37.899 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.710 27.336 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.727 37.899 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - clock pessimism -0.601 37.298 - clock uncertainty -0.197 37.101 - SLICE_X118Y67 FDCE (Recov_fdce_C_CLR) -0.609 36.492 pll_clk.u_rst_mlkem/delay_reg[1] - ------------------------------------------------------------------- - required time 36.492 - arrival time -27.336 - ------------------------------------------------------------------- - slack 9.156 - -Slack (MET) : 11.865ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - clock pessimism -0.601 37.373 - clock uncertainty -0.197 37.176 - SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 36.567 - arrival time -24.702 - ------------------------------------------------------------------- - slack 11.865 - -Slack (MET) : 11.865ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (mlkem_clk_clk_pll rise@40.000ns - sys_clk rise@20.000ns) - Data Path Delay: 7.189ns (logic 0.606ns (8.429%) route 6.583ns (91.571%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.140ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.026ns = ( 37.974 - 40.000 ) - Source Clock Delay (SCD): -2.488ns = ( 17.512 - 20.000 ) - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 21.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 22.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 13.725 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 15.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 15.658 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 17.512 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 17.968 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 21.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 21.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 3.076 24.702 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 40.000 40.000 r - K21 0.000 40.000 r clk (IN) - net (fo=0) 0.000 40.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 41.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 42.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.248 34.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.755 36.081 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 36.172 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.802 37.974 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.601 37.373 - clock uncertainty -0.197 37.176 - SLICE_X25Y79 FDCE (Recov_fdce_C_CLR) -0.609 36.567 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 36.567 - arrival time -24.702 - ------------------------------------------------------------------- - slack 11.865 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 11.249ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 11.249ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.124ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 16.786 - arrival time -5.537 - ------------------------------------------------------------------- - slack 11.249 - -Slack (MET) : 11.249ns (required time - arrival time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 8.025ns (logic 0.580ns (7.227%) route 7.445ns (92.773%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.124ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns = ( 17.989 - 20.000 ) - Source Clock Delay (SCD): -2.489ns - Clock Pessimism Removal (CPR): -0.601ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 1.853 -2.489 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.456 -2.033 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.874 -1.158 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.124 -1.034 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 6.571 5.537 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 17.989 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.601 17.388 - clock uncertainty -0.197 17.191 - SLICE_X13Y87 FDCE (Recov_fdce_C_CLR) -0.405 16.786 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 16.786 - arrival time -5.537 - ------------------------------------------------------------------- - slack 11.249 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: sys_clk - -Setup : 0 Failing Endpoints, Worst Slack 4.581ns, Total Violation 0.000ns -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA ---------------------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 4.581ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.588ns (logic 0.606ns (4.154%) route 13.982ns (95.846%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.151ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.132ns = ( 17.868 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 10.475 12.101 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X85Y50 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.696 17.868 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X85Y50 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2]/C - clock pessimism -0.507 17.361 - clock uncertainty -0.071 17.290 - SLICE_X85Y50 FDCE (Recov_fdce_C_CLR) -0.609 16.681 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[2] - ------------------------------------------------------------------- - required time 16.681 - arrival time -12.101 - ------------------------------------------------------------------- - slack 4.581 - -Slack (MET) : 5.171ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 14.003ns (logic 0.606ns (4.328%) route 13.397ns (95.672%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.127ns = ( 17.873 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.890 11.515 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X77Y52 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.701 17.873 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X77Y52 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0]/C - clock pessimism -0.507 17.366 - clock uncertainty -0.071 17.295 - SLICE_X77Y52 FDCE (Recov_fdce_C_CLR) -0.609 16.686 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[0] - ------------------------------------------------------------------- - required time 16.686 - arrival time -11.515 - ------------------------------------------------------------------- - slack 5.171 - -Slack (MET) : 5.624ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.646ns (logic 0.606ns (4.441%) route 13.040ns (95.559%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 9.533 11.158 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X90Y57 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X90Y57 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X90Y57 FDCE (Recov_fdce_C_CLR) -0.523 16.782 u_snix_axil_cdma_mux_8ch/u_core_engine/next_size_reg[2] - ------------------------------------------------------------------- - required time 16.782 - arrival time -11.158 - ------------------------------------------------------------------- - slack 5.624 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.450ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 13.011ns (logic 0.606ns (4.657%) route 12.405ns (95.343%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.840ns = ( 18.160 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.898 10.524 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X29Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.989 18.160 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X29Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C - clock pessimism -0.507 17.654 - clock uncertainty -0.071 17.583 - SLICE_X29Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.974 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4] - ------------------------------------------------------------------- - required time 16.974 - arrival time -10.524 - ------------------------------------------------------------------- - slack 6.450 - -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[12] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 - ------------------------------------------------------------------- - slack 6.650 - -Slack (MET) : 6.650ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.535ns (logic 0.606ns (4.834%) route 11.929ns (95.166%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.422 10.047 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X50Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X50Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X50Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/pending_bytes_reg[2] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.047 - ------------------------------------------------------------------- - slack 6.650 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[12] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[13] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[14] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.654ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.531ns (logic 0.606ns (4.836%) route 11.925ns (95.164%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.418 10.043 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X51Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[15] - ------------------------------------------------------------------- - required time 16.697 - arrival time -10.043 - ------------------------------------------------------------------- - slack 6.654 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[11] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[12] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[19] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.814ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.372ns (logic 0.606ns (4.898%) route 11.766ns (95.102%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.259 9.884 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[1] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.884 - ------------------------------------------------------------------- - slack 6.814 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[5] - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.881ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X19Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X19Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X19Y0 FDCE (Recov_fdce_C_CLR) -0.609 16.983 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_sp_en_reg - ------------------------------------------------------------------- - required time 16.983 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.881 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[4] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.947ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.239ns (logic 0.606ns (4.951%) route 11.633ns (95.049%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.126 9.751 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y63 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y63 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y63 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.751 - ------------------------------------------------------------------- - slack 6.947 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[14] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[15] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[5] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[6] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[7] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.955ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.231ns (logic 0.606ns (4.955%) route 11.625ns (95.045%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.118 9.743 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X53Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.743 - ------------------------------------------------------------------- - slack 6.955 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[7] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[8] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.967ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.589ns (logic 0.606ns (4.814%) route 11.983ns (95.186%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.476 10.102 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y0 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y0 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y0 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[9] - ------------------------------------------------------------------- - required time 17.069 - arrival time -10.102 - ------------------------------------------------------------------- - slack 6.967 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[0] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[10] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[3] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[4] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 6.996ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.189ns (logic 0.606ns (4.972%) route 11.583ns (95.028%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.076 9.702 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X55Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[9] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.702 - ------------------------------------------------------------------- - slack 6.996 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[10] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[11] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[8] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.098ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.088ns (logic 0.606ns (5.013%) route 11.482ns (94.987%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.134ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.115ns = ( 17.885 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.975 9.601 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y64 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 17.885 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y64 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9]/C - clock pessimism -0.507 17.378 - clock uncertainty -0.071 17.307 - SLICE_X51Y64 FDCE (Recov_fdce_C_CLR) -0.609 16.698 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[9] - ------------------------------------------------------------------- - required time 16.698 - arrival time -9.601 - ------------------------------------------------------------------- - slack 7.098 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[13] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[16] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[21] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[22] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.115ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.070ns (logic 0.606ns (5.021%) route 11.464ns (94.979%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.135ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.116ns = ( 17.884 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.957 9.583 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X53Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.712 17.884 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X53Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23]/C - clock pessimism -0.507 17.377 - clock uncertainty -0.071 17.306 - SLICE_X53Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.697 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[23] - ------------------------------------------------------------------- - required time 16.697 - arrival time -9.583 - ------------------------------------------------------------------- - slack 7.115 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[17] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.136ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.048ns (logic 0.606ns (5.030%) route 11.442ns (94.970%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.136ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.117ns = ( 17.883 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.935 9.561 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X55Y65 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.711 17.883 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X55Y65 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18]/C - clock pessimism -0.507 17.376 - clock uncertainty -0.071 17.305 - SLICE_X55Y65 FDCE (Recov_fdce_C_CLR) -0.609 16.696 u_snix_axil_cdma_mux_8ch/u_core_engine/transfer_len_reg[18] - ------------------------------------------------------------------- - required time 16.696 - arrival time -9.561 - ------------------------------------------------------------------- - slack 7.136 - -Slack (MET) : 7.143ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 12.414ns (logic 0.606ns (4.882%) route 11.808ns (95.118%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.150ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.831ns = ( 18.169 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 8.301 9.926 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/p_0_in - SLICE_X18Y1 FDCE f u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.998 18.169 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/sys_clk - SLICE_X18Y1 FDCE r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6]/C - clock pessimism -0.507 17.663 - clock uncertainty -0.071 17.592 - SLICE_X18Y1 FDCE (Recov_fdce_C_CLR) -0.523 17.069 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf2_count_reg[6] - ------------------------------------------------------------------- - required time 17.069 - arrival time -9.926 - ------------------------------------------------------------------- - slack 7.143 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0]/C - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[0] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - -Slack (MET) : 7.222ns (required time - arrival time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Recovery (Max at Slow Process Corner) - Requirement: 20.000ns (sys_clk rise@20.000ns - sys_clk rise@0.000ns) - Data Path Delay: 11.965ns (logic 0.606ns (5.065%) route 11.359ns (94.935%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.133ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.114ns = ( 17.886 - 20.000 ) - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): -0.507ns - Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 7.852 9.478 u_snix_axil_cdma_mux_8ch/u_core_engine/p_0_in - SLICE_X51Y62 FDCE f u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 20.000 20.000 r - K21 0.000 20.000 r clk (IN) - net (fo=0) 0.000 20.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 21.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 22.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 14.326 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 16.081 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 16.172 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.714 17.886 u_snix_axil_cdma_mux_8ch/u_core_engine/sys_clk - SLICE_X51Y62 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1]/C - clock pessimism -0.507 17.379 - clock uncertainty -0.071 17.308 - SLICE_X51Y62 FDCE (Recov_fdce_C_CLR) -0.609 16.699 u_snix_axil_cdma_mux_8ch/u_core_engine/copied_bytes_reg[1] - ------------------------------------------------------------------- - required time 16.699 - arrival time -9.478 - ------------------------------------------------------------------- - slack 7.222 - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: sys_clk - To Clock: cpu_clk - -Max Delay 59 Endpoints -Min Delay 0 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.470ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - -Slack: inf - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.445ns (logic 0.606ns (6.416%) route 8.839ns (93.584%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.470ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.332 6.958 u_Axi_CDC/bFifo/bufferCC_12/p_0_in_1 - SLICE_X30Y58 FDCE f u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - -Slack: inf - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_cpu/delay_reg[0]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.738ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 - SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[0]/C - -Slack: inf - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_cpu/delay_reg[1]/CLR - (recovery check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 9.183ns (logic 0.606ns (6.599%) route 8.577ns (93.401%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.738ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.750ns - Source Clock Delay (SCD): -2.488ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 3.507 1.475 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.150 1.625 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 5.070 6.696 pll_clk.u_rst_cpu/p_0_in_0 - SLICE_X0Y48 FDCE f pll_clk.u_rst_cpu/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - -Slack: inf - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[5]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 4.254ns (logic 0.419ns (9.850%) route 3.835ns (90.150%)) - Logic Levels: 0 - Clock Path Skew: 0.544ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.939ns - Source Clock Delay (SCD): -2.483ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.859 -2.483 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.419 -2.064 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/Q - net (fo=1, routed) 3.835 1.771 u_cpu/u_csr/interrupt[3] - SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.890 -1.939 u_cpu/u_csr/cpu_clk - SLICE_X50Y37 FDRE r u_cpu/u_csr/csr_estat_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.608ns (logic 0.595ns (37.010%) route 1.013ns (62.990%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 1.013 1.256 u_Axi_CDC/rFifo/_zz_ram_port10__2[19] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.565ns (logic 0.612ns (39.107%) route 0.953ns (60.893%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.953 1.215 u_Axi_CDC/rFifo/_zz_ram_port10__2[24] - SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.566ns (logic 0.612ns (39.088%) route 0.954ns (60.912%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.954 1.214 u_Axi_CDC/rFifo/_zz_ram_port10__2[18] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.491ns (logic 0.482ns (32.335%) route 1.009ns (67.665%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 1.009 1.138 u_Axi_CDC/rFifo/_zz_ram_port10__2[21] - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.465ns (logic 0.612ns (41.773%) route 0.853ns (58.227%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 0.853 1.113 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.455ns (logic 0.612ns (42.062%) route 0.843ns (57.938%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.262 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.843 1.105 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.417ns (logic 0.480ns (33.882%) route 0.937ns (66.118%)) - Logic Levels: 0 - Clock Path Skew: -0.145ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.127 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.937 1.063 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.406ns (logic 0.595ns (42.317%) route 0.811ns (57.683%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.811 1.056 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.401ns (logic 0.491ns (35.055%) route 0.910ns (64.945%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.910 1.050 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.394ns (logic 0.480ns (34.421%) route 0.914ns (65.579%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.914 1.044 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.361ns (logic 0.480ns (35.268%) route 0.881ns (64.732%)) - Logic Levels: 0 - Clock Path Skew: -0.145ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.497ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.881 1.009 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.354ns (logic 0.485ns (35.824%) route 0.869ns (64.176%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 0.869 1.004 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.323ns (logic 0.612ns (46.260%) route 0.711ns (53.740%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.711 0.970 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.317ns (logic 0.595ns (45.169%) route 0.722ns (54.831%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.245 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 0.722 0.967 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.310ns (logic 0.595ns (45.409%) route 0.715ns (54.591%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.243 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 0.715 0.958 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.304ns (logic 0.491ns (37.657%) route 0.813ns (62.343%)) - Logic Levels: 0 - Clock Path Skew: -0.148ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.498ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.141 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.813 0.954 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.765 -0.498 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.294ns (logic 0.612ns (47.295%) route 0.682ns (52.705%)) - Logic Levels: 0 - Clock Path Skew: -0.213ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.259 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 0.682 0.941 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.256ns (logic 0.482ns (38.384%) route 0.774ns (61.616%)) - Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.129 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.774 0.903 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.248ns (logic 0.595ns (47.682%) route 0.653ns (52.318%)) - Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 0.653 0.895 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.241ns (logic 0.491ns (39.556%) route 0.750ns (60.444%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.750 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.241ns (logic 0.485ns (39.089%) route 0.756ns (60.911%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.756 0.889 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.233ns (logic 0.482ns (39.088%) route 0.751ns (60.912%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.751 0.883 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.235ns (logic 0.491ns (39.769%) route 0.744ns (60.231%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.139 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 0.744 0.882 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.232ns (logic 0.595ns (48.288%) route 0.637ns (51.712%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.242 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.637 0.879 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.225ns (logic 0.482ns (39.361%) route 0.743ns (60.639%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 0.743 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.222ns (logic 0.482ns (39.449%) route 0.740ns (60.551%)) - Logic Levels: 0 - Clock Path Skew: -0.146ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.740 0.872 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.215ns (logic 0.480ns (39.516%) route 0.735ns (60.484%)) - Logic Levels: 0 - Clock Path Skew: -0.144ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.735 0.863 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.194ns (logic 0.480ns (40.215%) route 0.714ns (59.785%)) - Logic Levels: 0 - Clock Path Skew: -0.217ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.567ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.130 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.714 0.843 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C - -Slack: inf - Source: u_confreg/int_out_or_q2_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.180ns (logic 0.175ns (14.825%) route 1.005ns (85.175%)) - Logic Levels: 0 - Clock Path Skew: -0.172ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.509ns - Source Clock Delay (SCD): -0.337ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.971 -0.337 u_confreg/sys_clk - SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.175 -0.162 r u_confreg/int_out_or_q2_reg/Q - net (fo=1, routed) 1.005 0.843 u_cpu/u_csr/interrupt[0] - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.135ns (logic 0.491ns (43.278%) route 0.644ns (56.722%)) - Logic Levels: 0 - Clock Path Skew: -0.141ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.494ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.644 0.781 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.769 -0.494 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.130ns (logic 0.485ns (42.936%) route 0.645ns (57.064%)) - Logic Levels: 0 - Clock Path Skew: -0.143ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.496ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.645 0.776 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.122ns (logic 0.485ns (43.231%) route 0.637ns (56.769%)) - Logic Levels: 0 - Clock Path Skew: -0.216ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.135 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.637 0.772 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.111ns (logic 0.491ns (44.191%) route 0.620ns (55.809%)) - Logic Levels: 0 - Clock Path Skew: -0.214ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.567ns - Source Clock Delay (SCD): -0.353ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.138 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 0.620 0.758 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.695 -0.567 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.097ns (logic 0.485ns (44.212%) route 0.612ns (55.788%)) - Logic Levels: 0 - Clock Path Skew: -0.214ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.566ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 0.612 0.745 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.696 -0.566 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.089ns (logic 0.482ns (44.271%) route 0.607ns (55.729%)) - Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.569ns - Source Clock Delay (SCD): -0.350ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.958 -0.350 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.132 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 0.607 0.739 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.693 -0.569 u_Axi_CDC/rFifo/cpu_clk - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C - -Slack: inf - Source: u_matmul_axi_slave/done_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.975ns (logic 0.204ns (20.919%) route 0.771ns (79.081%)) - Logic Levels: 0 - Clock Path Skew: -0.115ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.508ns - Source Clock Delay (SCD): -0.393ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_matmul_axi_slave/sys_clk - SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.204 -0.189 r u_matmul_axi_slave/done_reg/Q - net (fo=12, routed) 0.771 0.582 u_cpu/u_csr/interrupt[2] - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.755 -0.508 u_cpu/u_csr/cpu_clk - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C - -Slack: inf - Source: u_cdma_matmul_bridge/seq_done_flag_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.752ns (logic 0.231ns (30.703%) route 0.521ns (69.297%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.223ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.610ns - Source Clock Delay (SCD): -0.387ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.921 -0.387 u_cdma_matmul_bridge/sys_clk - SLICE_X61Y63 FDRE r u_cdma_matmul_bridge/seq_done_flag_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X61Y63 FDRE (Prop_fdre_C_Q) 0.175 -0.212 r u_cdma_matmul_bridge/seq_done_flag_reg/Q - net (fo=3, routed) 0.521 0.309 u_snix_axil_cdma_mux_8ch/cdma_matmul_seq_irq - SLICE_X57Y58 LUT5 (Prop_lut5_I4_O) 0.056 0.365 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O - net (fo=1, routed) 0.000 0.365 u_cpu/u_csr/interrupt[1] - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.652 -0.610 u_cpu/u_csr/cpu_clk - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.576ns (logic 0.160ns (27.764%) route 0.416ns (72.236%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.160 -0.071 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.416 0.345 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.539 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.577ns (logic 0.175ns (30.321%) route 0.402ns (69.679%)) - Logic Levels: 0 - Clock Path Skew: -0.227ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.347ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.175 -0.172 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.402 0.230 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.688 -0.574 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.550ns (logic 0.160ns (29.072%) route 0.390ns (70.928%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.160 -0.186 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.390 0.204 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.549ns (logic 0.175ns (31.853%) route 0.374ns (68.147%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.374 0.203 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.482ns (logic 0.175ns (36.304%) route 0.307ns (63.696%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.346ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.962 -0.346 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.175 -0.171 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.307 0.136 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.363ns (logic 0.175ns (48.223%) route 0.188ns (51.777%)) - Logic Levels: 0 - Clock Path Skew: -0.234ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.465ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.188 0.132 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.446ns (logic 0.160ns (35.900%) route 0.286ns (64.100%)) - Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.553ns - Source Clock Delay (SCD): -0.321ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.987 -0.321 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.160 -0.161 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.286 0.125 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.316ns (logic 0.175ns (55.416%) route 0.141ns (44.584%)) - Logic Levels: 0 - Clock Path Skew: -0.234ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.465ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.175 -0.056 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.141 0.085 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: cpu_clk - To Clock: sys_clk - -Max Delay 162 Endpoints -Min Delay 0 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.565ns (logic 0.595ns (38.011%) route 0.970ns (61.989%)) - Logic Levels: 0 - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 0.970 1.333 u_Axi_CDC/wFifo/_zz_ram_port10__0[1] - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.442ns (logic 0.612ns (42.441%) route 0.830ns (57.559%)) - Logic Levels: 0 - Clock Path Skew: -0.317ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.548ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_36_36/WCLK - SLICE_X6Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_36_36/RAMA/O - net (fo=1, routed) 0.830 1.211 u_Axi_CDC/wFifo/_zz_ram_port10__0[36] - SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.714 -0.548 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y69 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[36]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.394ns (logic 0.485ns (34.784%) route 0.909ns (65.216%)) - Logic Levels: 0 - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.909 1.162 u_Axi_CDC/wFifo/_zz_ram_port10__0[16] - SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[16]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.251ns (logic 0.480ns (38.383%) route 0.771ns (61.617%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.771 1.021 u_Axi_CDC/wFifo/_zz_ram_port10__0[23] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Fast Process Corner) - Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.541ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - -Slack: inf - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Fast Process Corner) - Data Path Delay: 1.198ns (logic 0.231ns (19.278%) route 0.967ns (80.722%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: -0.312ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.541ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.175 -0.054 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.272 0.218 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.056 0.274 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.695 0.969 u_Axi_CDC/awFifo/bufferCC_12/p_0_in - SLICE_X7Y59 FDCE f u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.183ns (logic 0.485ns (41.003%) route 0.698ns (58.997%)) - Logic Levels: 0 - Clock Path Skew: -0.316ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.545ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.698 0.954 u_Axi_CDC/wFifo/_zz_ram_port10__0[22] - SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.717 -0.545 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y66 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.172ns (logic 0.595ns (50.766%) route 0.577ns (49.234%)) - Logic Levels: 0 - Clock Path Skew: -0.313ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.364 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.577 0.941 u_Axi_CDC/wFifo/_zz_ram_port10__0[31] - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y65 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.160ns (logic 0.485ns (41.821%) route 0.675ns (58.179%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 0.675 0.931 u_Axi_CDC/wFifo/_zz_ram_port10__0[10] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.146ns (logic 0.612ns (53.398%) route 0.534ns (46.602%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.381 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.534 0.915 u_Axi_CDC/wFifo/_zz_ram_port10__0[30] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[30]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.116ns (logic 0.595ns (53.305%) route 0.521ns (46.695%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.363 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 0.521 0.884 u_Axi_CDC/wFifo/_zz_ram_port10__0[13] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.107ns (logic 0.480ns (43.345%) route 0.627ns (56.655%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.251 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.627 0.878 u_Axi_CDC/wFifo/_zz_ram_port10__0[29] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[29]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.202ns (logic 0.612ns (50.922%) route 0.590ns (49.078%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.260 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMA/O - net (fo=1, routed) 0.590 0.850 u_Axi_CDC/arFifo/_zz_ram_port10__1[18] - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.188ns (logic 0.595ns (50.069%) route 0.593ns (49.931%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK - SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA_D1/O - net (fo=1, routed) 0.593 0.847 u_Axi_CDC/awFifo/_zz_ram_port10[19] - SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X22Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.021ns (logic 0.595ns (58.252%) route 0.426ns (41.748%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 0.426 0.792 u_Axi_CDC/wFifo/_zz_ram_port10__0[7] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.128ns (logic 0.480ns (42.561%) route 0.648ns (57.439%)) - Logic Levels: 0 - Clock Path Skew: -0.219ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.571ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.128 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC_D1/O - net (fo=1, routed) 0.648 0.776 u_Axi_CDC/arFifo/_zz_ram_port10__1[23] - SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk - SLICE_X14Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.005ns (logic 0.480ns (47.778%) route 0.525ns (52.222%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.249 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.525 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[35] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[35]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.002ns (logic 0.482ns (48.095%) route 0.520ns (51.905%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.520 0.773 u_Axi_CDC/wFifo/_zz_ram_port10__0[21] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.001ns (logic 0.480ns (47.953%) route 0.521ns (52.047%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.521 0.769 u_Axi_CDC/wFifo/_zz_ram_port10__0[17] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[17]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.109ns (logic 0.612ns (55.196%) route 0.497ns (44.804%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.340ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK - SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.272 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/O - net (fo=1, routed) 0.497 0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[24] - SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.116ns (logic 0.485ns (43.457%) route 0.631ns (56.543%)) - Logic Levels: 0 - Clock Path Skew: -0.224ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.133 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMC/O - net (fo=1, routed) 0.631 0.764 u_Axi_CDC/arFifo/_zz_ram_port10__1[22] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.987ns (logic 0.612ns (62.028%) route 0.375ns (37.972%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.375 0.757 u_Axi_CDC/wFifo/_zz_ram_port10__0[6] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.973ns (logic 0.612ns (62.874%) route 0.361ns (37.126%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 0.361 0.741 u_Axi_CDC/wFifo/_zz_ram_port10__0[12] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.966ns (logic 0.491ns (50.838%) route 0.475ns (49.162%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y46 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 0.475 0.734 u_Axi_CDC/wFifo/_zz_ram_port10__0[14] - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[14]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.960ns (logic 0.595ns (62.000%) route 0.365ns (38.000%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.365 0.730 u_Axi_CDC/wFifo/_zz_ram_port10__0[25] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.949ns (logic 0.485ns (51.100%) route 0.464ns (48.900%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.231ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.077 -0.231 u_Axi_CDC/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X6Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.254 r u_Axi_CDC/wFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.464 0.718 u_Axi_CDC/wFifo/_zz_ram_port10__0[34] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[34]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.047ns (logic 0.595ns (56.827%) route 0.452ns (43.173%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.571ns - Source Clock Delay (SCD): -0.340ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.968 -0.340 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/WCLK - SLICE_X20Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.255 r u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/O - net (fo=1, routed) 0.452 0.707 u_Axi_CDC/arFifo/_zz_ram_port10__1[25] - SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.928ns (logic 0.482ns (51.961%) route 0.446ns (48.039%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.536ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.446 0.698 u_Axi_CDC/wFifo/_zz_ram_port10__0[9] - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[9]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.040ns (logic 0.485ns (46.647%) route 0.555ns (53.353%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.345ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.140 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMC/O - net (fo=1, routed) 0.555 0.695 u_Axi_CDC/arFifo/_zz_ram_port10__1[46] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[46]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.920ns (logic 0.612ns (66.545%) route 0.308ns (33.455%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.539ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.380 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 0.308 0.687 u_Axi_CDC/wFifo/_zz_ram_port10__0[0] - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_Axi_CDC/wFifo/sys_clk - SLICE_X6Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.025ns (logic 0.612ns (59.711%) route 0.413ns (40.289%)) - Logic Levels: 0 - Clock Path Skew: -0.231ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.342ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.966 -0.342 u_Axi_CDC/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X22Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y60 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.270 r u_Axi_CDC/arFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.413 0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[12] - SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/arFifo/sys_clk - SLICE_X21Y63 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.021ns (logic 0.612ns (59.936%) route 0.409ns (40.064%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_18_23/WCLK - SLICE_X22Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y58 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_18_23/RAMA/O - net (fo=1, routed) 0.409 0.680 u_Axi_CDC/awFifo/_zz_ram_port10[18] - SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X22Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.026ns (logic 0.482ns (46.999%) route 0.544ns (53.001%)) - Logic Levels: 0 - Clock Path Skew: -0.222ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.352ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.956 -0.352 u_Axi_CDC/arFifo/ram_reg_0_3_18_23/WCLK - SLICE_X36Y63 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y63 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.130 r u_Axi_CDC/arFifo/ram_reg_0_3_18_23/RAMB_D1/O - net (fo=1, routed) 0.544 0.673 u_Axi_CDC/arFifo/_zz_ram_port10__1[21] - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/arFifo/sys_clk - SLICE_X22Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[21]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.019ns (logic 0.595ns (58.363%) route 0.424ns (41.637%)) - Logic Levels: 0 - Clock Path Skew: -0.228ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.576ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.247 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMA_D1/O - net (fo=1, routed) 0.424 0.671 u_Axi_CDC/awFifo/_zz_ram_port10[31] - SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y67 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.898ns (logic 0.612ns (68.152%) route 0.286ns (31.848%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.537ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.286 0.669 u_Axi_CDC/wFifo/_zz_ram_port10__0[18] - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[18]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.896ns (logic 0.595ns (66.419%) route 0.301ns (33.581%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y48 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.366 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.301 0.667 u_Axi_CDC/wFifo/_zz_ram_port10__0[19] - SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y57 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[19]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 1.012ns (logic 0.485ns (47.912%) route 0.527ns (52.088%)) - Logic Levels: 0 - Clock Path Skew: -0.264ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.612ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.137 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.527 0.664 u_Axi_CDC/arFifo/_zz_ram_port10__1[4] - SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.650 -0.612 u_Axi_CDC/arFifo/sys_clk - SLICE_X46Y64 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[4]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.892ns (logic 0.480ns (53.815%) route 0.412ns (46.185%)) - Logic Levels: 0 - Clock Path Skew: -0.306ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.480 0.248 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.412 0.660 u_Axi_CDC/wFifo/_zz_ram_port10__0[5] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.880ns (logic 0.612ns (69.559%) route 0.268ns (30.441%)) - Logic Levels: 0 - Clock Path Skew: -0.307ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.536ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.383 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.268 0.651 u_Axi_CDC/wFifo/_zz_ram_port10__0[24] - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y52 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.879ns (logic 0.482ns (54.834%) route 0.397ns (45.166%)) - Logic Levels: 0 - Clock Path Skew: -0.315ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.544ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.482 0.253 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.397 0.650 u_Axi_CDC/wFifo/_zz_ram_port10__0[27] - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y64 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.990ns (logic 0.612ns (61.797%) route 0.378ns (38.203%)) - Logic Levels: 0 - Clock Path Skew: -0.233ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.574ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_12_17/WCLK - SLICE_X22Y59 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.378 0.649 u_Axi_CDC/awFifo/_zz_ram_port10[12] - SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.688 -0.574 u_Axi_CDC/awFifo/sys_clk - SLICE_X24Y60 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.981ns (logic 0.612ns (62.415%) route 0.369ns (37.585%)) - Logic Levels: 0 - Clock Path Skew: -0.229ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.570ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_24_29/WCLK - SLICE_X22Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_24_29/RAMA/O - net (fo=1, routed) 0.369 0.639 u_Axi_CDC/awFifo/_zz_ram_port10[24] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[24]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.866ns (logic 0.485ns (56.026%) route 0.381ns (43.974%)) - Logic Levels: 0 - Clock Path Skew: -0.309ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.538ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y49 RAMD32 (Prop_ramd32_CLK_O) - 0.485 0.256 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.381 0.636 u_Axi_CDC/wFifo/_zz_ram_port10__0[28] - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.724 -0.538 u_Axi_CDC/wFifo/sys_clk - SLICE_X2Y58 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[28]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.867ns (logic 0.491ns (56.612%) route 0.376ns (43.388%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.540ns - Source Clock Delay (SCD): -0.232ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X6Y45 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.259 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 0.376 0.635 u_Axi_CDC/wFifo/_zz_ram_port10__0[2] - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.722 -0.540 u_Axi_CDC/wFifo/sys_clk - SLICE_X7Y56 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.955ns (logic 0.612ns (64.074%) route 0.343ns (35.926%)) - Logic Levels: 0 - Clock Path Skew: -0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.338ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.274 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 0.343 0.617 u_Axi_CDC/awFifo/_zz_ram_port10[6] - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.947ns (logic 0.595ns (62.805%) route 0.352ns (37.195%)) - Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.254 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA_D1/O - net (fo=1, routed) 0.352 0.606 u_Axi_CDC/awFifo/_zz_ram_port10[43] - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[43]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.953ns (logic 0.612ns (64.216%) route 0.341ns (35.784%)) - Logic Levels: 0 - Clock Path Skew: -0.229ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.577ns - Source Clock Delay (SCD): -0.348ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.264 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/O - net (fo=1, routed) 0.341 0.605 u_Axi_CDC/arFifo/_zz_ram_port10__1[0] - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/arFifo/sys_clk - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.833ns (logic 0.491ns (58.937%) route 0.342ns (41.063%)) - Logic Levels: 0 - Clock Path Skew: -0.308ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.537ns - Source Clock Delay (SCD): -0.229ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X2Y47 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X2Y47 RAMD32 (Prop_ramd32_CLK_O) - 0.491 0.262 r u_Axi_CDC/wFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.342 0.604 u_Axi_CDC/wFifo/_zz_ram_port10__0[8] - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_Axi_CDC/wFifo/sys_clk - SLICE_X3Y53 FDRE r u_Axi_CDC/wFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.937ns (logic 0.595ns (63.501%) route 0.342ns (36.499%)) - Logic Levels: 0 - Clock Path Skew: -0.230ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.568ns - Source Clock Delay (SCD): -0.338ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 0.595 0.257 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 0.342 0.599 u_Axi_CDC/awFifo/_zz_ram_port10[7] - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y57 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Fast Process Corner) - Data Path Delay: 0.914ns (logic 0.612ns (66.980%) route 0.302ns (33.020%)) - Logic Levels: 0 - Clock Path Skew: -0.232ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -0.573ns - Source Clock Delay (SCD): -0.341ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.967 -0.341 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 0.612 0.271 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.302 0.573 u_Axi_CDC/awFifo/_zz_ram_port10[42] - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_Axi_CDC/awFifo/sys_clk - SLICE_X20Y63 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[42]/C - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: clkfbout_clk_pll - To Clock: - -Max Delay 1 Endpoint -Min Delay 0 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT - (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN - Path Group: (none) - Path Type: Max at Fast Process Corner - Data Path Delay: 1.519ns (logic 0.029ns (1.909%) route 1.490ns (98.091%)) - Logic Levels: 1 (BUFG=1) - Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.075ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clkfbout_clk_pll fall edge) - 10.000 10.000 f - K21 0.000 10.000 f clk (IN) - net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 10.419 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 10.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) - -2.847 8.053 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT - net (fo=1, routed) 0.611 8.663 pll_clk.u_clk_pll/inst/clkfbout_clk_pll - BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.029 8.692 f pll_clk.u_clk_pll/inst/clkf_buf/O - net (fo=1, routed) 0.880 9.572 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN - ------------------------------------------------------------------- ------------------- - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: sys_clk - To Clock: - -Max Delay 41 Endpoints -Min Delay 0 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_clk - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.589ns (logic 3.629ns (42.252%) route 4.960ns (57.748%)) - Logic Levels: 2 (BUFG=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk fall edge) 10.000 10.000 f - K21 0.000 10.000 f clk (IN) - net (fo=0) 0.000 10.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 11.463 f pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 12.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 3.725 f pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 5.562 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 5.658 f pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 3.123 8.781 video_clk_OBUF - H22 OBUF (Prop_obuf_I_O) 3.533 12.314 f video_clk_OBUF_inst/O - net (fo=0) 0.000 12.314 video_clk - H22 f video_clk (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.637ns (logic 5.878ns (40.155%) route 8.759ns (59.845%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.844 8.704 video_red_OBUF[0] - K23 OBUF (Prop_obuf_I_O) 3.533 12.236 r video_red_OBUF[0]_inst/O - net (fo=0) 0.000 12.236 video_red[0] - K23 r video_red[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.524ns (logic 5.905ns (40.660%) route 8.618ns (59.340%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.703 8.563 video_red_OBUF[0] - F24 OBUF (Prop_obuf_I_O) 3.560 12.123 r video_red_OBUF[1]_inst/O - net (fo=0) 0.000 12.123 video_red[1] - F24 r video_red[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/DVI_RECT_L_W_reg[22]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 14.257ns (logic 5.932ns (41.605%) route 8.325ns (58.395%)) - Logic Levels: 9 (CARRY4=4 LUT2=2 LUT4=1 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.941 -2.401 u_axi_dvi/sys_clk - SLICE_X11Y83 FDRE r u_axi_dvi/DVI_RECT_L_W_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y83 FDRE (Prop_fdre_C_Q) 0.456 -1.945 r u_axi_dvi/DVI_RECT_L_W_reg[22]/Q - net (fo=3, routed) 1.109 -0.836 u_axi_dvi/p_0_in6_in[6] - SLICE_X10Y83 LUT2 (Prop_lut2_I1_O) 0.124 -0.712 r u_axi_dvi/video_red_OBUF[2]_inst_i_271/O - net (fo=1, routed) 0.000 -0.712 u_axi_dvi/video_red_OBUF[2]_inst_i_271_n_0 - SLICE_X10Y83 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.380 -0.332 r u_axi_dvi/video_red_OBUF[2]_inst_i_239/CO[3] - net (fo=1, routed) 0.000 -0.332 u_axi_dvi/video_red_OBUF[2]_inst_i_239_n_0 - SLICE_X10Y84 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 -0.017 r u_axi_dvi/video_red_OBUF[2]_inst_i_200/O[3] - net (fo=1, routed) 0.864 0.847 u_axi_dvi/video_red_OBUF[2]_inst_i_200_n_4 - SLICE_X11Y84 LUT2 (Prop_lut2_I1_O) 0.307 1.154 r u_axi_dvi/video_red_OBUF[2]_inst_i_132/O - net (fo=1, routed) 0.000 1.154 u_axi_dvi/video_red_OBUF[2]_inst_i_132_n_0 - SLICE_X11Y84 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.401 1.555 r u_axi_dvi/video_red_OBUF[2]_inst_i_67/CO[3] - net (fo=1, routed) 0.000 1.555 u_axi_dvi/video_red_OBUF[2]_inst_i_67_n_0 - SLICE_X11Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.114 1.669 f u_axi_dvi/video_red_OBUF[2]_inst_i_31/CO[3] - net (fo=1, routed) 1.273 2.942 u_axi_dvi/video_red_OBUF[2]_inst_i_31_n_0 - SLICE_X16Y85 LUT4 (Prop_lut4_I0_O) 0.124 3.066 r u_axi_dvi/video_red_OBUF[2]_inst_i_6/O - net (fo=1, routed) 0.670 3.736 u_axi_dvi/video_red_OBUF[2]_inst_i_6_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I4_O) 0.124 3.860 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 4.410 8.270 video_red_OBUF[0] - E26 OBUF (Prop_obuf_I_O) 3.587 11.856 r video_red_OBUF[2]_inst/O - net (fo=0) 0.000 11.856 video_red[2] - E26 r video_red[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/vdata_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_vsync - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 12.474ns (logic 4.441ns (35.600%) route 8.033ns (64.400%)) - Logic Levels: 4 (LUT2=1 LUT4=1 LUT6=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk - SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 r u_axi_dvi/vdata_reg[3]/Q - net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] - SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 f u_axi_dvi/vdata[11]_i_4/O - net (fo=3, routed) 0.682 0.535 u_axi_dvi/vdata[11]_i_4_n_0 - SLICE_X18Y86 LUT6 (Prop_lut6_I5_O) 0.124 0.659 r u_axi_dvi/video_vsync_OBUF_inst_i_2/O - net (fo=1, routed) 0.789 1.448 u_axi_dvi/video_vsync_OBUF_inst_i_2_n_0 - SLICE_X17Y86 LUT4 (Prop_lut4_I0_O) 0.124 1.572 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O - net (fo=1, routed) 4.943 6.515 video_vsync_OBUF - H24 OBUF (Prop_obuf_I_O) 3.551 10.066 r video_vsync_OBUF_inst/O - net (fo=0) 0.000 10.066 video_vsync - H24 r video_vsync (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/vdata_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_de - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 12.135ns (logic 4.451ns (36.677%) route 7.684ns (63.323%)) - Logic Levels: 4 (LUT2=1 LUT6=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_axi_dvi/sys_clk - SLICE_X18Y79 FDRE r u_axi_dvi/vdata_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X18Y79 FDRE (Prop_fdre_C_Q) 0.518 -1.890 f u_axi_dvi/vdata_reg[3]/Q - net (fo=11, routed) 1.619 -0.271 u_axi_dvi/vdata_reg_n_0_[3] - SLICE_X18Y86 LUT2 (Prop_lut2_I0_O) 0.124 -0.147 r u_axi_dvi/vdata[11]_i_4/O - net (fo=3, routed) 0.305 0.158 u_axi_dvi/vdata[11]_i_4_n_0 - SLICE_X17Y86 LUT6 (Prop_lut6_I2_O) 0.124 0.282 r u_axi_dvi/video_de_OBUF_inst_i_2/O - net (fo=1, routed) 1.030 1.313 u_axi_dvi/video_de_OBUF_inst_i_2_n_0 - SLICE_X14Y86 LUT6 (Prop_lut6_I0_O) 0.124 1.437 r u_axi_dvi/video_de_OBUF_inst_i_1/O - net (fo=1, routed) 4.730 6.166 video_de_OBUF - G24 OBUF (Prop_obuf_I_O) 3.561 9.727 r video_de_OBUF_inst/O - net (fo=0) 0.000 9.727 video_de - G24 r video_de (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_hsync - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.932ns (logic 4.311ns (36.128%) route 7.621ns (63.872%)) - Logic Levels: 3 (LUT5=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.936 -2.406 u_axi_dvi/sys_clk - SLICE_X12Y81 FDRE r u_axi_dvi/hdata_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.888 r u_axi_dvi/hdata_reg[3]/Q - net (fo=11, routed) 1.940 0.053 u_axi_dvi/hdata_reg_n_0_[3] - SLICE_X8Y82 LUT5 (Prop_lut5_I2_O) 0.124 0.177 f u_axi_dvi/video_hsync_OBUF_inst_i_2/O - net (fo=1, routed) 0.953 1.130 u_axi_dvi/video_hsync_OBUF_inst_i_2_n_0 - SLICE_X9Y86 LUT5 (Prop_lut5_I4_O) 0.124 1.254 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O - net (fo=1, routed) 4.728 5.982 video_hsync_OBUF - J24 OBUF (Prop_obuf_I_O) 3.545 9.527 r video_hsync_OBUF_inst/O - net (fo=0) 0.000 9.527 video_hsync - J24 r video_hsync (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[8]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[8] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.822ns (logic 4.079ns (34.503%) route 7.743ns (65.497%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.016 -2.326 u_confreg/sys_clk - SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.518 -1.808 r u_confreg/led_data_reg[8]_lopt_replica/Q - net (fo=1, routed) 7.743 5.935 lopt_14 - C23 OBUF (Prop_obuf_I_O) 3.561 9.496 r leds_OBUF[8]_inst/O - net (fo=0) 0.000 9.496 leds[8] - C23 r leds[8] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[15]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[15] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.646ns (logic 4.019ns (34.509%) route 7.627ns (65.491%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[15]_lopt_replica/Q - net (fo=1, routed) 7.627 5.768 lopt_6 - B20 OBUF (Prop_obuf_I_O) 3.563 9.331 r leds_OBUF[15]_inst/O - net (fo=0) 0.000 9.331 leds[15] - B20 r leds[15] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.447ns (logic 4.018ns (35.101%) route 7.429ns (64.899%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[4]_lopt_replica/Q - net (fo=1, routed) 7.429 5.569 lopt_10 - C22 OBUF (Prop_obuf_I_O) 3.562 9.131 r leds_OBUF[4]_inst/O - net (fo=0) 0.000 9.131 leds[4] - C22 r leds[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.583ns (logic 3.995ns (34.493%) route 7.588ns (65.507%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q - net (fo=1, routed) 7.588 5.556 dpy0_OBUF[4] - E18 OBUF (Prop_obuf_I_O) 3.539 9.095 r dpy0_OBUF[4]_inst/O - net (fo=0) 0.000 9.095 dpy0[4] - E18 r dpy0[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.360ns (logic 4.147ns (36.509%) route 7.213ns (63.491%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[5]_lopt_replica/Q - net (fo=1, routed) 7.213 5.317 lopt_11 - C21 OBUF (Prop_obuf_I_O) 3.728 9.045 r leds_OBUF[5]_inst/O - net (fo=0) 0.000 9.045 leds[5] - C21 r leds[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[9] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.061ns (logic 4.038ns (36.509%) route 7.023ns (63.491%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[9]_lopt_replica/Q - net (fo=1, routed) 7.023 5.159 lopt_15 - A23 OBUF (Prop_obuf_I_O) 3.582 8.741 r leds_OBUF[9]_inst/O - net (fo=0) 0.000 8.741 leds[9] - A23 r leds[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_uart_controller/uart0/regs/mcr_reg[4]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_TX - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 11.130ns (logic 4.308ns (38.708%) route 6.822ns (61.292%)) - Logic Levels: 2 (LUT4=1 OBUFT=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X8Y66 FDRE r u_axi_uart_controller/uart0/regs/mcr_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X8Y66 FDRE (Prop_fdre_C_Q) 0.478 -1.925 r u_axi_uart_controller/uart0/regs/mcr_reg[4]/Q - net (fo=8, routed) 1.213 -0.712 u_axi_uart_controller/uart0/regs/transmitter/counter_b_reg[7]_0[0] - SLICE_X1Y60 LUT4 (Prop_lut4_I3_O) 0.301 -0.411 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_1/O - net (fo=1, routed) 5.609 5.198 UART_TX_IOBUF_inst/I - H18 OBUFT (Prop_obuft_I_O) 3.529 8.727 r UART_TX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 8.727 UART_TX - H18 r UART_TX (INOUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.508ns (logic 3.970ns (37.784%) route 6.537ns (62.216%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q - net (fo=1, routed) 6.537 4.680 dpy1_OBUF[3] - F17 OBUF (Prop_obuf_I_O) 3.514 8.194 r dpy1_OBUF[3]_inst/O - net (fo=0) 0.000 8.194 dpy1[3] - F17 r dpy1[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.468ns (logic 4.014ns (38.349%) route 6.454ns (61.651%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q - net (fo=1, routed) 6.454 4.422 dpy0_OBUF[2] - B21 OBUF (Prop_obuf_I_O) 3.558 7.981 r dpy0_OBUF[2]_inst/O - net (fo=0) 0.000 7.981 dpy0[2] - B21 r dpy0[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.251ns (logic 4.018ns (39.198%) route 6.233ns (60.802%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[3]_lopt_replica/Q - net (fo=1, routed) 6.233 4.375 lopt_9 - D23 OBUF (Prop_obuf_I_O) 3.562 7.937 r leds_OBUF[3]_inst/O - net (fo=0) 0.000 7.937 leds[3] - D23 r leds[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[2]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 10.239ns (logic 4.043ns (39.483%) route 6.196ns (60.517%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[2]_lopt_replica/Q - net (fo=1, routed) 6.196 4.339 lopt_8 - A24 OBUF (Prop_obuf_I_O) 3.587 7.926 r leds_OBUF[2]_inst/O - net (fo=0) 0.000 7.926 leds[2] - A24 r leds[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[11]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[11] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.633ns (logic 4.023ns (41.758%) route 5.611ns (58.242%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[11]_lopt_replica/Q - net (fo=1, routed) 5.611 3.752 lopt_2 - A18 OBUF (Prop_obuf_I_O) 3.567 7.319 r leds_OBUF[11]_inst/O - net (fo=0) 0.000 7.319 leds[11] - A18 r leds[11] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.588ns (logic 3.993ns (41.645%) route 5.595ns (58.355%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q - net (fo=1, routed) 5.595 3.738 dpy1_OBUF[6] - F15 OBUF (Prop_obuf_I_O) 3.537 7.275 r dpy1_OBUF[6]_inst/O - net (fo=0) 0.000 7.275 dpy1[6] - F15 r dpy1[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[6]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.545ns (logic 4.133ns (43.294%) route 5.413ns (56.706%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[6]_lopt_replica/Q - net (fo=1, routed) 5.413 3.517 lopt_12 - E20 OBUF (Prop_obuf_I_O) 3.714 7.231 r leds_OBUF[6]_inst/O - net (fo=0) 0.000 7.231 leds[6] - E20 r leds[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.552ns (logic 4.002ns (41.895%) route 5.550ns (58.105%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q - net (fo=1, routed) 5.550 3.519 dpy0_OBUF[5] - C19 OBUF (Prop_obuf_I_O) 3.546 7.065 r dpy0_OBUF[5]_inst/O - net (fo=0) 0.000 7.065 dpy0[5] - C19 r dpy0[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[2] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.354ns (logic 3.998ns (42.735%) route 5.357ns (57.265%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q - net (fo=1, routed) 5.357 3.499 dpy1_OBUF[2] - E17 OBUF (Prop_obuf_I_O) 3.542 7.041 r dpy1_OBUF[2]_inst/O - net (fo=0) 0.000 7.041 dpy1[2] - E17 r dpy1[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_uart_controller/uart0/regs/sclk_reg_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_RX - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.365ns (logic 4.162ns (44.443%) route 5.203ns (55.557%)) - Logic Levels: 2 (LUT2=1 OBUFT=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.944 -2.398 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X10Y64 FDRE r u_axi_uart_controller/uart0/regs/sclk_reg_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X10Y64 FDRE (Prop_fdre_C_Q) 0.518 -1.880 r u_axi_uart_controller/uart0/regs/sclk_reg_reg/Q - net (fo=2, routed) 0.521 -1.358 u_axi_uart_controller/uart0/regs/sclk_reg_reg_n_0 - SLICE_X10Y64 LUT2 (Prop_lut2_I0_O) 0.124 -1.234 r u_axi_uart_controller/uart0/regs/UART_RX_IOBUF_inst_i_1/O - net (fo=1, routed) 4.682 3.448 UART_RX_IOBUF_inst/I - J20 OBUFT (Prop_obuft_I_O) 3.520 6.968 r UART_RX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 6.968 UART_RX - J20 r UART_RX (INOUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.190ns (logic 4.001ns (43.538%) route 5.189ns (56.462%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q - net (fo=1, routed) 5.189 3.157 dpy0_OBUF[1] - D19 OBUF (Prop_obuf_I_O) 3.545 6.703 r dpy0_OBUF[1]_inst/O - net (fo=0) 0.000 6.703 dpy0[1] - D19 r dpy0[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[4] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.973ns (logic 3.998ns (44.549%) route 4.976ns (55.451%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q - net (fo=1, routed) 4.976 3.118 dpy1_OBUF[4] - E16 OBUF (Prop_obuf_I_O) 3.542 6.660 r dpy1_OBUF[4]_inst/O - net (fo=0) 0.000 6.660 dpy1[4] - E16 r dpy1[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[3] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 9.071ns (logic 4.029ns (44.418%) route 5.042ns (55.582%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q - net (fo=1, routed) 5.042 3.010 dpy0_OBUF[3] - A19 OBUF (Prop_obuf_I_O) 3.573 6.583 r dpy0_OBUF[3]_inst/O - net (fo=0) 0.000 6.583 dpy0[3] - A19 r dpy0[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.824ns (logic 4.005ns (45.390%) route 4.819ns (54.610%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q - net (fo=1, routed) 4.819 2.961 dpy1_OBUF[1] - D16 OBUF (Prop_obuf_I_O) 3.549 6.510 r dpy1_OBUF[1]_inst/O - net (fo=0) 0.000 6.510 dpy1[1] - D16 r dpy1[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[12]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[12] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.826ns (logic 3.998ns (45.302%) route 4.828ns (54.698%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.025 -2.317 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.456 -1.861 r u_confreg/led_data_reg[12]_lopt_replica/Q - net (fo=1, routed) 4.828 2.967 lopt_3 - D20 OBUF (Prop_obuf_I_O) 3.542 6.510 r leds_OBUF[12]_inst/O - net (fo=0) 0.000 6.510 leds[12] - D20 r leds[12] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.940ns (logic 4.016ns (44.923%) route 4.924ns (55.077%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q - net (fo=1, routed) 4.924 2.892 dpy0_OBUF[0] - B19 OBUF (Prop_obuf_I_O) 3.560 6.452 r dpy0_OBUF[0]_inst/O - net (fo=0) 0.000 6.452 dpy0[0] - B19 r dpy0[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[5] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.755ns (logic 3.990ns (45.576%) route 4.765ns (54.424%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q - net (fo=1, routed) 4.765 2.907 dpy1_OBUF[5] - G16 OBUF (Prop_obuf_I_O) 3.534 6.441 r dpy1_OBUF[5]_inst/O - net (fo=0) 0.000 6.441 dpy1[5] - G16 r dpy1[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.735ns (logic 4.021ns (46.039%) route 4.713ns (53.961%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q - net (fo=1, routed) 4.713 2.856 dpy1_OBUF[0] - A17 OBUF (Prop_obuf_I_O) 3.565 6.421 r dpy1_OBUF[0]_inst/O - net (fo=0) 0.000 6.421 dpy1[0] - A17 r dpy1[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[7] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.710ns (logic 3.976ns (45.648%) route 4.734ns (54.352%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.456 -1.858 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q - net (fo=1, routed) 4.734 2.877 dpy1_OBUF[7] - G17 OBUF (Prop_obuf_I_O) 3.520 6.397 r dpy1_OBUF[7]_inst/O - net (fo=0) 0.000 6.397 dpy1[7] - G17 r dpy1[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[14]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[14] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.585ns (logic 4.019ns (46.814%) route 4.566ns (53.186%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[14]_lopt_replica/Q - net (fo=1, routed) 4.566 2.707 lopt_5 - A20 OBUF (Prop_obuf_I_O) 3.563 6.270 r leds_OBUF[14]_inst/O - net (fo=0) 0.000 6.270 leds[14] - A20 r leds[14] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[6] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.741ns (logic 4.012ns (45.901%) route 4.729ns (54.099%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q - net (fo=1, routed) 4.729 2.697 dpy0_OBUF[6] - B17 OBUF (Prop_obuf_I_O) 3.556 6.254 r dpy0_OBUF[6]_inst/O - net (fo=0) 0.000 6.254 dpy0[6] - B17 r dpy0[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[10]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[10] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.566ns (logic 4.003ns (46.730%) route 4.563ns (53.270%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.022 -2.320 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.456 -1.864 r u_confreg/led_data_reg[10]_lopt_replica/Q - net (fo=1, routed) 4.563 2.700 lopt_1 - D21 OBUF (Prop_obuf_I_O) 3.547 6.247 r leds_OBUF[10]_inst/O - net (fo=0) 0.000 6.247 leds[10] - D21 r leds[10] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[7] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.730ns (logic 4.001ns (45.828%) route 4.729ns (54.172%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.854 -2.488 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.456 -2.032 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q - net (fo=1, routed) 4.729 2.697 dpy0_OBUF[7] - C17 OBUF (Prop_obuf_I_O) 3.545 6.242 r dpy0_OBUF[7]_inst/O - net (fo=0) 0.000 6.242 dpy0[7] - C17 r dpy0[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[7]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[7] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.548ns (logic 4.164ns (48.712%) route 4.384ns (51.288%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.419 -1.896 r u_confreg/led_data_reg[7]_lopt_replica/Q - net (fo=1, routed) 4.384 2.489 lopt_13 - B22 OBUF (Prop_obuf_I_O) 3.745 6.234 r leds_OBUF[7]_inst/O - net (fo=0) 0.000 6.234 leds[7] - B22 r leds[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[13]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[13] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.473ns (logic 4.027ns (47.524%) route 4.446ns (52.476%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[13]_lopt_replica/Q - net (fo=1, routed) 4.446 2.588 lopt_4 - A22 OBUF (Prop_obuf_I_O) 3.571 6.159 r leds_OBUF[13]_inst/O - net (fo=0) 0.000 6.159 leds[13] - A22 r leds[13] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[1]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[1] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.398ns (logic 3.997ns (47.597%) route 4.401ns (52.403%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.028 -2.314 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.456 -1.858 r u_confreg/led_data_reg[1]_lopt_replica/Q - net (fo=1, routed) 4.401 2.543 lopt_7 - E21 OBUF (Prop_obuf_I_O) 3.541 6.084 r leds_OBUF[1]_inst/O - net (fo=0) 0.000 6.084 leds[1] - E21 r leds[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[0]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[0] - (output port) - Path Group: (none) - Path Type: Max at Slow Process Corner - Data Path Delay: 8.138ns (logic 4.031ns (49.529%) route 4.108ns (50.471%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.027 -2.315 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.456 -1.859 r u_confreg/led_data_reg[0]_lopt_replica/Q - net (fo=1, routed) 4.108 2.249 lopt - B24 OBUF (Prop_obuf_I_O) 3.575 5.824 r leds_OBUF[0]_inst/O - net (fo=0) 0.000 5.824 leds[0] - B24 r leds[0] (OUT) - ------------------------------------------------------------------- ------------------- - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: - To Clock: sys_clk - -Max Delay 43 Endpoints -Min Delay 0 Endpoints --------------------------------------------------------------------------------------- - - -Max Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: dip_sw[8] - (input port) - Destination: u_confreg/s_rdata_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.851ns (logic 1.724ns (14.546%) route 10.127ns (85.454%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.940ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M6 0.000 0.000 r dip_sw[8] (IN) - net (fo=0) 0.000 0.000 dip_sw[8] - M6 IBUF (Prop_ibuf_I_O) 1.476 1.476 r dip_sw_IBUF[8]_inst/O - net (fo=1, routed) 9.460 10.936 u_confreg/dip_sw_IBUF[8] - SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.124 11.060 r u_confreg/s_rdata[8]_i_4/O - net (fo=1, routed) 0.667 11.727 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 11.851 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O - net (fo=1, routed) 0.000 11.851 u_confreg/u_int_ctrl_n_23 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C - -Slack: inf - Source: dip_sw[20] - (input port) - Destination: u_confreg/s_rdata_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.647ns (logic 1.723ns (14.794%) route 9.924ns (85.206%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M4 0.000 0.000 r dip_sw[20] (IN) - net (fo=0) 0.000 0.000 dip_sw[20] - M4 IBUF (Prop_ibuf_I_O) 1.475 1.475 r dip_sw_IBUF[20]_inst/O - net (fo=1, routed) 9.163 10.638 u_confreg/dip_sw_IBUF[20] - SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.762 r u_confreg/s_rdata[20]_i_4/O - net (fo=1, routed) 0.761 11.523 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 11.647 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O - net (fo=1, routed) 0.000 11.647 u_confreg/u_int_ctrl_n_11 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C - -Slack: inf - Source: dip_sw[13] - (input port) - Destination: u_confreg/s_rdata_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.183ns (logic 1.734ns (15.504%) route 9.449ns (84.496%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K3 0.000 0.000 r dip_sw[13] (IN) - net (fo=0) 0.000 0.000 dip_sw[13] - K3 IBUF (Prop_ibuf_I_O) 1.486 1.486 r dip_sw_IBUF[13]_inst/O - net (fo=1, routed) 8.863 10.349 u_confreg/dip_sw_IBUF[13] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.473 r u_confreg/s_rdata[13]_i_4/O - net (fo=1, routed) 0.586 11.059 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 11.183 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O - net (fo=1, routed) 0.000 11.183 u_confreg/u_int_ctrl_n_18 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C - -Slack: inf - Source: dip_sw[1] - (input port) - Destination: u_confreg/s_rdata_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.155ns (logic 1.746ns (15.651%) route 9.409ns (84.349%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J3 0.000 0.000 r dip_sw[1] (IN) - net (fo=0) 0.000 0.000 dip_sw[1] - J3 IBUF (Prop_ibuf_I_O) 1.498 1.498 r dip_sw_IBUF[1]_inst/O - net (fo=1, routed) 8.467 9.965 u_confreg/dip_sw_IBUF[1] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 10.089 r u_confreg/s_rdata[1]_i_4/O - net (fo=1, routed) 0.942 11.031 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 11.155 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O - net (fo=1, routed) 0.000 11.155 u_confreg/u_int_ctrl_n_30 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C - -Slack: inf - Source: dip_sw[11] - (input port) - Destination: u_confreg/s_rdata_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 11.052ns (logic 1.719ns (15.556%) route 9.333ns (84.444%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.937ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.937ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L7 0.000 0.000 r dip_sw[11] (IN) - net (fo=0) 0.000 0.000 dip_sw[11] - L7 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[11]_inst/O - net (fo=1, routed) 8.677 10.148 u_confreg/dip_sw_IBUF[11] - SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.124 10.272 r u_confreg/s_rdata[11]_i_4/O - net (fo=1, routed) 0.656 10.928 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 11.052 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O - net (fo=1, routed) 0.000 11.052 u_confreg/u_int_ctrl_n_20 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C - -Slack: inf - Source: dip_sw[25] - (input port) - Destination: u_confreg/s_rdata_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.711ns (logic 1.737ns (16.220%) route 8.974ns (83.780%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R3 0.000 0.000 r dip_sw[25] (IN) - net (fo=0) 0.000 0.000 dip_sw[25] - R3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[25]_inst/O - net (fo=1, routed) 8.245 9.734 u_confreg/dip_sw_IBUF[25] - SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.124 9.858 r u_confreg/s_rdata[25]_i_4/O - net (fo=1, routed) 0.729 10.587 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 10.711 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O - net (fo=1, routed) 0.000 10.711 u_confreg/u_int_ctrl_n_6 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C - -Slack: inf - Source: dip_sw[19] - (input port) - Destination: u_confreg/s_rdata_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.426ns (logic 1.726ns (16.557%) route 8.700ns (83.443%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.934ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.934ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L4 0.000 0.000 r dip_sw[19] (IN) - net (fo=0) 0.000 0.000 dip_sw[19] - L4 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[19]_inst/O - net (fo=1, routed) 8.546 10.024 u_confreg/dip_sw_IBUF[19] - SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.124 10.148 r u_confreg/s_rdata[19]_i_4/O - net (fo=1, routed) 0.154 10.302 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 - SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.124 10.426 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O - net (fo=1, routed) 0.000 10.426 u_confreg/u_int_ctrl_n_12 - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C - -Slack: inf - Source: touch_btn[2] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 10.138ns (logic 1.487ns (14.666%) route 8.651ns (85.334%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P3 0.000 0.000 r touch_btn[2] (IN) - net (fo=0) 0.000 0.000 touch_btn[2] - P3 IBUF (Prop_ibuf_I_O) 1.487 1.487 r touch_btn_IBUF[2]_inst/O - net (fo=1, routed) 8.651 10.138 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/u_int_ctrl/sys_clk - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C - -Slack: inf - Source: dip_sw[9] - (input port) - Destination: u_confreg/s_rdata_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.432ns (logic 1.718ns (20.372%) route 6.714ns (79.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.938ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.938ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N7 0.000 0.000 r dip_sw[9] (IN) - net (fo=0) 0.000 0.000 dip_sw[9] - N7 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[9]_inst/O - net (fo=1, routed) 6.067 7.537 u_confreg/dip_sw_IBUF[9] - SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.661 r u_confreg/s_rdata[9]_i_4/O - net (fo=1, routed) 0.647 8.308 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 - SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.124 8.432 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O - net (fo=1, routed) 0.000 8.432 u_confreg/u_int_ctrl_n_22 - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.890 -1.938 u_confreg/sys_clk - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C - -Slack: inf - Source: dip_sw[4] - (input port) - Destination: u_confreg/s_rdata_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.408ns (logic 1.736ns (20.649%) route 6.672ns (79.351%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.934ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.934ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P4 0.000 0.000 r dip_sw[4] (IN) - net (fo=0) 0.000 0.000 dip_sw[4] - P4 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[4]_inst/O - net (fo=1, routed) 6.006 7.495 u_confreg/dip_sw_IBUF[4] - SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.124 7.619 r u_confreg/s_rdata[4]_i_4/O - net (fo=1, routed) 0.666 8.284 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 - SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.408 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O - net (fo=1, routed) 0.000 8.408 u_confreg/u_int_ctrl_n_27 - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.894 -1.934 u_confreg/sys_clk - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C - -Slack: inf - Source: dip_sw[10] - (input port) - Destination: u_confreg/s_rdata_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.284ns (logic 1.720ns (20.765%) route 6.564ns (79.235%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M7 0.000 0.000 r dip_sw[10] (IN) - net (fo=0) 0.000 0.000 dip_sw[10] - M7 IBUF (Prop_ibuf_I_O) 1.472 1.472 r dip_sw_IBUF[10]_inst/O - net (fo=1, routed) 6.100 7.572 u_confreg/dip_sw_IBUF[10] - SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.124 7.696 r u_confreg/s_rdata[10]_i_4/O - net (fo=1, routed) 0.464 8.160 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.284 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O - net (fo=1, routed) 0.000 8.284 u_confreg/u_int_ctrl_n_21 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C - -Slack: inf - Source: dip_sw[23] - (input port) - Destination: u_confreg/s_rdata_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.265ns (logic 1.766ns (21.372%) route 6.499ns (78.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N1 0.000 0.000 r dip_sw[23] (IN) - net (fo=0) 0.000 0.000 dip_sw[23] - N1 IBUF (Prop_ibuf_I_O) 1.518 1.518 r dip_sw_IBUF[23]_inst/O - net (fo=1, routed) 5.411 6.929 u_confreg/dip_sw_IBUF[23] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 7.053 r u_confreg/s_rdata[23]_i_4/O - net (fo=1, routed) 1.088 8.141 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 8.265 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O - net (fo=1, routed) 0.000 8.265 u_confreg/u_int_ctrl_n_8 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C - -Slack: inf - Source: dip_sw[5] - (input port) - Destination: u_confreg/s_rdata_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.233ns (logic 1.718ns (20.872%) route 6.515ns (79.128%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L5 0.000 0.000 r dip_sw[5] (IN) - net (fo=0) 0.000 0.000 dip_sw[5] - L5 IBUF (Prop_ibuf_I_O) 1.470 1.470 r dip_sw_IBUF[5]_inst/O - net (fo=1, routed) 5.514 6.985 u_confreg/dip_sw_IBUF[5] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.109 r u_confreg/s_rdata[5]_i_4/O - net (fo=1, routed) 1.000 8.109 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.233 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O - net (fo=1, routed) 0.000 8.233 u_confreg/u_int_ctrl_n_26 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C - -Slack: inf - Source: dip_sw[26] - (input port) - Destination: u_confreg/s_rdata_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.161ns (logic 1.757ns (21.535%) route 6.403ns (78.465%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.011ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T4 0.000 0.000 r dip_sw[26] (IN) - net (fo=0) 0.000 0.000 dip_sw[26] - T4 IBUF (Prop_ibuf_I_O) 1.509 1.509 r dip_sw_IBUF[26]_inst/O - net (fo=1, routed) 5.313 6.823 u_confreg/dip_sw_IBUF[26] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.947 r u_confreg/s_rdata[26]_i_4/O - net (fo=1, routed) 1.090 8.037 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 8.161 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O - net (fo=1, routed) 0.000 8.161 u_confreg/u_int_ctrl_n_5 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C - -Slack: inf - Source: dip_sw[17] - (input port) - Destination: u_confreg/s_rdata_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.117ns (logic 1.752ns (21.585%) route 6.365ns (78.415%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K1 0.000 0.000 r dip_sw[17] (IN) - net (fo=0) 0.000 0.000 dip_sw[17] - K1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[17]_inst/O - net (fo=1, routed) 5.516 7.020 u_confreg/dip_sw_IBUF[17] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.144 r u_confreg/s_rdata[17]_i_4/O - net (fo=1, routed) 0.849 7.993 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.117 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O - net (fo=1, routed) 0.000 8.117 u_confreg/u_int_ctrl_n_14 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C - -Slack: inf - Source: dip_sw[2] - (input port) - Destination: u_confreg/s_rdata_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.080ns (logic 1.743ns (21.573%) route 6.337ns (78.427%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.017ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.017ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M2 0.000 0.000 r dip_sw[2] (IN) - net (fo=0) 0.000 0.000 dip_sw[2] - M2 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[2]_inst/O - net (fo=1, routed) 5.346 6.841 u_confreg/dip_sw_IBUF[2] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.965 r u_confreg/s_rdata[2]_i_4/O - net (fo=1, routed) 0.991 7.956 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.124 8.080 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O - net (fo=1, routed) 0.000 8.080 u_confreg/u_int_ctrl_n_29 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C - -Slack: inf - Source: dip_sw[6] - (input port) - Destination: u_confreg/s_rdata_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.077ns (logic 1.736ns (21.494%) route 6.341ns (78.506%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L3 0.000 0.000 r dip_sw[6] (IN) - net (fo=0) 0.000 0.000 dip_sw[6] - L3 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[6]_inst/O - net (fo=1, routed) 5.394 6.882 u_confreg/dip_sw_IBUF[6] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.124 7.006 r u_confreg/s_rdata[6]_i_4/O - net (fo=1, routed) 0.947 7.953 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 8.077 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O - net (fo=1, routed) 0.000 8.077 u_confreg/u_int_ctrl_n_25 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C - -Slack: inf - Source: dip_sw[14] - (input port) - Destination: u_confreg/s_rdata_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 8.038ns (logic 1.763ns (21.934%) route 6.275ns (78.066%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J1 0.000 0.000 r dip_sw[14] (IN) - net (fo=0) 0.000 0.000 dip_sw[14] - J1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r dip_sw_IBUF[14]_inst/O - net (fo=1, routed) 5.331 6.846 u_confreg/dip_sw_IBUF[14] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.970 r u_confreg/s_rdata[14]_i_4/O - net (fo=1, routed) 0.944 7.914 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 8.038 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O - net (fo=1, routed) 0.000 8.038 u_confreg/u_int_ctrl_n_17 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C - -Slack: inf - Source: dip_sw[15] - (input port) - Destination: u_confreg/s_rdata_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.951ns (logic 1.742ns (21.911%) route 6.209ns (78.089%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L2 0.000 0.000 r dip_sw[15] (IN) - net (fo=0) 0.000 0.000 dip_sw[15] - L2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[15]_inst/O - net (fo=1, routed) 5.453 6.948 u_confreg/dip_sw_IBUF[15] - SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.124 7.072 r u_confreg/s_rdata[15]_i_4/O - net (fo=1, routed) 0.755 7.827 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.951 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O - net (fo=1, routed) 0.000 7.951 u_confreg/u_int_ctrl_n_16 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C - -Slack: inf - Source: dip_sw[0] - (input port) - Destination: u_confreg/s_rdata_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.807ns (logic 1.743ns (22.326%) route 6.064ns (77.674%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.937ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.937ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T3 0.000 0.000 r dip_sw[0] (IN) - net (fo=0) 0.000 0.000 dip_sw[0] - T3 IBUF (Prop_ibuf_I_O) 1.495 1.495 r dip_sw_IBUF[0]_inst/O - net (fo=1, routed) 5.166 6.661 u_confreg/dip_sw_IBUF[0] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.785 r u_confreg/s_rdata[0]_i_4/O - net (fo=1, routed) 0.898 7.683 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.124 7.807 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O - net (fo=1, routed) 0.000 7.807 u_confreg/u_int_ctrl_n_31 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.891 -1.937 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C - -Slack: inf - Source: dip_sw[3] - (input port) - Destination: u_confreg/s_rdata_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.770ns (logic 1.752ns (22.553%) route 6.018ns (77.447%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.940ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.940ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P1 0.000 0.000 r dip_sw[3] (IN) - net (fo=0) 0.000 0.000 dip_sw[3] - P1 IBUF (Prop_ibuf_I_O) 1.504 1.504 r dip_sw_IBUF[3]_inst/O - net (fo=1, routed) 5.171 6.676 u_confreg/dip_sw_IBUF[3] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.800 r u_confreg/s_rdata[3]_i_4/O - net (fo=1, routed) 0.846 7.646 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.124 7.770 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O - net (fo=1, routed) 0.000 7.770 u_confreg/u_int_ctrl_n_28 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.888 -1.940 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C - -Slack: inf - Source: dip_sw[21] - (input port) - Destination: u_confreg/s_rdata_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.691ns (logic 1.736ns (22.574%) route 5.955ns (77.426%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N2 0.000 0.000 r dip_sw[21] (IN) - net (fo=0) 0.000 0.000 dip_sw[21] - N2 IBUF (Prop_ibuf_I_O) 1.488 1.488 r dip_sw_IBUF[21]_inst/O - net (fo=1, routed) 5.069 6.557 u_confreg/dip_sw_IBUF[21] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.681 r u_confreg/s_rdata[21]_i_4/O - net (fo=1, routed) 0.886 7.567 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.691 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O - net (fo=1, routed) 0.000 7.691 u_confreg/u_int_ctrl_n_10 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C - -Slack: inf - Source: dip_sw[16] - (input port) - Destination: u_confreg/s_rdata_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.536ns (logic 1.748ns (23.196%) route 5.788ns (76.804%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K2 0.000 0.000 r dip_sw[16] (IN) - net (fo=0) 0.000 0.000 dip_sw[16] - K2 IBUF (Prop_ibuf_I_O) 1.500 1.500 r dip_sw_IBUF[16]_inst/O - net (fo=1, routed) 5.492 6.993 u_confreg/dip_sw_IBUF[16] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.124 7.117 r u_confreg/s_rdata[16]_i_4/O - net (fo=1, routed) 0.296 7.412 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.536 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O - net (fo=1, routed) 0.000 7.536 u_confreg/u_int_ctrl_n_15 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C - -Slack: inf - Source: dip_sw[24] - (input port) - Destination: u_confreg/s_rdata_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.500ns (logic 1.714ns (22.860%) route 5.785ns (77.140%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P5 0.000 0.000 r dip_sw[24] (IN) - net (fo=0) 0.000 0.000 dip_sw[24] - P5 IBUF (Prop_ibuf_I_O) 1.466 1.466 r dip_sw_IBUF[24]_inst/O - net (fo=1, routed) 4.979 6.445 u_confreg/dip_sw_IBUF[24] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.569 r u_confreg/s_rdata[24]_i_4/O - net (fo=1, routed) 0.806 7.376 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.500 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O - net (fo=1, routed) 0.000 7.500 u_confreg/u_int_ctrl_n_7 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C - -Slack: inf - Source: dip_sw[18] - (input port) - Destination: u_confreg/s_rdata_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.469ns (logic 1.737ns (23.257%) route 5.732ns (76.743%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.011ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.011ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N3 0.000 0.000 r dip_sw[18] (IN) - net (fo=0) 0.000 0.000 dip_sw[18] - N3 IBUF (Prop_ibuf_I_O) 1.489 1.489 r dip_sw_IBUF[18]_inst/O - net (fo=1, routed) 5.052 6.541 u_confreg/dip_sw_IBUF[18] - SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.124 6.665 r u_confreg/s_rdata[18]_i_4/O - net (fo=1, routed) 0.680 7.345 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.124 7.469 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O - net (fo=1, routed) 0.000 7.469 u_confreg/u_int_ctrl_n_13 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.817 -2.011 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C - -Slack: inf - Source: dip_sw[7] - (input port) - Destination: u_confreg/s_rdata_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.415ns (logic 1.719ns (23.186%) route 5.696ns (76.814%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.933ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.933ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N6 0.000 0.000 r dip_sw[7] (IN) - net (fo=0) 0.000 0.000 dip_sw[7] - N6 IBUF (Prop_ibuf_I_O) 1.471 1.471 r dip_sw_IBUF[7]_inst/O - net (fo=1, routed) 5.542 7.013 u_confreg/dip_sw_IBUF[7] - SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.124 7.137 r u_confreg/s_rdata[7]_i_4/O - net (fo=1, routed) 0.154 7.291 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 - SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.124 7.415 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O - net (fo=1, routed) 0.000 7.415 u_confreg/u_int_ctrl_n_24 - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.895 -1.933 u_confreg/sys_clk - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C - -Slack: inf - Source: dip_sw[12] - (input port) - Destination: u_confreg/s_rdata_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.331ns (logic 1.717ns (23.423%) route 5.614ns (76.577%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.936ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.936ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M5 0.000 0.000 r dip_sw[12] (IN) - net (fo=0) 0.000 0.000 dip_sw[12] - M5 IBUF (Prop_ibuf_I_O) 1.469 1.469 r dip_sw_IBUF[12]_inst/O - net (fo=1, routed) 5.177 6.646 u_confreg/dip_sw_IBUF[12] - SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.124 6.770 r u_confreg/s_rdata[12]_i_4/O - net (fo=1, routed) 0.437 7.207 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.124 7.331 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O - net (fo=1, routed) 0.000 7.331 u_confreg/u_int_ctrl_n_19 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.892 -1.936 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C - -Slack: inf - Source: dip_sw[30] - (input port) - Destination: u_confreg/s_rdata_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.316ns (logic 1.707ns (23.334%) route 5.609ns (76.666%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R6 0.000 0.000 r dip_sw[30] (IN) - net (fo=0) 0.000 0.000 dip_sw[30] - R6 IBUF (Prop_ibuf_I_O) 1.459 1.459 r dip_sw_IBUF[30]_inst/O - net (fo=1, routed) 4.515 5.975 u_confreg/dip_sw_IBUF[30] - SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.124 6.099 r u_confreg/s_rdata[30]_i_4/O - net (fo=1, routed) 1.093 7.192 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.316 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O - net (fo=1, routed) 0.000 7.316 u_confreg/u_int_ctrl_n_1 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C - -Slack: inf - Source: dip_sw[29] - (input port) - Destination: u_confreg/s_rdata_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.273ns (logic 1.726ns (23.732%) route 5.547ns (76.268%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T5 0.000 0.000 r dip_sw[29] (IN) - net (fo=0) 0.000 0.000 dip_sw[29] - T5 IBUF (Prop_ibuf_I_O) 1.478 1.478 r dip_sw_IBUF[29]_inst/O - net (fo=1, routed) 4.537 6.015 u_confreg/dip_sw_IBUF[29] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.139 r u_confreg/s_rdata[29]_i_4/O - net (fo=1, routed) 1.010 7.149 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.273 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O - net (fo=1, routed) 0.000 7.273 u_confreg/u_int_ctrl_n_2 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C - -Slack: inf - Source: touch_btn[3] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.267ns (logic 1.513ns (20.816%) route 5.755ns (79.184%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -1.938ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.938ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - U2 0.000 0.000 r touch_btn[3] (IN) - net (fo=0) 0.000 0.000 touch_btn[3] - U2 IBUF (Prop_ibuf_I_O) 1.513 1.513 r touch_btn_IBUF[3]_inst/O - net (fo=1, routed) 5.755 7.267 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.890 -1.938 u_confreg/u_int_ctrl/sys_clk - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C - -Slack: inf - Source: touch_btn[1] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.239ns (logic 1.515ns (20.930%) route 5.724ns (79.070%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -2.009ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M1 0.000 0.000 r touch_btn[1] (IN) - net (fo=0) 0.000 0.000 touch_btn[1] - M1 IBUF (Prop_ibuf_I_O) 1.515 1.515 r touch_btn_IBUF[1]_inst/O - net (fo=1, routed) 5.724 7.239 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C - -Slack: inf - Source: dip_sw[28] - (input port) - Destination: u_confreg/s_rdata_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.116ns (logic 1.716ns (24.110%) route 5.400ns (75.890%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.931ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.931ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R5 0.000 0.000 r dip_sw[28] (IN) - net (fo=0) 0.000 0.000 dip_sw[28] - R5 IBUF (Prop_ibuf_I_O) 1.468 1.468 r dip_sw_IBUF[28]_inst/O - net (fo=1, routed) 4.960 6.427 u_confreg/dip_sw_IBUF[28] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.551 r u_confreg/s_rdata[28]_i_4/O - net (fo=1, routed) 0.440 6.992 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.124 7.116 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O - net (fo=1, routed) 0.000 7.116 u_confreg/u_int_ctrl_n_3 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.897 -1.931 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C - -Slack: inf - Source: dip_sw[22] - (input port) - Destination: u_confreg/s_rdata_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 7.094ns (logic 1.710ns (24.108%) route 5.384ns (75.892%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P6 0.000 0.000 r dip_sw[22] (IN) - net (fo=0) 0.000 0.000 dip_sw[22] - P6 IBUF (Prop_ibuf_I_O) 1.462 1.462 r dip_sw_IBUF[22]_inst/O - net (fo=1, routed) 4.542 6.004 u_confreg/dip_sw_IBUF[22] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.124 6.128 r u_confreg/s_rdata[22]_i_4/O - net (fo=1, routed) 0.842 6.970 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 - SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.124 7.094 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O - net (fo=1, routed) 0.000 7.094 u_confreg/u_int_ctrl_n_9 - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.945ns (logic 1.963ns (28.269%) route 4.982ns (71.731%)) - Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) - Clock Path Skew: -1.929ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.929ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.683 6.191 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.372 6.563 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O - net (fo=1, routed) 0.382 6.945 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C - -Slack: inf - Source: dip_sw[27] - (input port) - Destination: u_confreg/s_rdata_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.892ns (logic 1.753ns (25.432%) route 5.139ns (74.568%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -2.010ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.010ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R1 0.000 0.000 r dip_sw[27] (IN) - net (fo=0) 0.000 0.000 dip_sw[27] - R1 IBUF (Prop_ibuf_I_O) 1.505 1.505 r dip_sw_IBUF[27]_inst/O - net (fo=1, routed) 4.238 5.743 u_confreg/dip_sw_IBUF[27] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.124 5.867 r u_confreg/s_rdata[27]_i_4/O - net (fo=1, routed) 0.902 6.768 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.892 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O - net (fo=1, routed) 0.000 6.892 u_confreg/u_int_ctrl_n_4 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.818 -2.010 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C - -Slack: inf - Source: dip_sw[31] - (input port) - Destination: u_confreg/s_rdata_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.857ns (logic 1.742ns (25.399%) route 5.116ns (74.601%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R2 0.000 0.000 r dip_sw[31] (IN) - net (fo=0) 0.000 0.000 dip_sw[31] - R2 IBUF (Prop_ibuf_I_O) 1.494 1.494 r dip_sw_IBUF[31]_inst/O - net (fo=1, routed) 4.636 6.130 u_confreg/dip_sw_IBUF[31] - SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.124 6.254 r u_confreg/s_rdata[31]_i_6/O - net (fo=1, routed) 0.480 6.733 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.124 6.857 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O - net (fo=1, routed) 0.000 6.857 u_confreg/u_int_ctrl_n_0 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.182ns (logic 1.939ns (31.371%) route 4.243ns (68.629%)) - Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.117 5.508 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.326 5.834 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.348 6.182 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O - net (fo=1, routed) 0.000 6.182 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 6.135ns (logic 1.598ns (26.054%) route 4.537ns (73.946%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -1.929ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.929ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 r UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.916 5.391 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.124 5.515 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O - net (fo=1, routed) 0.620 6.135 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.899 -1.929 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C - -Slack: inf - Source: touch_btn[0] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.929ns (logic 1.499ns (25.283%) route 4.430ns (74.717%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -2.009ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -2.009ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T2 0.000 0.000 r touch_btn[0] (IN) - net (fo=0) 0.000 0.000 touch_btn[0] - T2 IBUF (Prop_ibuf_I_O) 1.499 1.499 r touch_btn_IBUF[0]_inst/O - net (fo=1, routed) 4.430 5.929 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.819 -2.009 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C - -Slack: inf - Source: UART_RX - (input port) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.784ns (logic 1.590ns (27.483%) route 4.194ns (72.517%)) - Logic Levels: 2 (IBUF=1 LUT4=1) - Clock Path Skew: -1.930ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.930ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J20 0.000 0.000 r UART_RX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_RX_IOBUF_inst/IO - J20 IBUF (Prop_ibuf_I_O) 1.466 1.466 r UART_RX_IOBUF_inst/IBUF/O - net (fo=1, routed) 4.194 5.660 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_RX_IBUF - SLICE_X1Y61 LUT4 (Prop_lut4_I3_O) 0.124 5.784 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O - net (fo=1, routed) 0.000 5.784 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.898 -1.930 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Setup (Max at Slow Process Corner) - Data Path Delay: 5.395ns (logic 1.598ns (29.628%) route 3.796ns (70.372%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -1.932ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): -1.932ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 1.474 1.474 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 3.796 5.271 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF - SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.124 5.395 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O - net (fo=1, routed) 0.000 5.395 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.896 -1.932 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR - (recovery check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Recovery (Max at Slow Process Corner) - Data Path Delay: 4.648ns (logic 0.124ns (2.668%) route 4.524ns (97.332%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 3.378 3.378 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.124 3.502 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 1.146 4.648 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.736 -2.092 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - - - - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_hold_full.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_hold_full.rpt deleted file mode 100644 index 288f9a5..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/timing_summary_hold_full.rpt +++ /dev/null @@ -1,32214 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:11 2026 -| Host : fedora running 64-bit unknown -| Command : report_timing_summary -delay_type min -report_unconstrained -check_timing_verbose -max_paths 50 -file /home/fallensigh/vivado_reports_nodsp/timing_summary_hold_full.rpt -| Design : soc_top -| Device : 7a200t-fbg676 -| Speed File : -1 PRODUCTION 1.23 2018-06-13 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Timing Summary Report - ------------------------------------------------------------------------------------------------- -| Timer Settings -| -------------- ------------------------------------------------------------------------------------------------- - - Enable Multi Corner Analysis : Yes - Enable Pessimism Removal : Yes - Pessimism Removal Resolution : Nearest Common Node - Enable Input Delay Default Clock : No - Enable Preset / Clear Arcs : No - Disable Flight Delays : No - Ignore I/O Paths : No - Timing Early Launch at Borrowing Latches : No - Borrow Time for Max Delay Exceptions : Yes - Merge Timing Exceptions : Yes - - Corner Analyze Analyze - Name Max Paths Min Paths - ------ --------- --------- - Slow Yes Yes - Fast Yes Yes - - - -check_timing report - -Table of Contents ------------------ -1. checking no_clock -2. checking constant_clock -3. checking pulse_width_clock -4. checking unconstrained_internal_endpoints -5. checking no_input_delay -6. checking no_output_delay -7. checking multiple_clock -8. checking generated_clocks -9. checking loops -10. checking partial_input_delay -11. checking partial_output_delay -12. checking latch_loops - -1. checking no_clock --------------------- - There are 0 register/latch pins with no clock. - - -2. checking constant_clock --------------------------- - There are 0 register/latch pins with constant_clock. - - -3. checking pulse_width_clock ------------------------------ - There are 0 register/latch pins which need pulse_width check - - -4. checking unconstrained_internal_endpoints --------------------------------------------- - There are 0 pins that are not constrained for maximum delay. - - There are 0 pins that are not constrained for maximum delay due to constant clock. - - -5. checking no_input_delay --------------------------- - There are 38 input ports with no input delay specified. (HIGH) - -UART_RX -UART_TX -dip_sw[0] -dip_sw[10] -dip_sw[11] -dip_sw[12] -dip_sw[13] -dip_sw[14] -dip_sw[15] -dip_sw[16] -dip_sw[17] -dip_sw[18] -dip_sw[19] -dip_sw[1] -dip_sw[20] -dip_sw[21] -dip_sw[22] -dip_sw[23] -dip_sw[24] -dip_sw[25] -dip_sw[26] -dip_sw[27] -dip_sw[28] -dip_sw[29] -dip_sw[2] -dip_sw[30] -dip_sw[31] -dip_sw[3] -dip_sw[4] -dip_sw[5] -dip_sw[6] -dip_sw[7] -dip_sw[8] -dip_sw[9] -touch_btn[0] -touch_btn[1] -touch_btn[2] -touch_btn[3] - - There are 0 input ports with no input delay but user has a false path constraint. - - -6. checking no_output_delay ---------------------------- - There are 40 ports with no output delay specified. (HIGH) - -UART_RX -UART_TX -dpy0[0] -dpy0[1] -dpy0[2] -dpy0[3] -dpy0[4] -dpy0[5] -dpy0[6] -dpy0[7] -dpy1[0] -dpy1[1] -dpy1[2] -dpy1[3] -dpy1[4] -dpy1[5] -dpy1[6] -dpy1[7] -leds[0] -leds[10] -leds[11] -leds[12] -leds[13] -leds[14] -leds[15] -leds[1] -leds[2] -leds[3] -leds[4] -leds[5] -leds[6] -leds[7] -leds[8] -leds[9] -video_de -video_hsync -video_red[0] -video_red[1] -video_red[2] -video_vsync - - There are 0 ports with no output delay but user has a false path constraint - - There are 0 ports with no output delay but with a timing clock defined on it or propagating through it - - -7. checking multiple_clock --------------------------- - There are 0 register/latch pins with multiple clocks. - - -8. checking generated_clocks ----------------------------- - There are 0 generated clocks that are not connected to a clock source. - - -9. checking loops ------------------ - There are 0 combinational loops in the design. - - -10. checking partial_input_delay --------------------------------- - There are 0 input ports with partial input delay specified. - - -11. checking partial_output_delay ---------------------------------- - There are 0 ports with partial output delay specified. - - -12. checking latch_loops ------------------------- - There are 0 combinational latch loops in the design through latch input - - - ------------------------------------------------------------------------------------------------- -| Design Timing Summary -| --------------------- ------------------------------------------------------------------------------------------------- - - WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints - ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 0.032 0.000 0 115177 7.000 0.000 0 42610 - - -All user specified timing constraints are met. - - ------------------------------------------------------------------------------------------------- -| Clock Summary -| ------------- ------------------------------------------------------------------------------------------------- - -Clock Waveform(ns) Period(ns) Frequency(MHz) ------ ------------ ---------- -------------- -clk {0.000 10.000} 20.000 50.000 - clkfbout_clk_pll {0.000 10.000} 20.000 50.000 - cpu_clk {0.000 15.161} 30.323 32.979 - mlkem_clk_clk_pll {0.000 20.000} 40.000 25.000 - sys_clk {0.000 10.000} 20.000 50.000 - - ------------------------------------------------------------------------------------------------- -| Intra Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk 7.000 0.000 0 1 - clkfbout_clk_pll 17.845 0.000 0 3 - cpu_clk 0.049 0.000 0 17197 13.911 0.000 0 6486 - mlkem_clk_clk_pll 0.058 0.000 0 48474 18.750 0.000 0 26131 - sys_clk 0.079 0.000 0 22818 8.750 0.000 0 9989 - - ------------------------------------------------------------------------------------------------- -| Inter Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- -sys_clk mlkem_clk_clk_pll 0.054 0.000 0 108 -mlkem_clk_clk_pll sys_clk 0.032 0.000 0 59 - - ------------------------------------------------------------------------------------------------- -| Other Path Groups Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- ---------- -------- ------- ------- --------------------- ------------------- -**async_default** cpu_clk cpu_clk 0.651 0.000 0 67 -**async_default** mlkem_clk_clk_pll mlkem_clk_clk_pll 0.613 0.000 0 25694 -**async_default** sys_clk mlkem_clk_clk_pll 2.861 0.000 0 4 -**async_default** mlkem_clk_clk_pll sys_clk 2.991 0.000 0 2 -**async_default** sys_clk sys_clk 0.479 0.000 0 886 - - ------------------------------------------------------------------------------------------------- -| User Ignored Path Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock ----------- ---------- -------- -(none) sys_clk cpu_clk -(none) cpu_clk sys_clk - - ------------------------------------------------------------------------------------------------- -| Unconstrained Path Table -| ------------------------ ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock ----------- ---------- -------- -(none) clkfbout_clk_pll -(none) sys_clk -(none) sys_clk - - ------------------------------------------------------------------------------------------------- -| Timing Details -| -------------- ------------------------------------------------------------------------------------------------- - - ---------------------------------------------------------------------------------------------------- -From Clock: clk - To Clock: clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clk -Waveform(ns): { 0.000 10.000 } -Period(ns): 20.000 -Sources: { clk } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 -High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKIN1 - - - ---------------------------------------------------------------------------------------------------- -From Clock: clkfbout_clk_pll - To Clock: clkfbout_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA -PW : 0 Failing Endpoints, Worst Slack 17.845ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: clkfbout_clk_pll -Waveform(ns): { 0.000 10.000 } -Period(ns): 20.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y19 pll_clk.u_clk_pll/inst/clkf_buf/I -Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT -Min Period n/a PLLE2_ADV/CLKFBIN n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN -Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN -Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT - - - ---------------------------------------------------------------------------------------------------- -From Clock: cpu_clk - To Clock: cpu_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.049ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 13.911ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.049ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.454%) route 0.068ns (32.546%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[14]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[14]/Q - net (fo=4, routed) 0.068 -0.332 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIA0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA/CLK - clock pessimism -0.218 -0.528 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMA - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.332 - ------------------------------------------------------------------- - slack 0.049 - -Slack (MET) : 0.052ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP/CLK - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.052 - -Slack (MET) : 0.057ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.395ns (logic 0.141ns (35.653%) route 0.254ns (64.347%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.496ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.767 -0.496 u_cpu/axi_bridge/cpu_clk - SLICE_X17Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[10]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.355 r u_cpu/axi_bridge/awaddr_reg[10]/Q - net (fo=1, routed) 0.254 -0.100 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/DIC0 - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC/CLK - clock pessimism 0.037 -0.301 - SLICE_X16Y57 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.157 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMC - ------------------------------------------------------------------- - required time 0.157 - arrival time -0.100 - ------------------------------------------------------------------- - slack 0.057 - -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[0]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.155 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.155 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.061ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.221ns (logic 0.141ns (63.716%) route 0.080ns (36.284%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.273ns - Source Clock Delay (SCD): -0.507ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.756 -0.507 u_cpu/u_csr/cpu_clk - SLICE_X37Y38 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X37Y38 FDRE (Prop_fdre_C_Q) 0.141 -0.366 r u_cpu/u_csr/csr_tlbelo1_reg[20]/Q - net (fo=4, routed) 0.080 -0.285 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/DIA0 - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.035 -0.273 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/WCLK - SLICE_X36Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA/CLK - clock pessimism -0.221 -0.494 - SLICE_X36Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.347 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.285 - ------------------------------------------------------------------- - slack 0.061 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.209ns (logic 0.141ns (67.433%) route 0.068ns (32.567%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.219ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X43Y35 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[3]/Q - net (fo=7, routed) 0.068 -0.331 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/D - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.000 -0.308 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/WCLK - SLICE_X42Y35 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP/CLK - clock pessimism -0.219 -0.527 - SLICE_X42Y35 RAMD32 (Hold_ramd32_CLK_I) - 0.117 -0.410 u_cpu/addr_trans/tlb_entry/tlb_plv0_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.410 - arrival time -0.331 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.400ns (logic 0.141ns (35.262%) route 0.259ns (64.738%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X23Y49 FDRE r u_cpu/axi_bridge/awaddr_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X23Y49 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[1]/Q - net (fo=1, routed) 0.259 -0.097 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIA1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.182 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.182 - arrival time -0.097 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[14]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[14]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[14]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.306 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB - ------------------------------------------------------------------- - required time 0.306 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[26]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.037%) route 0.120ns (45.963%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[26]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[26]/Q - net (fo=4, routed) 0.120 -0.280 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA0 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA/CLK - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.379 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.280 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_cpu/axi_bridge/awaddr_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.422ns (logic 0.141ns (33.450%) route 0.281ns (66.550%)) - Logic Levels: 0 - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.497ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.766 -0.497 u_cpu/axi_bridge/cpu_clk - SLICE_X21Y48 FDRE r u_cpu/axi_bridge/awaddr_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X21Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.356 r u_cpu/axi_bridge/awaddr_reg[3]/Q - net (fo=1, routed) 0.281 -0.075 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/DIB1 - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.969 -0.339 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - clock pessimism 0.037 -0.302 - SLICE_X20Y58 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.178 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.178 - arrival time -0.075 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[1]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.263%) route 0.101ns (41.737%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[1]/Q - net (fo=1, routed) 0.101 -0.226 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA1 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.332 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.118ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.257ns (logic 0.141ns (54.812%) route 0.116ns (45.188%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X7Y48 FDRE r u_cpu/axi_bridge/wdata_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[15]/Q - net (fo=1, routed) 0.116 -0.210 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIB1 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.328 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMB_D1 - ------------------------------------------------------------------- - required time 0.328 - arrival time -0.210 - ------------------------------------------------------------------- - slack 0.118 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.369 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/SP - ------------------------------------------------------------------- - required time 0.369 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.076 -0.499 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.499 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.076 -0.476 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.476 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[10]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.281ns (logic 0.141ns (50.124%) route 0.140ns (49.876%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[10]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[10]/Q - net (fo=4, routed) 0.140 -0.258 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIB0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB/CLK - clock pessimism -0.217 -0.526 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMB - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.075 -0.477 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.477 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.553ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.709 -0.553 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.412 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.356 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.229 -0.553 - SLICE_X5Y75 FDCE (Hold_fdce_C_D) 0.075 -0.478 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.478 - arrival time -0.356 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.123ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.404%) route 0.139ns (49.596%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y34 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y34 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[12]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/DIC0 - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/WCLK - SLICE_X44Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC/CLK - clock pessimism -0.218 -0.527 - SLICE_X44Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.383 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.383 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.123 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[16]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.284ns (logic 0.141ns (49.682%) route 0.143ns (50.318%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo0_reg[16]/Q - net (fo=4, routed) 0.143 -0.257 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/DIB0 - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/WCLK - SLICE_X46Y34 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB/CLK - clock pessimism -0.217 -0.527 - SLICE_X46Y34 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.381 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_6_11/RAMB - ------------------------------------------------------------------- - required time 0.381 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[22]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.310ns (logic 0.141ns (45.479%) route 0.169ns (54.521%)) - Logic Levels: 0 - Clock Path Skew: 0.042ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.796 -0.467 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y47 FDRE r u_cpu/axi_bridge/wdata_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y47 FDRE (Prop_fdre_C_Q) 0.141 -0.326 r u_cpu/axi_bridge/wdata_reg[22]/Q - net (fo=1, routed) 0.169 -0.157 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/DIC0 - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/WCLK - SLICE_X2Y48 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC/CLK - clock pessimism -0.196 -0.425 - SLICE_X2Y48 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.281 u_Axi_CDC/wFifo/ram_reg_0_7_18_23/RAMC - ------------------------------------------------------------------- - required time 0.281 - arrival time -0.157 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[3]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.261ns (logic 0.141ns (54.075%) route 0.120ns (45.925%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[3]/Q - net (fo=7, routed) 0.120 -0.248 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r3_0_31_1_1/DP - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.378 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.575 - SLICE_X15Y69 FDCE (Hold_fdce_C_D) 0.071 -0.504 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.504 - arrival time -0.378 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.694 -0.568 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.230 -0.568 - SLICE_X19Y59 FDCE (Hold_fdce_C_D) 0.071 -0.497 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.323ns - Source Clock Delay (SCD): -0.552ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.710 -0.552 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y76 FDCE (Prop_fdce_C_Q) 0.141 -0.411 r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.355 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.985 -0.323 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.229 -0.552 - SLICE_X5Y76 FDCE (Hold_fdce_C_D) 0.071 -0.481 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.481 - arrival time -0.355 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.199ns (logic 0.141ns (70.953%) route 0.058ns (29.047%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.058 -0.266 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.071 -0.394 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.394 - arrival time -0.266 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[15]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.265ns (logic 0.141ns (53.167%) route 0.124ns (46.833%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.510ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.753 -0.510 u_cpu/u_csr/cpu_clk - SLICE_X41Y37 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X41Y37 FDRE (Prop_fdre_C_Q) 0.141 -0.369 r u_cpu/u_csr/csr_tlbelo1_reg[15]/Q - net (fo=4, routed) 0.124 -0.245 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/DIA1 - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/WCLK - SLICE_X40Y38 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y38 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.373 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_6_11/RAMA_D1 - ------------------------------------------------------------------- - required time 0.373 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[27]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.263ns (logic 0.141ns (53.571%) route 0.122ns (46.429%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.722 -0.541 u_cpu/u_csr/cpu_clk - SLICE_X47Y35 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[27]/C - ------------------------------------------------------------------- ------------------- - SLICE_X47Y35 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_cpu/u_csr/csr_tlbelo1_reg[27]/Q - net (fo=4, routed) 0.122 -0.278 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/DIA1 - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.999 -0.309 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/WCLK - SLICE_X46Y36 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1/CLK - clock pessimism -0.217 -0.526 - SLICE_X46Y36 RAMD32 (Hold_ramd32_CLK_I) - 0.120 -0.406 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r1_0_31_18_19/RAMA_D1 - ------------------------------------------------------------------- - required time 0.406 - arrival time -0.278 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.141 -0.434 r u_Axi_CDC/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.065 -0.369 u_Axi_CDC/bFifo/bufferCC_12/buffers_0 - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.963 -0.345 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.230 -0.575 - SLICE_X30Y58 FDCE (Hold_fdce_C_D) 0.075 -0.500 u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.369 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.206ns (logic 0.141ns (68.336%) route 0.065ns (31.664%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.065 -0.258 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.236 -0.465 - SLICE_X0Y49 FDCE (Hold_fdce_C_D) 0.075 -0.390 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.390 - arrival time -0.258 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[20]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.141ns (47.970%) route 0.153ns (52.030%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.542ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.721 -0.542 u_cpu/u_csr/cpu_clk - SLICE_X43Y32 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X43Y32 FDRE (Prop_fdre_C_Q) 0.141 -0.401 r u_cpu/u_csr/csr_tlbelo0_reg[20]/Q - net (fo=4, routed) 0.153 -0.248 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/DIA0 - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.998 -0.310 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/WCLK - SLICE_X42Y33 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA/CLK - clock pessimism -0.217 -0.527 - SLICE_X42Y33 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.380 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r3_0_31_12_17/RAMA - ------------------------------------------------------------------- - required time 0.380 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.296ns (logic 0.141ns (47.613%) route 0.155ns (52.387%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[0]/Q - net (fo=1, routed) 0.155 -0.172 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/DIA0 - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/WCLK - SLICE_X6Y45 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y45 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_0_5/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.172 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.264ns (logic 0.141ns (53.394%) route 0.123ns (46.606%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.275ns - Source Clock Delay (SCD): -0.509ns - Clock Pessimism Removal (CPR): 0.218ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.754 -0.509 u_cpu/u_csr/cpu_clk - SLICE_X39Y39 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X39Y39 FDRE (Prop_fdre_C_Q) 0.141 -0.368 r u_cpu/u_csr/csr_tlbelo1_reg[2]/Q - net (fo=7, routed) 0.123 -0.245 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/D - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.033 -0.275 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/WCLK - SLICE_X40Y39 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP/CLK - clock pessimism -0.218 -0.493 - SLICE_X40Y39 RAMD32 (Hold_ramd32_CLK_I) - 0.114 -0.379 u_cpu/addr_trans/tlb_entry/tlb_plv1_reg_r2_0_31_0_0/DP - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.245 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[2]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.469ns (logic 0.141ns (30.053%) route 0.328ns (69.947%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk - SLICE_X28Y48 FDRE r u_cpu/axi_bridge/araddr_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[2]/Q - net (fo=1, routed) 0.328 -0.031 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIB0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.165 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB - ------------------------------------------------------------------- - required time 0.165 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.135ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.298ns (logic 0.141ns (47.334%) route 0.157ns (52.666%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/axi_bridge/cpu_clk - SLICE_X5Y45 FDRE r u_cpu/axi_bridge/wdata_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y45 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/axi_bridge/wdata_reg[12]/Q - net (fo=1, routed) 0.157 -0.170 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/DIA0 - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/WCLK - SLICE_X6Y46 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA/CLK - clock pessimism -0.220 -0.452 - SLICE_X6Y46 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.305 u_Axi_CDC/wFifo/ram_reg_0_7_12_17/RAMA - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.170 - ------------------------------------------------------------------- - slack 0.135 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[12]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.164ns (55.832%) route 0.130ns (44.168%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk - SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[12]/Q - net (fo=4, routed) 0.130 -0.249 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIC0 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC/CLK - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.144 -0.385 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMC - ------------------------------------------------------------------- - required time 0.385 - arrival time -0.249 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_cpu/axi_bridge/araddr_reg[0]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.472ns (logic 0.141ns (29.890%) route 0.331ns (70.110%)) - Logic Levels: 0 - Clock Path Skew: 0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.500ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.763 -0.500 u_cpu/axi_bridge/cpu_clk - SLICE_X29Y48 FDRE r u_cpu/axi_bridge/araddr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X29Y48 FDRE (Prop_fdre_C_Q) 0.141 -0.359 r u_cpu/axi_bridge/araddr_reg[0]/Q - net (fo=1, routed) 0.331 -0.028 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/DIA0 - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.960 -0.348 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA/CLK - clock pessimism 0.037 -0.311 - SLICE_X36Y59 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.164 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMA - ------------------------------------------------------------------- - required time 0.164 - arrival time -0.028 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo1_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.275ns (logic 0.164ns (59.651%) route 0.111ns (40.349%)) - Logic Levels: 0 - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.720 -0.543 u_cpu/u_csr/cpu_clk - SLICE_X48Y32 FDRE r u_cpu/u_csr/csr_tlbelo1_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X48Y32 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_cpu/u_csr/csr_tlbelo1_reg[11]/Q - net (fo=4, routed) 0.111 -0.268 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/DIB1 - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.996 -0.312 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/WCLK - SLICE_X46Y32 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1/CLK - clock pessimism -0.217 -0.529 - SLICE_X46Y32 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.405 u_cpu/addr_trans/tlb_entry/tlb_ppn1_reg_r3_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.405 - arrival time -0.268 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_cpu/axi_bridge/wdata_reg[28]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.128ns (52.542%) route 0.116ns (47.458%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_cpu/axi_bridge/cpu_clk - SLICE_X3Y48 FDRE r u_cpu/axi_bridge/wdata_reg[28]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y48 FDRE (Prop_fdre_C_Q) 0.128 -0.337 r u_cpu/axi_bridge/wdata_reg[28]/Q - net (fo=1, routed) 0.116 -0.221 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/DIC0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC/CLK - clock pessimism -0.220 -0.449 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_I) - 0.090 -0.359 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMC - ------------------------------------------------------------------- - required time 0.359 - arrival time -0.221 - ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_cpu/icache/lfsr/r_lfsr_reg[6]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/icache/lfsr/r_lfsr_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.210ns (logic 0.141ns (67.004%) route 0.069ns (32.996%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.232ns - Source Clock Delay (SCD): -0.468ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.795 -0.468 u_cpu/icache/lfsr/cpu_clk - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y43 FDRE (Prop_fdre_C_Q) 0.141 -0.327 r u_cpu/icache/lfsr/r_lfsr_reg[6]/Q - net (fo=2, routed) 0.069 -0.257 u_cpu/icache/lfsr/Q[0] - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.076 -0.232 u_cpu/icache/lfsr/cpu_clk - SLICE_X5Y43 FDRE r u_cpu/icache/lfsr/r_lfsr_reg[7]/C - clock pessimism -0.236 -0.468 - SLICE_X5Y43 FDRE (Hold_fdre_C_D) 0.071 -0.397 u_cpu/icache/lfsr/r_lfsr_reg[7] - ------------------------------------------------------------------- - required time 0.397 - arrival time -0.257 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/u_csr/csr_tlbelo0_reg[11]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.280ns (logic 0.141ns (50.435%) route 0.139ns (49.565%)) - Logic Levels: 0 - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.540ns - Clock Pessimism Removal (CPR): 0.217ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.723 -0.540 u_cpu/u_csr/cpu_clk - SLICE_X45Y36 FDRE r u_cpu/u_csr/csr_tlbelo0_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X45Y36 FDRE (Prop_fdre_C_Q) 0.141 -0.399 r u_cpu/u_csr/csr_tlbelo0_reg[11]/Q - net (fo=4, routed) 0.139 -0.260 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/DIB1 - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/I - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/WCLK - SLICE_X44Y37 RAMD32 r u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1/CLK - clock pessimism -0.217 -0.524 - SLICE_X44Y37 RAMD32 (Hold_ramd32_CLK_I) - 0.124 -0.400 u_cpu/addr_trans/tlb_entry/tlb_ppn0_reg_r1_0_31_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.400 - arrival time -0.260 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.330%) route 0.059ns (29.670%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.268ns - Source Clock Delay (SCD): -0.502ns - Clock Pessimism Removal (CPR): 0.221ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.761 -0.502 u_cpu/wb_stage/cpu_clk - SLICE_X31Y41 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y41 FDRE (Prop_fdre_C_Q) 0.141 -0.361 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[238]/Q - net (fo=1, routed) 0.059 -0.301 u_cpu/u_csr/ws_lladdr[16] - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.040 -0.268 u_cpu/u_csr/cpu_clk - SLICE_X30Y41 FDRE r u_cpu/u_csr/lladdr_reg[16]/C - clock pessimism -0.221 -0.489 - SLICE_X30Y41 FDRE (Hold_fdre_C_D) 0.047 -0.442 u_cpu/u_csr/lladdr_reg[16] - ------------------------------------------------------------------- - required time 0.442 - arrival time -0.301 - ------------------------------------------------------------------- - slack 0.140 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/u_csr/lladdr_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.260ns (logic 0.141ns (54.241%) route 0.119ns (45.759%)) - Logic Levels: 0 - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.269ns - Source Clock Delay (SCD): -0.504ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.759 -0.504 u_cpu/wb_stage/cpu_clk - SLICE_X32Y40 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/C - ------------------------------------------------------------------- ------------------- - SLICE_X32Y40 FDRE (Prop_fdre_C_Q) 0.141 -0.363 r u_cpu/wb_stage/ms_to_ws_bus_r_reg[231]/Q - net (fo=1, routed) 0.119 -0.244 u_cpu/u_csr/ws_lladdr[9] - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.039 -0.269 u_cpu/u_csr/cpu_clk - SLICE_X31Y39 FDRE r u_cpu/u_csr/lladdr_reg[9]/C - clock pessimism -0.196 -0.465 - SLICE_X31Y39 FDRE (Hold_fdre_C_D) 0.078 -0.387 u_cpu/u_csr/lladdr_reg[9] - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.244 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.254ns (logic 0.141ns (55.548%) route 0.113ns (44.452%)) - Logic Levels: 0 - Clock Path Skew: 0.035ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.282ns - Source Clock Delay (SCD): -0.513ns - Clock Pessimism Removal (CPR): 0.196ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.750 -0.513 u_cpu/mem_stage/cpu_clk - SLICE_X27Y26 FDRE r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y26 FDRE (Prop_fdre_C_Q) 0.141 -0.372 r u_cpu/mem_stage/es_to_ms_bus_r_reg[89]/Q - net (fo=1, routed) 0.113 -0.259 u_cpu/wb_stage/ms_to_ws_bus[46] - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.026 -0.282 u_cpu/wb_stage/cpu_clk - SLICE_X28Y26 FDRE r u_cpu/wb_stage/ms_to_ws_bus_r_reg[82]/C - clock pessimism -0.196 -0.478 - SLICE_X28Y26 FDRE (Hold_fdre_C_D) 0.071 -0.407 u_cpu/wb_stage/ms_to_ws_bus_r_reg[82] - ------------------------------------------------------------------- - required time 0.407 - arrival time -0.259 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMA_D1 - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: cpu_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.471ns (logic 0.141ns (29.919%) route 0.330ns (70.081%)) - Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.223ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/Q - net (fo=62, routed) 0.330 0.007 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/ADDRD0 - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/WCLK - SLICE_X2Y49 RAMD32 r u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB/CLK - clock pessimism -0.223 -0.452 - SLICE_X2Y49 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.142 u_Axi_CDC/wFifo/ram_reg_0_7_24_29/RAMB - ------------------------------------------------------------------- - required time 0.142 - arrival time 0.007 - ------------------------------------------------------------------- - slack 0.148 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: cpu_clk -Waveform(ns): { 0.000 15.161 } -Period(ns): 30.323 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y14 u_cpu/dcache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y16 u_cpu/dcache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y15 u_cpu/dcache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y10 u_cpu/dcache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y17 u_cpu/dcache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y13 u_cpu/dcache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y11 u_cpu/dcache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X0Y12 u_cpu/dcache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y2 u_cpu/icache/data_ram_way[0].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y3 u_cpu/icache/data_ram_way[0].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y0 u_cpu/icache/data_ram_way[0].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X1Y1 u_cpu/icache/data_ram_way[0].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y2 u_cpu/icache/data_ram_way[1].data_ram_bank[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y1 u_cpu/icache/data_ram_way[1].data_ram_bank[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y3 u_cpu/icache/data_ram_way[1].data_ram_bank[2].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 30.323 27.379 RAMB18_X2Y0 u_cpu/icache/data_ram_way[1].data_ram_bank[3].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y18 u_cpu/dcache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X1Y16 u_cpu/dcache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y12 u_cpu/icache/tagv_ram_way[0].u/mem_reg_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 30.323 27.747 RAMB18_X2Y13 u_cpu/icache/tagv_ram_way[1].u/mem_reg_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 30.323 28.167 BUFGCTRL_X0Y18 pll_clk.u_clk_pll/inst/clkout1_buf/I -Min Period n/a PLLE2_ADV/CLKOUT0 n/a 1.249 30.323 29.074 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 30.323 29.323 SLICE_X0Y48 pll_clk.u_rst_cpu/delay_reg[1]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y5 u_cpu/btb/btb_untaken_entry_r_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X46Y6 u_cpu/btb/btb_untaken_entry_r_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y8 u_cpu/btb/btb_untaken_entry_r_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X48Y4 u_cpu/btb/btb_untaken_entry_r_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X50Y5 u_cpu/btb/btb_untaken_entry_r_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 30.323 29.323 SLICE_X49Y9 u_cpu/btb/btb_untaken_entry_r_reg[14]/C -Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 30.323 129.677 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y12 u_cpu/btb/btb_target_reg_0_31_12_13/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y15 u_cpu/btb/ras_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y60 u_Axi_CDC/arFifo/ram_reg_0_3_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X20Y58 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y10 u_cpu/btb/btb_target_reg_0_31_10_11/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y13 u_cpu/btb/btb_target_reg_0_31_14_15/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y9 u_cpu/btb/btb_target_reg_0_31_16_17/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X40Y8 u_cpu/btb/btb_target_reg_0_31_18_19/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y12 u_cpu/btb/btb_target_reg_0_31_20_21/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 15.161 13.911 SLICE_X36Y10 u_cpu/btb/btb_target_reg_0_31_24_25/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 15.161 13.911 SLICE_X42Y11 u_cpu/btb/btb_target_reg_0_31_26_27/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.058ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 18.750ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.058ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.247ns (55.601%) route 0.197ns (44.399%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.695ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.568 -0.695 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y144 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y144 FDRE (Prop_fdre_C_Q) 0.148 -0.547 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3/Q - net (fo=1, routed) 0.197 -0.350 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[5]_u_fft_mlkem_axi_slave_u_mlkem_axi_slave_u_mlkem_u_ntt_u_scl_valid_sr_reg_c_3_n_0 - SLICE_X84Y151 LUT2 (Prop_lut2_I0_O) 0.099 -0.251 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate/O - net (fo=1, routed) 0.000 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg_gate_n_0 - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.833 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6]/C - clock pessimism 0.045 -0.430 - SLICE_X84Y151 FDCE (Hold_fdce_C_D) 0.121 -0.309 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/valid_sr_reg[6] - ------------------------------------------------------------------- - required time 0.309 - arrival time -0.251 - ------------------------------------------------------------------- - slack 0.058 - -Slack (MET) : 0.077ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.446ns (logic 0.186ns (41.734%) route 0.260ns (58.266%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.277ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X86Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r_reg[2]/Q - net (fo=234, routed) 0.260 -0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_b_data_r[2] - SLICE_X86Y148 LUT6 (Prop_lut6_I0_O) 0.045 -0.255 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1/O - net (fo=1, routed) 0.000 -0.255 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[241][2]_i_1_n_0 - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2]/C - clock pessimism 0.045 -0.424 - SLICE_X86Y148 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[241][2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.255 - ------------------------------------------------------------------- - slack 0.077 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.453ns (logic 0.186ns (41.036%) route 0.267ns (58.964%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.278ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.439ns - Source Clock Delay (SCD): -0.672ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.591 -0.672 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X138Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/C - ------------------------------------------------------------------- ------------------- - SLICE_X138Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.531 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5/Q - net (fo=127, routed) 0.267 -0.264 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_valid_r_reg_rep__5_n_0 - SLICE_X137Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.219 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1/O - net (fo=1, routed) 0.000 -0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[130][5]_i_1_n_0 - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.869 -0.439 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X137Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5]/C - clock pessimism 0.045 -0.394 - SLICE_X137Y147 FDCE (Hold_fdce_C_D) 0.092 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[130][5] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.219 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.094ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.256ns (55.346%) route 0.207ns (44.654%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[0] - net (fo=1, routed) 0.000 -0.238 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[0] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[0] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.238 - ------------------------------------------------------------------- - slack 0.094 - -Slack (MET) : 0.095ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.416ns (logic 0.141ns (33.875%) route 0.275ns (66.125%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.464ns - Source Clock Delay (SCD): -0.683ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.580 -0.683 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X73Y148 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X73Y148 FDCE (Prop_fdce_C_Q) 0.141 -0.542 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s1_reg[16]/Q - net (fo=14, routed) 0.275 -0.267 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/Q[16] - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.844 -0.464 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X73Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16]/C - clock pessimism 0.045 -0.419 - SLICE_X73Y154 FDCE (Hold_fdce_C_D) 0.057 -0.362 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s2_reg[16] - ------------------------------------------------------------------- - required time 0.362 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.095 - -Slack (MET) : 0.099ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.252ns (53.610%) route 0.218ns (46.390%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[2] - net (fo=1, routed) 0.000 -0.233 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[2] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2]/C - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[2] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.233 - ------------------------------------------------------------------- - slack 0.099 - -Slack (MET) : 0.105ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.502ns (logic 0.185ns (36.874%) route 0.317ns (63.126%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X83Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[5]/Q - net (fo=4, routed) 0.317 -0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[5] - SLICE_X84Y155 LUT3 (Prop_lut3_I0_O) 0.044 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1/O - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[5]_i_1_n_0 - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y155 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.105 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[10]/Q - net (fo=1, routed) 0.200 -0.336 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[10] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.291 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3/O - net (fo=1, routed) 0.000 -0.291 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_3_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.225 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[2] - net (fo=1, routed) 0.000 -0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[10] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[10] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.225 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[14] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_3_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[14] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[14] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[18]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[18] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_3_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[18] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[18] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.475ns (logic 0.275ns (57.843%) route 0.200ns (42.157%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[22]/Q - net (fo=1, routed) 0.200 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[22] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_3_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.066 -0.226 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[2] - net (fo=1, routed) 0.000 -0.226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[22] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[22] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.226 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.107ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.186ns (36.603%) route 0.322ns (63.397%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.280ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.458ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[8]/Q - net (fo=234, routed) 0.322 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[8] - SLICE_X90Y147 LUT6 (Prop_lut6_I3_O) 0.045 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1/O - net (fo=1, routed) 0.000 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][8]_i_1_n_0 - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.850 -0.458 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X90Y147 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8]/C - clock pessimism 0.045 -0.413 - SLICE_X90Y147 FDCE (Hold_fdce_C_D) 0.121 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][8] - ------------------------------------------------------------------- - required time 0.292 - arrival time -0.185 - ------------------------------------------------------------------- - slack 0.107 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT1=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.479ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y160 FDCE (Prop_fdce_C_Q) 0.164 -0.539 f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[24]/Q - net (fo=1, routed) 0.199 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[24] - SLICE_X83Y160 LUT1 (Prop_lut1_I0_O) 0.045 -0.294 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2/O - net (fo=1, routed) 0.000 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[24]_i_2_n_0 - SLICE_X83Y160 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.224 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]_i_1/O[0] - net (fo=1, routed) 0.000 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[24] - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.829 -0.479 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24]/C - clock pessimism 0.040 -0.439 - SLICE_X83Y160 FDCE (Hold_fdce_C_D) 0.105 -0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[24] - ------------------------------------------------------------------- - required time 0.334 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[12] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_5_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[12] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[12] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[16]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[16] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_5_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[16] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[16] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[20]/Q - net (fo=1, routed) 0.199 -0.338 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[20] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.293 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5/O - net (fo=1, routed) 0.000 -0.293 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_5_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.223 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[0] - net (fo=1, routed) 0.000 -0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[20] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[20] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.223 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.110ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.279ns (58.317%) route 0.199ns (41.683%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[8]/Q - net (fo=1, routed) 0.199 -0.337 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[8] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.292 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5/O - net (fo=1, routed) 0.000 -0.292 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_5_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.222 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[0] - net (fo=1, routed) 0.000 -0.222 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[8] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[8] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.222 - ------------------------------------------------------------------- - slack 0.110 - -Slack (MET) : 0.111ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.510ns (logic 0.256ns (50.190%) route 0.254ns (49.810%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q - net (fo=7, routed) 0.254 -0.307 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10] - SLICE_X84Y157 LUT4 (Prop_lut4_I3_O) 0.045 -0.262 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_9/O - net (fo=1, routed) 0.000 -0.262 u_fft_mlkem_axi_slave_n_123 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[0]_O[0]) - 0.070 -0.192 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[0] - net (fo=1, routed) 0.000 -0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[4] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[12] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.192 - ------------------------------------------------------------------- - slack 0.111 - -Slack (MET) : 0.114ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.557ns (logic 0.234ns (42.015%) route 0.323ns (57.985%)) - Logic Levels: 2 (LUT3=1 LUT6=1) - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.398ns - Source Clock Delay (SCD): -0.694ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/mlkem_clk - SLICE_X79Y101 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/C - ------------------------------------------------------------------- ------------------- - SLICE_X79Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/squeeze_state_r_reg[445]/Q - net (fo=2, routed) 0.169 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/data18[13] - SLICE_X81Y99 LUT6 (Prop_lut6_I0_O) 0.045 -0.339 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_snt/state_r[445]_i_2/O - net (fo=1, routed) 0.154 -0.185 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/kc_state_i_mux[185] - SLICE_X81Y99 LUT3 (Prop_lut3_I1_O) 0.048 -0.137 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r[445]_i_1/O - net (fo=1, routed) 0.000 -0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/p_1_in[445] - SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.910 -0.398 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/mlkem_clk - SLICE_X81Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445]/C - clock pessimism 0.040 -0.358 - SLICE_X81Y99 FDCE (Hold_fdce_C_D) 0.107 -0.251 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_keccak/state_r_reg[445] - ------------------------------------------------------------------- - required time 0.251 - arrival time -0.137 - ------------------------------------------------------------------- - slack 0.114 - -Slack (MET) : 0.115ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.518ns (logic 0.186ns (35.884%) route 0.332ns (64.116%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.282ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.456ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[4]/Q - net (fo=234, routed) 0.332 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[4] - SLICE_X92Y145 LUT6 (Prop_lut6_I3_O) 0.045 -0.175 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1/O - net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[240][4]_i_1_n_0 - SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X92Y145 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4]/C - clock pessimism 0.045 -0.411 - SLICE_X92Y145 FDCE (Hold_fdce_C_D) 0.121 -0.290 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[240][4] - ------------------------------------------------------------------- - required time 0.290 - arrival time -0.175 - ------------------------------------------------------------------- - slack 0.115 - -Slack (MET) : 0.116ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.474ns (logic 0.226ns (47.682%) route 0.248ns (52.318%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.704ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.559 -0.704 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X81Y162 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X81Y162 FDCE (Prop_fdce_C_Q) 0.128 -0.576 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg[6]/Q - net (fo=4, routed) 0.248 -0.328 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r1_s6_reg_n_0_[6] - SLICE_X87Y160 LUT3 (Prop_lut3_I0_O) 0.098 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0/O - net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r[6]_i_1__0_n_0 - SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X87Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6]/C - clock pessimism 0.040 -0.438 - SLICE_X87Y160 FDCE (Hold_fdce_C_D) 0.092 -0.346 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/product_r_reg[6] - ------------------------------------------------------------------- - required time 0.346 - arrival time -0.230 - ------------------------------------------------------------------- - slack 0.116 - -Slack (MET) : 0.120ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.519ns (logic 0.252ns (48.552%) route 0.267ns (51.448%)) - Logic Levels: 2 (CARRY4=1 LUT5=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]/Q - net (fo=7, routed) 0.267 -0.294 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[10] - SLICE_X84Y157 LUT5 (Prop_lut5_I0_O) 0.045 -0.249 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_8/O - net (fo=1, routed) 0.000 -0.249 u_fft_mlkem_axi_slave_n_122 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[1]_O[1]) - 0.066 -0.183 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[1] - net (fo=1, routed) 0.000 -0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[5] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[13] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.183 - ------------------------------------------------------------------- - slack 0.120 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.076 -0.505 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.505 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0 - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.228 -0.581 - SLICE_X25Y79 FDCE (Hold_fdce_C_D) 0.075 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.226 -0.615 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.540 - arrival time -0.418 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.614ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.226 -0.614 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.075 -0.539 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.539 - arrival time -0.417 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.521ns (logic 0.273ns (52.394%) route 0.248ns (47.606%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X80Y155 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[3]/Q - net (fo=6, routed) 0.248 -0.289 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[3] - SLICE_X84Y156 LUT4 (Prop_lut4_I1_O) 0.045 -0.244 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11]_i_5/O - net (fo=1, routed) 0.000 -0.244 u_fft_mlkem_axi_slave_n_417 - SLICE_X84Y156 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.064 -0.180 r u_bf/u_barrett/qprod_s4_reg[11]_i_1/O[3] - net (fo=1, routed) 0.000 -0.180 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[3] - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y156 FDCE (Hold_fdce_C_D) 0.134 -0.302 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11] - ------------------------------------------------------------------- - required time 0.302 - arrival time -0.180 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y156 FDCE (Prop_fdce_C_Q) 0.164 -0.537 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[11]/Q - net (fo=1, routed) 0.222 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[11] - SLICE_X83Y156 LUT2 (Prop_lut2_I1_O) 0.045 -0.269 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2/O - net (fo=1, routed) 0.000 -0.269 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[11]_i_2_n_0 - SLICE_X83Y156 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.206 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]_i_1/O[3] - net (fo=1, routed) 0.000 -0.206 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[11] - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y156 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[11] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.206 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y157 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[15]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15] - SLICE_X83Y157 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[15]_i_2_n_0 - SLICE_X83Y157 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[15] - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y157 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[15] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y158 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19] - SLICE_X83Y158 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[19]_i_2_n_0 - SLICE_X83Y158 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[19] - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y158 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[19] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.494ns (logic 0.272ns (55.014%) route 0.222ns (44.986%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y159 FDCE (Prop_fdce_C_Q) 0.164 -0.538 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]/Q - net (fo=1, routed) 0.222 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[23] - SLICE_X83Y159 LUT2 (Prop_lut2_I1_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2/O - net (fo=1, routed) 0.000 -0.270 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[23]_i_2_n_0 - SLICE_X83Y159 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.063 -0.207 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]_i_1/O[3] - net (fo=1, routed) 0.000 -0.207 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[23] - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23]/C - clock pessimism 0.040 -0.438 - SLICE_X83Y159 FDCE (Hold_fdce_C_D) 0.105 -0.333 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[23] - ------------------------------------------------------------------- - required time 0.333 - arrival time -0.207 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.440 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.384 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.581 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.071 -0.510 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.510 - arrival time -0.384 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.227 -0.582 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.071 -0.511 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.511 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X115Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.226 -0.615 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.071 -0.544 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.544 - arrival time -0.418 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.614ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.648 -0.614 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.473 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.056 -0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.226 -0.614 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.071 -0.543 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.543 - arrival time -0.417 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.527ns (logic 0.251ns (47.592%) route 0.276ns (52.408%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y157 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[5]/Q - net (fo=7, routed) 0.276 -0.285 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[12]_0[5] - SLICE_X84Y157 LUT4 (Prop_lut4_I0_O) 0.045 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[15]_i_7/O - net (fo=1, routed) 0.000 -0.240 u_fft_mlkem_axi_slave_n_121 - SLICE_X84Y157 CARRY4 (Prop_carry4_S[2]_O[2]) - 0.065 -0.175 r u_bf/u_barrett/qprod_s4_reg[15]_i_1/O[2] - net (fo=1, routed) 0.000 -0.175 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[6] - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y157 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y157 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[14] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.175 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.129ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.526ns (logic 0.185ns (35.176%) route 0.341ns (64.824%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X83Y154 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/Q - net (fo=4, routed) 0.341 -0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[1] - SLICE_X84Y154 LUT3 (Prop_lut3_I0_O) 0.044 -0.176 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1/O - net (fo=1, routed) 0.000 -0.176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6[1]_i_1_n_0 - SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1]/C - clock pessimism 0.040 -0.436 - SLICE_X84Y154 FDCE (Hold_fdce_C_D) 0.131 -0.305 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[1] - ------------------------------------------------------------------- - required time 0.305 - arrival time -0.176 - ------------------------------------------------------------------- - slack 0.129 - -Slack (MET) : 0.130ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.499ns (logic 0.292ns (58.570%) route 0.207ns (41.430%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X85Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.560 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[0]/Q - net (fo=1, routed) 0.207 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[0] - SLICE_X83Y154 LUT2 (Prop_lut2_I1_O) 0.045 -0.308 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5/O - net (fo=1, routed) 0.000 -0.308 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5[3]_i_5_n_0 - SLICE_X83Y154 CARRY4 (Prop_carry4_S[0]_O[1]) - 0.106 -0.202 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[3]_i_1/O[1] - net (fo=1, routed) 0.000 -0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s50[1] - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X83Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1]/C - clock pessimism 0.040 -0.437 - SLICE_X83Y154 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r0_s5_reg[1] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.202 - ------------------------------------------------------------------- - slack 0.130 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.531ns (logic 0.186ns (35.046%) route 0.345ns (64.954%)) - Logic Levels: 1 (LUT2=1) - Clock Path Skew: 0.337ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns - Source Clock Delay (SCD): -0.612ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.651 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/mlkem_clk - SLICE_X161Y100 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/C - ------------------------------------------------------------------- ------------------- - SLICE_X161Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.471 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r_reg[352]/Q - net (fo=1, routed) 0.156 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/squeezed_state_r[352] - SLICE_X161Y100 LUT2 (Prop_lut2_I0_O) 0.045 -0.270 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_sha3/r_r[96]_i_1/O - net (fo=2, routed) 0.189 -0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/sha3_hash[352] - SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.993 -0.315 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/mlkem_clk - SLICE_X158Y99 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96]/C - clock pessimism 0.040 -0.275 - SLICE_X158Y99 FDCE (Hold_fdce_C_D) 0.063 -0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/r_r_reg[96] - ------------------------------------------------------------------- - required time 0.212 - arrival time -0.081 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.478ns (logic 0.164ns (34.335%) route 0.314ns (65.665%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.475ns - Source Clock Delay (SCD): -0.694ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.569 -0.694 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X80Y149 FDCE (Prop_fdce_C_Q) 0.164 -0.530 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3_reg[5]/Q - net (fo=1, routed) 0.314 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s3[5] - SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.832 -0.475 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X80Y154 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5]/C - clock pessimism 0.045 -0.430 - SLICE_X80Y154 FDCE (Hold_fdce_C_D) 0.083 -0.347 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/p_s4_reg[5] - ------------------------------------------------------------------- - required time 0.347 - arrival time -0.216 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.131ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.454ns (logic 0.141ns (31.069%) route 0.313ns (68.931%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.478ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y159 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[0]/Q - net (fo=1, routed) 0.313 -0.248 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[0] - SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.830 -0.478 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X82Y159 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0]/C - clock pessimism 0.040 -0.438 - SLICE_X82Y159 FDCE (Hold_fdce_C_D) 0.059 -0.379 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[0] - ------------------------------------------------------------------- - required time 0.379 - arrival time -0.248 - ------------------------------------------------------------------- - slack 0.131 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.504ns (logic 0.249ns (49.413%) route 0.255ns (50.587%)) - Logic Levels: 1 (LUT3=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.476ns - Source Clock Delay (SCD): -0.701ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.562 -0.701 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X84Y155 FDCE (Prop_fdce_C_Q) 0.148 -0.553 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg[5]/Q - net (fo=4, routed) 0.255 -0.298 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/r1_s6_reg_n_0_[5] - SLICE_X82Y151 LUT3 (Prop_lut3_I0_O) 0.101 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1/O - net (fo=1, routed) 0.000 -0.197 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r[5]_i_1_n_0 - SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.832 -0.476 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y151 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5]/C - clock pessimism 0.040 -0.436 - SLICE_X82Y151 FDCE (Hold_fdce_C_D) 0.107 -0.329 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/product_r_reg[5] - ------------------------------------------------------------------- - required time 0.329 - arrival time -0.197 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.132ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.503ns (logic 0.285ns (56.653%) route 0.218ns (43.347%)) - Logic Levels: 2 (CARRY4=1 LUT2=1) - Clock Path Skew: 0.266ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.703ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.560 -0.703 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X85Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X85Y160 FDCE (Prop_fdce_C_Q) 0.141 -0.562 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[2]/Q - net (fo=2, routed) 0.218 -0.344 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4[2] - SLICE_X79Y160 LUT2 (Prop_lut2_I0_O) 0.045 -0.299 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0/O - net (fo=1, routed) 0.000 -0.299 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5[3]_i_3__0_n_0 - SLICE_X79Y160 CARRY4 (Prop_carry4_S[2]_O[3]) - 0.099 -0.200 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]_i_1__0/O[3] - net (fo=1, routed) 0.000 -0.200 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s50[3] - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X79Y160 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3]/C - clock pessimism 0.040 -0.437 - SLICE_X79Y160 FDCE (Hold_fdce_C_D) 0.105 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/r0_s5_reg[3] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.200 - ------------------------------------------------------------------- - slack 0.132 - -Slack (MET) : 0.133ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.480ns (logic 0.141ns (29.345%) route 0.339ns (70.655%)) - Logic Levels: 0 - Clock Path Skew: 0.264ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.481ns - Source Clock Delay (SCD): -0.705ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.558 -0.705 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X87Y164 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/C - ------------------------------------------------------------------- ------------------- - SLICE_X87Y164 FDCE (Prop_fdce_C_Q) 0.141 -0.564 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3_reg[20]/Q - net (fo=1, routed) 0.339 -0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s3[20] - SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.826 -0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/mlkem_clk - SLICE_X80Y165 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20]/C - clock pessimism 0.040 -0.441 - SLICE_X80Y165 FDCE (Hold_fdce_C_D) 0.084 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_scl/p_s4_reg[20] - ------------------------------------------------------------------- - required time 0.357 - arrival time -0.224 - ------------------------------------------------------------------- - slack 0.133 - -Slack (MET) : 0.136ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.240ns (logic 0.186ns (77.515%) route 0.054ns (22.485%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.456ns - Source Clock Delay (SCD): -0.681ns - Clock Pessimism Removal (CPR): 0.212ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.582 -0.681 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk - SLICE_X58Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X58Y137 FDCE (Prop_fdce_C_Q) 0.141 -0.540 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5_reg[11]/Q - net (fo=1, routed) 0.054 -0.486 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/decomp_result_s5[11] - SLICE_X59Y137 LUT5 (Prop_lut5_I0_O) 0.045 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1/O - net (fo=1, routed) 0.000 -0.441 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r[11]_i_1_n_0 - SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.852 -0.456 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/mlkem_clk - SLICE_X59Y137 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11]/C - clock pessimism -0.212 -0.668 - SLICE_X59Y137 FDCE (Hold_fdce_C_D) 0.091 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_comp/data_r_reg[11] - ------------------------------------------------------------------- - required time 0.577 - arrival time -0.441 - ------------------------------------------------------------------- - slack 0.136 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.536ns (logic 0.250ns (46.632%) route 0.286ns (53.368%)) - Logic Levels: 2 (CARRY4=1 LUT4=1) - Clock Path Skew: 0.265ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.477ns - Source Clock Delay (SCD): -0.702ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.561 -0.702 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X82Y156 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X82Y156 FDCE (Prop_fdce_C_Q) 0.141 -0.561 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3_reg[11]/Q - net (fo=8, routed) 0.286 -0.275 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/q_s3[11] - SLICE_X84Y158 LUT4 (Prop_lut4_I3_O) 0.045 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4[19]_i_6/O - net (fo=1, routed) 0.000 -0.230 u_fft_mlkem_axi_slave_n_135 - SLICE_X84Y158 CARRY4 (Prop_carry4_S[3]_O[3]) - 0.064 -0.166 r u_bf/u_barrett/qprod_s4_reg[19]_i_1/O[3] - net (fo=1, routed) 0.000 -0.166 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[23]_1[11] - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.831 -0.477 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/mlkem_clk - SLICE_X84Y158 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19]/C - clock pessimism 0.040 -0.437 - SLICE_X84Y158 FDCE (Hold_fdce_C_D) 0.134 -0.303 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/u_bf/u_barrett/qprod_s4_reg[19] - ------------------------------------------------------------------- - required time 0.303 - arrival time -0.166 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.138ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.498ns (logic 0.186ns (37.319%) route 0.312ns (62.681%)) - Logic Levels: 1 (LUT6=1) - Clock Path Skew: 0.269ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.469ns - Source Clock Delay (SCD): -0.693ns - Clock Pessimism Removal (CPR): -0.045ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.570 -0.693 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X89Y155 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X89Y155 FDCE (Prop_fdce_C_Q) 0.141 -0.552 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r_reg[6]/Q - net (fo=234, routed) 0.312 -0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/wb_a_data_r[6] - SLICE_X86Y149 LUT6 (Prop_lut6_I2_O) 0.045 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1/O - net (fo=1, routed) 0.000 -0.194 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr[245][6]_i_1_n_0 - SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.839 -0.469 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/mlkem_clk - SLICE_X86Y149 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6]/C - clock pessimism 0.045 -0.424 - SLICE_X86Y149 FDCE (Hold_fdce_C_D) 0.092 -0.332 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ntt/cr_reg[245][6] - ------------------------------------------------------------------- - required time 0.332 - arrival time -0.194 - ------------------------------------------------------------------- - slack 0.138 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: mlkem_clk_clk_pll -Waveform(ns): { 0.000 20.000 } -Period(ns): 40.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 40.000 37.056 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_0/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y56 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_a/mem_reg_1/CLKBWRCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB36_X4Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_se/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X4Y52 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_bank_t/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y26 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_c_in_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y27 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ct_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y28 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_dkp_bram/mem_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 40.000 37.424 RAMB18_X7Y25 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_ek_bram/mem_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y17 pll_clk.u_clk_pll/inst/clkout3_buf/I -Min Period n/a PLLE2_ADV/CLKOUT2 n/a 1.249 40.000 38.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X103Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[897]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X101Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[898]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y118 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[899]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[89]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y110 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[900]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X102Y114 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[901]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[902]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X100Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[903]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X56Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[904]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[905]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y130 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[906]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[907]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X55Y129 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[908]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[909]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X147Y105 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[90]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[910]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X64Y123 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[911]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y117 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[912]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X93Y116 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[913]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X92Y115 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/dj_block_r_reg[914]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X148Y176 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][3]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][4]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X149Y181 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][5]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X125Y187 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][6]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X132Y173 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][7]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X135Y186 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][8]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X150Y179 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[191][9]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X130Y211 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][0]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][10]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X129Y208 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][11]/C -Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X121Y226 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/u_mlkem/u_pmul/mem_A_reg[192][1]/C -Max Period n/a PLLE2_ADV/CLKOUT2 n/a 160.000 40.000 120.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X20Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X46Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y77 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X22Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X52Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y76 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 20.000 18.750 SLICE_X64Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.079ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 8.750ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.544ns (logic 0.378ns (69.538%) route 0.166ns (30.462%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.260ns - Source Clock Delay (SCD): -0.566ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.696 -0.566 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X18Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.188 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][2]_srl32/Q31 - net (fo=1, routed) 0.166 -0.023 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__56 - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.048 -0.260 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X14Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32/CLK - clock pessimism 0.037 -0.223 - SLICE_X14Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.101 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][2]_srl32 - ------------------------------------------------------------------- - required time 0.101 - arrival time -0.023 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.079ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.242ns (logic 0.141ns (58.248%) route 0.101ns (41.752%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk - SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[5]/Q - net (fo=1, routed) 0.101 -0.299 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIB0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.146 -0.378 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.378 - arrival time -0.299 - ------------------------------------------------------------------- - slack 0.079 - -Slack (MET) : 0.080ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.244ns (logic 0.141ns (57.830%) route 0.103ns (42.170%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_axi_uart_controller/uart0/regs/receiver/sys_clk - SLICE_X4Y57 FDRE r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y57 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_axi_uart_controller/uart0/regs/receiver/rf_data_in_reg[3]/Q - net (fo=1, routed) 0.103 -0.298 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/DIA0 - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/I - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y56 RAMD32 r u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.524 - SLICE_X6Y56 RAMD32 (Hold_ramd32_CLK_I) - 0.147 -0.377 u_axi_uart_controller/uart0/regs/receiver/fifo_rx/rfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.377 - arrival time -0.298 - ------------------------------------------------------------------- - slack 0.080 - -Slack (MET) : 0.083ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.488ns (logic 0.164ns (33.640%) route 0.324ns (66.360%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[49]/Q - net (fo=1, routed) 0.324 -0.145 u_matmul_axi_slave/mult_inst[1].u_mult/prod[49] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.070 -0.228 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[49] - ------------------------------------------------------------------- - required time 0.228 - arrival time -0.145 - ------------------------------------------------------------------- - slack 0.083 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - (rising edge-triggered cell RAMB18E1 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.324ns (logic 0.164ns (50.614%) route 0.160ns (49.386%)) - Logic Levels: 0 - Clock Path Skew: 0.056ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.636 -0.626 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk - SLICE_X62Y75 FDCE r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X62Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.462 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5]/Q - net (fo=2, routed) 0.160 -0.302 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/wptr_reg[5] - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/ADDRBWRADDR[10] - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/sys_clk - RAMB18_X3Y30 RAMB18E1 r u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK - clock pessimism -0.213 -0.570 - RAMB18_X3Y30 RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10]) - 0.183 -0.387 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg - ------------------------------------------------------------------- - required time 0.387 - arrival time -0.302 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.096ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - (rising edge-triggered cell SRLC32E clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.561ns (logic 0.378ns (67.415%) route 0.183ns (32.585%)) - Logic Levels: 0 - Clock Path Skew: 0.343ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X20Y50 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y50 SRLC32E (Prop_srlc32e_CLK_Q31) - 0.378 -0.190 r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[127][1]_srl32/Q31 - net (fo=1, routed) 0.183 -0.008 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/xlnx_opt__55 - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.046 -0.262 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/sys_clk - SLICE_X20Y49 SRLC32E r u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32/CLK - clock pessimism 0.037 -0.225 - SLICE_X20Y49 SRLC32E (Hold_srlc32e_CLK_D) - 0.122 -0.103 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/DB1/buf_re_reg[159][1]_srl32 - ------------------------------------------------------------------- - required time 0.103 - arrival time -0.008 - ------------------------------------------------------------------- - slack 0.096 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.505ns (logic 0.164ns (32.465%) route 0.341ns (67.535%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[51]/Q - net (fo=1, routed) 0.341 -0.128 u_matmul_axi_slave/mult_inst[1].u_mult/prod[51] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51]/C - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.070 -0.229 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[51] - ------------------------------------------------------------------- - required time 0.229 - arrival time -0.128 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.101ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.198%) route 0.345ns (67.802%)) - Logic Levels: 0 - Clock Path Skew: 0.336ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[59]/Q - net (fo=1, routed) 0.345 -0.125 u_matmul_axi_slave/mult_inst[1].u_mult/prod[59] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.072 -0.226 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[59] - ------------------------------------------------------------------- - required time 0.226 - arrival time -0.125 - ------------------------------------------------------------------- - slack 0.101 - -Slack (MET) : 0.106ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.507ns (logic 0.164ns (32.320%) route 0.343ns (67.680%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.634ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.629 -0.634 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y104 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y104 FDRE (Prop_fdre_C_Q) 0.164 -0.470 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[57]/Q - net (fo=1, routed) 0.343 -0.127 u_matmul_axi_slave/mult_inst[1].u_mult/prod[57] - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X15Y89 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57]/C - clock pessimism 0.040 -0.299 - SLICE_X15Y89 FDRE (Hold_fdre_C_D) 0.066 -0.233 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[57] - ------------------------------------------------------------------- - required time 0.233 - arrival time -0.127 - ------------------------------------------------------------------- - slack 0.106 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.379ns (logic 0.164ns (43.254%) route 0.215ns (56.746%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[2]/Q - net (fo=18, routed) 0.215 -0.164 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD2 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR2 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR2) - 0.254 -0.272 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.272 - arrival time -0.164 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.509ns (logic 0.164ns (32.204%) route 0.345ns (67.796%)) - Logic Levels: 0 - Clock Path Skew: 0.335ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.633ns - Clock Pessimism Removal (CPR): -0.040ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.630 -0.633 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X14Y102 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y102 FDRE (Prop_fdre_C_Q) 0.164 -0.469 r u_matmul_axi_slave/mult_inst[1].u_mult/prod_reg[48]/Q - net (fo=1, routed) 0.345 -0.124 u_matmul_axi_slave/mult_inst[1].u_mult/prod[48] - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_matmul_axi_slave/mult_inst[1].u_mult/sys_clk - SLICE_X17Y92 FDRE r u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48]/C - clock pessimism 0.040 -0.298 - SLICE_X17Y92 FDRE (Hold_fdre_C_D) 0.066 -0.232 u_matmul_axi_slave/mult_inst[1].u_mult/p_reg[48] - ------------------------------------------------------------------- - required time 0.232 - arrival time -0.124 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.463ns (logic 0.164ns (35.436%) route 0.299ns (64.564%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[0]/Q - net (fo=8, routed) 0.299 -0.088 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A0 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.204 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.204 - arrival time -0.088 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/DP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.462ns (logic 0.164ns (35.508%) route 0.298ns (64.492%)) - Logic Levels: 0 - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.322ns - Source Clock Delay (SCD): -0.550ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.712 -0.550 u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/sys_clk - SLICE_X2Y75 FDCE r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y75 FDCE (Prop_fdce_C_Q) 0.164 -0.386 r u_AxiCrossbar_2x8/axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ptr_push_reg[1]/Q - net (fo=7, routed) 0.298 -0.089 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/A1 - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/WADR1 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.986 -0.322 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/WCLK - SLICE_X2Y74 RAMD32 r axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP/CLK - clock pessimism -0.192 -0.514 - SLICE_X2Y74 RAMD32 (Hold_ramd32_CLK_WADR1) - 0.309 -0.205 axi4WriteOnlyArbiter_4/cmdRouteFork_translated_fifo/fifo/logic_ram_reg_0_3_0_0/SP - ------------------------------------------------------------------- - required time 0.205 - arrival time -0.089 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMA_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMB_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/WADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMD32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMD32 (Hold_ramd32_CLK_WADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMC_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.117ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - (rising edge-triggered cell RAMS32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.444ns (logic 0.164ns (36.916%) route 0.280ns (63.084%)) - Logic Levels: 0 - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): -0.543ns - Clock Pessimism Removal (CPR): 0.216ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.719 -0.543 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/sys_clk - SLICE_X6Y62 FDRE r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X6Y62 FDRE (Prop_fdre_C_Q) 0.164 -0.379 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/top_reg[0]/Q - net (fo=20, routed) 0.280 -0.099 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/ADDRD0 - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/ADR0 - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/WCLK - SLICE_X6Y61 RAMS32 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1/CLK - clock pessimism -0.216 -0.526 - SLICE_X6Y61 RAMS32 (Hold_rams32_CLK_ADR0) - 0.310 -0.216 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tfifo/ram_reg_0_15_0_5/RAMD_D1 - ------------------------------------------------------------------- - required time 0.216 - arrival time -0.099 - ------------------------------------------------------------------- - slack 0.117 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.076 -0.496 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.496 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.076 -0.500 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.500 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.076 -0.492 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.492 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.076 -0.506 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.506 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.075 -0.497 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.497 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.309ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.232ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.400 r u_Axi_CDC/awFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.344 u_Axi_CDC/awFifo/bufferCC_12/buffers_0 - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.999 -0.309 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.232 -0.541 - SLICE_X7Y59 FDCE (Hold_fdce_C_D) 0.075 -0.466 u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.466 - arrival time -0.344 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.568ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.694 -0.568 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y59 FDCE (Prop_fdce_C_Q) 0.141 -0.427 r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.371 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.568 - SLICE_X17Y59 FDCE (Hold_fdce_C_D) 0.075 -0.493 u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.493 - arrival time -0.371 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): -0.539ns - Clock Pessimism Removal (CPR): 0.231ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y61 FDSE (Prop_fdse_C_Q) 0.141 -0.398 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.342 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0 - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0]/C - clock pessimism -0.231 -0.539 - SLICE_X1Y61 FDSE (Hold_fdse_C_D) 0.075 -0.464 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sync_dat_o_reg[0] - ------------------------------------------------------------------- - required time 0.464 - arrival time -0.342 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.603ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.659 -0.603 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X117Y61 FDCE (Prop_fdce_C_Q) 0.141 -0.462 r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/Q - net (fo=1, routed) 0.056 -0.406 u_fft_mlkem_axi_slave/mlkem_intr_sync[0] - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1]/C - clock pessimism -0.229 -0.603 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.075 -0.528 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[1] - ------------------------------------------------------------------- - required time 0.528 - arrival time -0.406 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): 0.227ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X29Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.390 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.227 -0.587 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.075 -0.512 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.512 - arrival time -0.390 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0 - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism -0.229 -0.570 - SLICE_X13Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.582 - SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.075 -0.507 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.507 - arrival time -0.385 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.569ns - Clock Pessimism Removal (CPR): 0.230ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.693 -0.569 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y88 FDCE (Prop_fdce_C_Q) 0.141 -0.428 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.372 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.230 -0.569 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.075 -0.494 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.494 - arrival time -0.372 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.229ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y87 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.056 -0.373 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.229 -0.570 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.075 -0.495 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.495 - arrival time -0.373 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.122ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): 0.226ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X113Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/Q - net (fo=1, routed) 0.056 -0.418 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0[0] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.226 -0.615 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.075 -0.540 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.540 - arrival time -0.418 - ------------------------------------------------------------------- - slack 0.122 - -Slack (MET) : 0.124ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.200ns (logic 0.141ns (70.589%) route 0.059ns (29.411%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/Q - net (fo=1, routed) 0.059 -0.267 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[2] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.236 -0.467 - SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.076 -0.391 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.391 - arrival time -0.267 - ------------------------------------------------------------------- - slack 0.124 - -Slack (MET) : 0.125ns (arrival time - required time) - Source: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.203ns (logic 0.141ns (69.572%) route 0.062ns (30.428%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.467ns - Clock Pessimism Removal (CPR): 0.236ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.796 -0.467 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X4Y49 FDCE (Prop_fdce_C_Q) 0.141 -0.326 r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/Q - net (fo=1, routed) 0.062 -0.264 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0[3] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.236 -0.467 - SLICE_X4Y49 FDCE (Hold_fdce_C_D) 0.078 -0.389 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.389 - arrival time -0.264 - ------------------------------------------------------------------- - slack 0.125 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.572ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y66 FDCE (Prop_fdce_C_Q) 0.141 -0.431 r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.375 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.572 - SLICE_X15Y66 FDCE (Hold_fdce_C_D) 0.071 -0.501 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.501 - arrival time -0.375 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) - Logic Levels: 0 - Clock Path Skew: 0.000ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.348ns - Source Clock Delay (SCD): -0.576ns - Clock Pessimism Removal (CPR): 0.228ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.686 -0.576 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.435 r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/Q - net (fo=1, routed) 0.056 -0.379 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0[1] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.960 -0.348 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.228 -0.576 - SLICE_X15Y70 FDCE (Hold_fdce_C_D) 0.071 -0.505 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.505 - arrival time -0.379 - ------------------------------------------------------------------- - slack 0.126 - - - - - -Pulse Width Checks --------------------------------------------------------------------------------------- -Clock Name: sys_clk -Waveform(ns): { 0.000 10.000 } -Period(ns): 20.000 -Sources: { pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 } - -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.944 20.000 17.056 RAMB18_X3Y30 u_snix_axil_cdma_mux_8ch/u_core_engine/axis_fifo_u0/u_fifo/mem_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y4 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y3 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_im_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y1 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_im_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB36_X0Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU2/TW/ff_re_reg/CLKBWRCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 20.000 17.424 RAMB36_X1Y2 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU4/TW/ff_re_reg/CLKARDCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y24 u_fft_mlkem_axi_slave/u_fft_controller/u_in0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y25 u_fft_mlkem_axi_slave/u_fft_controller/u_in1/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y22 u_fft_mlkem_axi_slave/u_fft_controller/u_out0/ram_reg/CLKBWRCLK -Min Period n/a RAMB18E1/CLKBWRCLK n/a 2.576 20.000 17.424 RAMB18_X1Y23 u_fft_mlkem_axi_slave/u_fft_controller/u_out1/ram_reg/CLKBWRCLK -Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y16 pll_clk.u_clk_pll/inst/clkout2_buf/I -Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.249 20.000 18.751 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y68 cdma_axil_b_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X24Y67 cdma_axil_r_bridge_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X14Y67 cdma_axil_wr_active_reg/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X15Y67 cdma_axil_wr_bridge_hold_reg/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X29Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X31Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X30Y0 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_count_reg[9]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y5 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[0]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y9 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[10]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[11]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X21Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X20Y10 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[13]/C -Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X17Y8 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU3/bf1_do_im_reg[14]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[0]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[1]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[2]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[3]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[4]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[5]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X4Y50 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[6]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[7]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[8]/C -Min Period n/a FDCE/C n/a 1.000 20.000 19.000 SLICE_X5Y51 u_fft_mlkem_axi_slave/u_fft_controller/u_FFT/SU1/bf1_count_reg[9]/C -Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 20.000 140.000 PLLE2_ADV_X0Y3 pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y75 u_matmul_axi_slave/b0_c_reg_r1_0_15_18_23/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X68Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y74 u_matmul_axi_slave/b0_c_reg_r1_0_15_48_53/RAMD_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -Low Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X44Y69 u_matmul_axi_slave/b0_c_reg_r2_0_15_36_41/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMA_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMB_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMC_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X42Y71 u_matmul_axi_slave/b0_c_reg_r2_0_15_6_11/RAMD_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X20Y72 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y68 u_matmul_axi_slave/b0_c_reg_r1_0_15_0_5/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X64Y69 u_matmul_axi_slave/b0_c_reg_r1_0_15_30_35/RAMD_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMA_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMB_D1/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC/CLK -High Pulse Width Slow RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMC_D1/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD/CLK -High Pulse Width Slow RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X60Y72 u_matmul_axi_slave/b0_c_reg_r1_0_15_54_59/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X62Y71 u_matmul_axi_slave/b0_c_reg_r1_0_15_60_65/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X22Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD/CLK -High Pulse Width Fast RAMS32/CLK n/a 1.250 10.000 8.750 SLICE_X36Y68 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMD_D1/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA/CLK -High Pulse Width Fast RAMD32/CLK n/a 1.250 10.000 8.750 SLICE_X56Y75 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - - - ---------------------------------------------------------------------------------------------------- -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.054ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.054ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.567ns (logic 0.394ns (69.509%) route 0.173ns (30.491%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.185 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB/O - net (fo=1, routed) 0.173 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[14] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[14] - ------------------------------------------------------------------- - required time 0.067 - arrival time -0.013 - ------------------------------------------------------------------- - slack 0.054 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.633ns (logic 0.390ns (61.631%) route 0.243ns (38.369%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.243 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[34] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.002 -0.056 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.056 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.113ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.678ns (logic 0.478ns (70.458%) route 0.200ns (29.542%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA_D1/O - net (fo=1, routed) 0.200 0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[13] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[13] - ------------------------------------------------------------------- - required time 0.014 - arrival time 0.099 - ------------------------------------------------------------------- - slack 0.113 - -Slack (MET) : 0.126ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.641ns (logic 0.394ns (61.457%) route 0.247ns (38.543%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB/O - net (fo=1, routed) 0.247 0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[38] - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y76 FDRE (Hold_fdre_C_D) -0.007 -0.069 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.069 - arrival time 0.058 - ------------------------------------------------------------------- - slack 0.126 - -Slack (MET) : 0.129ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.720ns (logic 0.478ns (66.344%) route 0.242ns (33.656%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.105 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.242 0.137 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[37] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.137 - ------------------------------------------------------------------- - slack 0.129 - -Slack (MET) : 0.134ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.629ns (logic 0.394ns (62.601%) route 0.235ns (37.399%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB/O - net (fo=1, routed) 0.235 0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[32] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) -0.027 -0.085 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.085 - arrival time 0.049 - ------------------------------------------------------------------- - slack 0.134 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.725ns (logic 0.388ns (53.539%) route 0.337ns (46.461%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMB_D1/O - net (fo=1, routed) 0.337 0.141 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[39] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.066 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time -0.004 - arrival time 0.141 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.137ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.666ns (logic 0.492ns (73.905%) route 0.174ns (26.095%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.090 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.174 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[42] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.006 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[42] - ------------------------------------------------------------------- - required time 0.054 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.137 - -Slack (MET) : 0.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.668ns (logic 0.492ns (73.684%) route 0.176ns (26.316%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.091 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMA/O - net (fo=1, routed) 0.176 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[36] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.005 -0.055 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.055 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.139 - -Slack (MET) : 0.143ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.734ns (logic 0.386ns (52.563%) route 0.348ns (47.437%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.348 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[41] - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X24Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y76 FDRE (Hold_fdre_C_D) 0.070 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[41] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.143 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.386ns (52.125%) route 0.355ns (47.875%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.355 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[35] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.072 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.160 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.153ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.670ns (logic 0.394ns (58.792%) route 0.276ns (41.208%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.186 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB/O - net (fo=1, routed) 0.276 0.090 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[32] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) -0.003 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.063 - arrival time 0.090 - ------------------------------------------------------------------- - slack 0.153 - -Slack (MET) : 0.157ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.681ns (logic 0.390ns (57.280%) route 0.291ns (42.720%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_36_41/RAMC/O - net (fo=1, routed) 0.291 0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[40] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) 0.002 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[40] - ------------------------------------------------------------------- - required time 0.060 - arrival time 0.097 - ------------------------------------------------------------------- - slack 0.157 - -Slack (MET) : 0.167ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.767ns (logic 0.164ns (21.391%) route 0.603ns (78.609%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.603 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[1] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.076 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.029 - arrival time 0.196 - ------------------------------------------------------------------- - slack 0.167 - -Slack (MET) : 0.170ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.754ns (logic 0.141ns (18.697%) route 0.613ns (81.303%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.613 0.183 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[3] - SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X16Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X16Y86 FDCE (Hold_fdce_C_D) 0.059 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.183 - ------------------------------------------------------------------- - slack 0.170 - -Slack (MET) : 0.182ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.775ns (logic 0.478ns (61.697%) route 0.297ns (38.303%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.297 0.195 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[49] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.071 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[49] - ------------------------------------------------------------------- - required time -0.013 - arrival time 0.195 - ------------------------------------------------------------------- - slack 0.182 - -Slack (MET) : 0.194ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.714ns (logic 0.394ns (55.191%) route 0.320ns (44.809%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.188 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMB/O - net (fo=1, routed) 0.320 0.132 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[44] - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X27Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X27Y76 FDRE (Hold_fdre_C_D) -0.001 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[44] - ------------------------------------------------------------------- - required time 0.063 - arrival time 0.132 - ------------------------------------------------------------------- - slack 0.194 - -Slack (MET) : 0.195ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.388ns (50.735%) route 0.377ns (49.265%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.377 0.184 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[33] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time 0.011 - arrival time 0.184 - ------------------------------------------------------------------- - slack 0.195 - -Slack (MET) : 0.198ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.768ns (logic 0.141ns (18.369%) route 0.627ns (81.631%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.627 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[1] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) 0.046 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.198 - -Slack (MET) : 0.205ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.775ns (logic 0.141ns (18.187%) route 0.634ns (81.813%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.634 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[0] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.046 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.193 - ------------------------------------------------------------------- - slack 0.205 - -Slack (MET) : 0.220ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.738ns (logic 0.128ns (17.350%) route 0.610ns (82.650%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.488 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.610 0.121 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[3] - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X117Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X117Y75 FDCE (Hold_fdce_C_D) -0.006 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.099 - arrival time 0.121 - ------------------------------------------------------------------- - slack 0.220 - -Slack (MET) : 0.225ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.748ns (logic 0.390ns (52.130%) route 0.358ns (47.870%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.358 0.168 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[34] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.002 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.168 - ------------------------------------------------------------------- - slack 0.225 - -Slack (MET) : 0.227ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.815ns (logic 0.141ns (17.291%) route 0.674ns (82.709%)) - Logic Levels: 0 - Clock Path Skew: 0.322ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.361ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.674 0.231 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[0] - SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.947 -0.361 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X32Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.262 - clock uncertainty 0.197 -0.066 - SLICE_X32Y74 FDCE (Hold_fdce_C_D) 0.070 0.004 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.004 - arrival time 0.231 - ------------------------------------------------------------------- - slack 0.227 - -Slack (MET) : 0.228ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.766ns (logic 0.128ns (16.716%) route 0.638ns (83.284%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.128 -0.456 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.638 0.181 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.018 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.181 - ------------------------------------------------------------------- - slack 0.228 - -Slack (MET) : 0.234ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.781ns (logic 0.148ns (18.960%) route 0.633ns (81.040%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.148 -0.422 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.633 0.210 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[2] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.023 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.024 - arrival time 0.210 - ------------------------------------------------------------------- - slack 0.234 - -Slack (MET) : 0.236ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.831ns (logic 0.386ns (46.464%) route 0.445ns (53.536%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y71 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y71 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.445 0.250 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[35] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.072 0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time -0.014 - arrival time 0.250 - ------------------------------------------------------------------- - slack 0.236 - -Slack (MET) : 0.238ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.827ns (logic 0.141ns (17.044%) route 0.686ns (82.956%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/sys_clk - SLICE_X27Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y73 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.686 0.243 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/Q[1] - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y74 FDCE (Hold_fdce_C_D) 0.070 0.005 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.005 - arrival time 0.243 - ------------------------------------------------------------------- - slack 0.238 - -Slack (MET) : 0.241ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.823ns (logic 0.388ns (47.171%) route 0.435ns (52.829%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X18Y74 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y74 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.192 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.435 0.242 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[33] - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y76 FDRE (Hold_fdre_C_D) 0.061 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time -0.001 - arrival time 0.242 - ------------------------------------------------------------------- - slack 0.241 - -Slack (MET) : 0.257ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.827ns (logic 0.141ns (17.047%) route 0.686ns (82.953%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.686 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[1] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.047 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.245 - ------------------------------------------------------------------- - slack 0.257 - -Slack (MET) : 0.259ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.857ns (logic 0.164ns (19.129%) route 0.693ns (80.871%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y87 FDCE (Prop_fdce_C_Q) 0.164 -0.406 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.693 0.287 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/Q[0] - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X14Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.243 - clock uncertainty 0.197 -0.047 - SLICE_X14Y86 FDCE (Hold_fdce_C_D) 0.075 0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.028 - arrival time 0.287 - ------------------------------------------------------------------- - slack 0.259 - -Slack (MET) : 0.259ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.788ns (logic 0.492ns (62.440%) route 0.296ns (37.560%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X22Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_36_41/RAMA/O - net (fo=1, routed) 0.296 0.211 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[36] - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X25Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y70 FDRE (Hold_fdre_C_D) 0.009 -0.049 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.049 - arrival time 0.211 - ------------------------------------------------------------------- - slack 0.259 - -Slack (MET) : 0.262ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.788ns (logic 0.492ns (62.458%) route 0.296ns (37.542%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y70 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y70 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.296 0.208 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[48] - SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X26Y70 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X26Y70 FDRE (Hold_fdre_C_D) 0.004 -0.054 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[48] - ------------------------------------------------------------------- - required time 0.054 - arrival time 0.208 - ------------------------------------------------------------------- - slack 0.262 - -Slack (MET) : 0.272ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.793ns (logic 0.492ns (62.032%) route 0.301ns (37.968%)) - Logic Levels: 0 - Clock Path Skew: 0.320ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.358ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMA/O - net (fo=1, routed) 0.301 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[12] - SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.950 -0.358 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X25Y74 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12]/C - clock pessimism 0.099 -0.259 - clock uncertainty 0.197 -0.063 - SLICE_X25Y74 FDRE (Hold_fdre_C_D) 0.004 -0.059 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[12] - ------------------------------------------------------------------- - required time 0.059 - arrival time 0.214 - ------------------------------------------------------------------- - slack 0.272 - -Slack (MET) : 0.287ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.856ns (logic 0.141ns (16.478%) route 0.715ns (83.522%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.715 0.239 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[0] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.048 - arrival time 0.239 - ------------------------------------------------------------------- - slack 0.287 - -Slack (MET) : 0.289ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.861ns (logic 0.141ns (16.382%) route 0.720ns (83.618%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.720 0.278 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/Q[1] - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) 0.047 -0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.011 - arrival time 0.278 - ------------------------------------------------------------------- - slack 0.289 - -Slack (MET) : 0.319ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.916ns (logic 0.478ns (52.162%) route 0.438ns (47.838%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X22Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.104 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_42_47/RAMA_D1/O - net (fo=1, routed) 0.438 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[43] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.075 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[43] - ------------------------------------------------------------------- - required time -0.015 - arrival time 0.334 - ------------------------------------------------------------------- - slack 0.319 - -Slack (MET) : 0.351ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.478ns (51.242%) route 0.455ns (48.758%)) - Logic Levels: 0 - Clock Path Skew: 0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.101 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.455 0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[49] - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[49] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.353 - ------------------------------------------------------------------- - slack 0.351 - -Slack (MET) : 0.363ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.879ns (logic 0.128ns (14.560%) route 0.751ns (85.440%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.751 0.297 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) -0.007 -0.067 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.067 - arrival time 0.297 - ------------------------------------------------------------------- - slack 0.363 - -Slack (MET) : 0.364ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.953ns (logic 0.388ns (40.695%) route 0.565ns (59.305%)) - Logic Levels: 0 - Clock Path Skew: 0.323ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/WCLK - SLICE_X20Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_12_17/RAMB_D1/O - net (fo=1, routed) 0.565 0.374 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[15] - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X23Y73 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X23Y73 FDRE (Hold_fdre_C_D) 0.070 0.010 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time -0.010 - arrival time 0.374 - ------------------------------------------------------------------- - slack 0.364 - -Slack (MET) : 0.389ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.957ns (logic 0.141ns (14.730%) route 0.816ns (85.270%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X26Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.816 0.375 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/mlkem_clk - SLICE_X27Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.256 - clock uncertainty 0.197 -0.060 - SLICE_X27Y72 FDCE (Hold_fdce_C_D) 0.046 -0.014 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.014 - arrival time 0.375 - ------------------------------------------------------------------- - slack 0.389 - -Slack (MET) : 0.405ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.922ns (logic 0.128ns (13.878%) route 0.794ns (86.122%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/sys_clk - SLICE_X27Y77 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X27Y77 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.794 0.340 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X27Y79 FDCE (Hold_fdce_C_D) -0.007 -0.065 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.065 - arrival time 0.340 - ------------------------------------------------------------------- - slack 0.405 - -Slack (MET) : 0.464ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.033ns (logic 0.141ns (13.645%) route 0.892ns (86.355%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.616ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.646 -0.616 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/sys_clk - SLICE_X111Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X111Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.475 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=2, routed) 0.892 0.417 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/D[2] - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X115Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X115Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.417 - ------------------------------------------------------------------- - slack 0.464 - -Slack (MET) : 0.480ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.000ns (logic 0.492ns (49.207%) route 0.508ns (50.793%)) - Logic Levels: 0 - Clock Path Skew: 0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y73 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y73 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.087 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.508 0.420 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port10__2[48] - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X31Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X31Y76 FDRE (Hold_fdre_C_D) 0.004 -0.060 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/_zz_ram_port1_reg[48] - ------------------------------------------------------------------- - required time 0.060 - arrival time 0.420 - ------------------------------------------------------------------- - slack 0.480 - -Slack (MET) : 0.497ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.967ns (logic 0.394ns (40.759%) route 0.573ns (59.241%)) - Logic Levels: 0 - Clock Path Skew: 0.283ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.573 0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[2] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.010 -0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[2] - ------------------------------------------------------------------- - required time 0.115 - arrival time 0.382 - ------------------------------------------------------------------- - slack 0.497 - -Slack (MET) : 0.502ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.108ns (logic 0.386ns (34.837%) route 0.722ns (65.163%)) - Logic Levels: 0 - Clock Path Skew: 0.339ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.387ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.722 0.481 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[11] - SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.921 -0.387 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X110Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.288 - clock uncertainty 0.197 -0.092 - SLICE_X110Y72 FDRE (Hold_fdre_C_D) 0.070 -0.022 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 0.022 - arrival time 0.481 - ------------------------------------------------------------------- - slack 0.502 - -Slack (MET) : 0.533ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.124ns (logic 0.388ns (34.515%) route 0.736ns (65.485%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.736 0.497 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[9] - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X100Y72 FDRE (Hold_fdre_C_D) 0.063 -0.037 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time 0.037 - arrival time 0.497 - ------------------------------------------------------------------- - slack 0.533 - -Slack (MET) : 0.632ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.187ns (logic 0.386ns (32.521%) route 0.801ns (67.479%)) - Logic Levels: 0 - Clock Path Skew: 0.282ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y67 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y67 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.197 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_6_11/RAMC_D1/O - net (fo=1, routed) 0.801 0.604 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[11] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) 0.076 -0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time 0.029 - arrival time 0.604 - ------------------------------------------------------------------- - slack 0.632 - -Slack (MET) : 0.642ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.159ns (logic 0.394ns (33.980%) route 0.765ns (66.020%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/WCLK - SLICE_X72Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X72Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.765 0.532 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[8] - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X100Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X100Y72 FDRE (Hold_fdre_C_D) -0.010 -0.110 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 0.110 - arrival time 0.532 - ------------------------------------------------------------------- - slack 0.642 - -Slack (MET) : 0.658ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.258ns (logic 0.386ns (30.689%) route 0.872ns (69.311%)) - Logic Levels: 0 - Clock Path Skew: 0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.385ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/WCLK - SLICE_X68Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X68Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.872 0.631 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port10__0[35] - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.923 -0.385 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X116Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.286 - clock uncertainty 0.197 -0.090 - SLICE_X116Y77 FDRE (Hold_fdre_C_D) 0.063 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.631 - ------------------------------------------------------------------- - slack 0.658 - -Slack (MET) : 0.705ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: mlkem_clk_clk_pll - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.170ns (logic 0.390ns (33.342%) route 0.780ns (66.658%)) - Logic Levels: 0 - Clock Path Skew: 0.283ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.400ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y68 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y68 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.194 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.780 0.585 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port10[4] - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.908 -0.400 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X76Y67 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4]/C - clock pessimism 0.099 -0.301 - clock uncertainty 0.197 -0.105 - SLICE_X76Y67 FDRE (Hold_fdre_C_D) -0.015 -0.120 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 0.120 - arrival time 0.585 - ------------------------------------------------------------------- - slack 0.705 - - - - - ---------------------------------------------------------------------------------------------------- -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.032ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.032ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.560ns (logic 0.390ns (69.595%) route 0.170ns (30.405%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.191 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC/O - net (fo=1, routed) 0.170 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[34] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.004 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[34] - ------------------------------------------------------------------- - required time 0.053 - arrival time -0.021 - ------------------------------------------------------------------- - slack 0.032 - -Slack (MET) : 0.042ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.558ns (logic 0.394ns (70.575%) route 0.164ns (29.425%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB/O - net (fo=1, routed) 0.164 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[38] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) -0.007 -0.061 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[38] - ------------------------------------------------------------------- - required time 0.061 - arrival time -0.019 - ------------------------------------------------------------------- - slack 0.042 - -Slack (MET) : 0.066ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.647ns (logic 0.386ns (59.641%) route 0.261ns (40.359%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.241 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.261 0.020 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[23] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23]/C - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) 0.052 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[23] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.020 - ------------------------------------------------------------------- - slack 0.066 - -Slack (MET) : 0.085ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.386ns (58.079%) route 0.279ns (41.921%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.195 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMC_D1/O - net (fo=1, routed) 0.279 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[35] - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X14Y78 FDRE (Hold_fdre_C_D) 0.052 -0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[35] - ------------------------------------------------------------------- - required time 0.002 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.085 - -Slack (MET) : 0.087ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.611ns (logic 0.492ns (80.558%) route 0.119ns (19.442%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.089 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 0.119 0.029 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[30] - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X23Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30]/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X23Y77 FDRE (Hold_fdre_C_D) 0.000 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[30] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.029 - ------------------------------------------------------------------- - slack 0.087 - -Slack (MET) : 0.103ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.697ns (logic 0.478ns (68.593%) route 0.219ns (31.407%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.099 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA_D1/O - net (fo=1, routed) 0.219 0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[37] - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X15Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[37] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.119 - ------------------------------------------------------------------- - slack 0.103 - -Slack (MET) : 0.108ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.707ns (logic 0.388ns (54.849%) route 0.319ns (45.151%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 0.319 0.081 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[15] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.070 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[15] - ------------------------------------------------------------------- - required time 0.027 - arrival time 0.081 - ------------------------------------------------------------------- - slack 0.108 - -Slack (MET) : 0.121ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.723ns (logic 0.388ns (53.631%) route 0.335ns (46.369%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.239 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB_D1/O - net (fo=1, routed) 0.335 0.096 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[21] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.072 -0.025 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[21] - ------------------------------------------------------------------- - required time 0.025 - arrival time 0.096 - ------------------------------------------------------------------- - slack 0.121 - -Slack (MET) : 0.128ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.656ns (logic 0.492ns (75.032%) route 0.164ns (24.968%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.085 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMA/O - net (fo=1, routed) 0.164 0.078 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[36] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.004 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[36] - ------------------------------------------------------------------- - required time 0.050 - arrival time 0.078 - ------------------------------------------------------------------- - slack 0.128 - -Slack (MET) : 0.130ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.648ns (logic 0.394ns (60.840%) route 0.254ns (39.160%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.187 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 0.254 0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[32] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) -0.007 -0.064 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[32] - ------------------------------------------------------------------- - required time 0.064 - arrival time 0.066 - ------------------------------------------------------------------- - slack 0.130 - -Slack (MET) : 0.142ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.739ns (logic 0.478ns (64.724%) route 0.261ns (35.276%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.146 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 0.261 0.114 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[25] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.072 -0.028 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[25] - ------------------------------------------------------------------- - required time 0.028 - arrival time 0.114 - ------------------------------------------------------------------- - slack 0.142 - -Slack (MET) : 0.148ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.665ns (logic 0.492ns (73.994%) route 0.173ns (26.006%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.399ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.135 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA/O - net (fo=1, routed) 0.173 0.038 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[18] - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.909 -0.399 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18]/C - clock pessimism 0.099 -0.300 - clock uncertainty 0.197 -0.104 - SLICE_X62Y76 FDRE (Hold_fdre_C_D) -0.007 -0.111 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[18] - ------------------------------------------------------------------- - required time 0.111 - arrival time 0.038 - ------------------------------------------------------------------- - slack 0.148 - -Slack (MET) : 0.172ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.699ns (logic 0.390ns (55.761%) route 0.309ns (44.239%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.234 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 0.309 0.075 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[28] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.003 -0.097 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[28] - ------------------------------------------------------------------- - required time 0.097 - arrival time 0.075 - ------------------------------------------------------------------- - slack 0.172 - -Slack (MET) : 0.172ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.141ns (19.033%) route 0.600ns (80.967%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.600 0.125 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.047 -0.047 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.047 - arrival time 0.125 - ------------------------------------------------------------------- - slack 0.172 - -Slack (MET) : 0.173ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.390ns (56.076%) route 0.305ns (43.924%)) - Logic Levels: 0 - Clock Path Skew: 0.322ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.682 -0.580 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/WCLK - SLICE_X22Y72 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y72 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.190 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/ram_reg_0_3_0_5/RAMC/O - net (fo=1, routed) 0.305 0.115 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port10__1[4] - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X28Y72 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X28Y72 FDRE (Hold_fdre_C_D) 0.004 -0.058 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/_zz_ram_port1_reg[4] - ------------------------------------------------------------------- - required time 0.058 - arrival time 0.115 - ------------------------------------------------------------------- - slack 0.173 - -Slack (MET) : 0.178ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.141ns (18.448%) route 0.623ns (81.552%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 0.623 0.193 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[2] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) 0.061 0.015 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time -0.015 - arrival time 0.193 - ------------------------------------------------------------------- - slack 0.178 - -Slack (MET) : 0.180ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.709ns (logic 0.390ns (55.003%) route 0.319ns (44.997%)) - Logic Levels: 0 - Clock Path Skew: 0.330ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 0.319 0.083 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[16] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.002 -0.098 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[16] - ------------------------------------------------------------------- - required time 0.098 - arrival time 0.083 - ------------------------------------------------------------------- - slack 0.180 - -Slack (MET) : 0.187ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.766ns (logic 0.164ns (21.399%) route 0.602ns (78.601%)) - Logic Levels: 0 - Clock Path Skew: 0.337ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.374ns - Source Clock Delay (SCD): -0.612ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.650 -0.612 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X112Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X112Y71 FDCE (Prop_fdce_C_Q) 0.164 -0.448 r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/done_sync_reg[1]/Q - net (fo=2, routed) 0.602 0.154 u_fft_mlkem_axi_slave/mlkem_intr_m - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.934 -0.374 u_fft_mlkem_axi_slave/sys_clk - SLICE_X117Y61 FDCE r u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0]/C - clock pessimism 0.099 -0.275 - clock uncertainty 0.197 -0.079 - SLICE_X117Y61 FDCE (Hold_fdce_C_D) 0.046 -0.033 u_fft_mlkem_axi_slave/mlkem_intr_sync_reg[0] - ------------------------------------------------------------------- - required time 0.033 - arrival time 0.154 - ------------------------------------------------------------------- - slack 0.187 - -Slack (MET) : 0.189ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.758ns (logic 0.141ns (18.596%) route 0.617ns (81.404%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.617 0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[3] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X114Y76 FDCE (Hold_fdce_C_D) 0.047 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.143 - ------------------------------------------------------------------- - slack 0.189 - -Slack (MET) : 0.199ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.767ns (logic 0.141ns (18.390%) route 0.626ns (81.610%)) - Logic Levels: 0 - Clock Path Skew: 0.325ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.389ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.141 -0.474 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.626 0.151 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.919 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X113Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.290 - clock uncertainty 0.197 -0.094 - SLICE_X113Y75 FDCE (Hold_fdce_C_D) 0.046 -0.048 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.048 - arrival time 0.151 - ------------------------------------------------------------------- - slack 0.199 - -Slack (MET) : 0.200ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.721ns (logic 0.390ns (54.106%) route 0.331ns (45.894%)) - Logic Levels: 0 - Clock Path Skew: 0.333ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.393ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.390 -0.237 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 0.331 0.093 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[22] - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.915 -0.393 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X62Y81 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22]/C - clock pessimism 0.099 -0.294 - clock uncertainty 0.197 -0.098 - SLICE_X62Y81 FDRE (Hold_fdre_C_D) -0.009 -0.107 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[22] - ------------------------------------------------------------------- - required time 0.107 - arrival time 0.093 - ------------------------------------------------------------------- - slack 0.200 - -Slack (MET) : 0.211ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.780ns (logic 0.141ns (18.081%) route 0.639ns (81.919%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.639 0.192 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[1] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.019 - arrival time 0.192 - ------------------------------------------------------------------- - slack 0.211 - -Slack (MET) : 0.216ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.790ns (logic 0.141ns (17.837%) route 0.649ns (82.163%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.649 0.219 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[1] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.240 - clock uncertainty 0.197 -0.044 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.047 0.003 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time -0.003 - arrival time 0.219 - ------------------------------------------------------------------- - slack 0.216 - -Slack (MET) : 0.221ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.844ns (logic 0.386ns (45.725%) route 0.458ns (54.275%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.458 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[11] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.066 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[11] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.221 - -Slack (MET) : 0.228ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.822ns (logic 0.388ns (47.208%) route 0.434ns (52.792%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.349ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.685 -0.577 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X18Y78 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y78 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.189 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 0.434 0.245 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[39] - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.959 -0.349 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39]/C - clock pessimism 0.099 -0.250 - clock uncertainty 0.197 -0.054 - SLICE_X17Y78 FDRE (Hold_fdre_C_D) 0.070 0.016 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[39] - ------------------------------------------------------------------- - required time -0.016 - arrival time 0.245 - ------------------------------------------------------------------- - slack 0.228 - -Slack (MET) : 0.233ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.802ns (logic 0.141ns (17.574%) route 0.661ns (82.426%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.661 0.220 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y71 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.220 - ------------------------------------------------------------------- - slack 0.233 - -Slack (MET) : 0.234ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.803ns (logic 0.141ns (17.555%) route 0.662ns (82.445%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.587ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.675 -0.587 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X31Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.446 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.662 0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[2] - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X29Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X29Y74 FDCE (Hold_fdce_C_D) 0.047 -0.018 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.018 - arrival time 0.216 - ------------------------------------------------------------------- - slack 0.234 - -Slack (MET) : 0.236ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.807ns (logic 0.141ns (17.466%) route 0.666ns (82.534%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.584ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.678 -0.584 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y78 FDCE (Prop_fdce_C_Q) 0.141 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.666 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[0] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.046 -0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.013 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.236 - -Slack (MET) : 0.238ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.811ns (logic 0.141ns (17.379%) route 0.670ns (82.621%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.141 -0.430 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.670 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[0] - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.240 - clock uncertainty 0.197 -0.044 - SLICE_X15Y88 FDCE (Hold_fdce_C_D) 0.046 0.002 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time -0.002 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.238 - -Slack (MET) : 0.241ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.746ns (logic 0.492ns (65.912%) route 0.254ns (34.088%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.132 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMA/O - net (fo=1, routed) 0.254 0.122 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[24] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) -0.019 -0.119 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[24] - ------------------------------------------------------------------- - required time 0.119 - arrival time 0.122 - ------------------------------------------------------------------- - slack 0.241 - -Slack (MET) : 0.246ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.850ns (logic 0.388ns (45.663%) route 0.462ns (54.337%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.236 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 0.462 0.225 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[27] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.076 -0.021 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[27] - ------------------------------------------------------------------- - required time 0.021 - arrival time 0.225 - ------------------------------------------------------------------- - slack 0.246 - -Slack (MET) : 0.247ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.848ns (logic 0.386ns (45.530%) route 0.462ns (54.470%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.238 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 0.462 0.223 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[29] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.076 -0.024 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[29] - ------------------------------------------------------------------- - required time 0.024 - arrival time 0.223 - ------------------------------------------------------------------- - slack 0.247 - -Slack (MET) : 0.249ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.822ns (logic 0.386ns (46.947%) route 0.436ns (53.053%)) - Logic Levels: 0 - Clock Path Skew: 0.330ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.395ns - Source Clock Delay (SCD): -0.626ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.636 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X64Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.240 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.436 0.196 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[17] - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.913 -0.395 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X61Y77 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17]/C - clock pessimism 0.099 -0.296 - clock uncertainty 0.197 -0.100 - SLICE_X61Y77 FDRE (Hold_fdre_C_D) 0.047 -0.053 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[17] - ------------------------------------------------------------------- - required time 0.053 - arrival time 0.196 - ------------------------------------------------------------------- - slack 0.249 - -Slack (MET) : 0.252ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.824ns (logic 0.141ns (17.122%) route 0.683ns (82.878%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.683 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[2] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.252 - -Slack (MET) : 0.255ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.845ns (logic 0.478ns (56.587%) route 0.367ns (43.413%)) - Logic Levels: 0 - Clock Path Skew: 0.321ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.103 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 0.367 0.263 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[31] - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X29Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X29Y76 FDRE (Hold_fdre_C_D) 0.072 0.008 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[31] - ------------------------------------------------------------------- - required time -0.008 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.255 - -Slack (MET) : 0.256ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.828ns (logic 0.141ns (17.038%) route 0.687ns (82.962%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.583ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.679 -0.583 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y79 FDCE (Prop_fdce_C_Q) 0.141 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.687 0.244 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/D[1] - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/sys_clk - SLICE_X27Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.099 -0.255 - clock uncertainty 0.197 -0.059 - SLICE_X27Y78 FDCE (Hold_fdce_C_D) 0.047 -0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.012 - arrival time 0.244 - ------------------------------------------------------------------- - slack 0.256 - -Slack (MET) : 0.260ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.829ns (logic 0.141ns (16.998%) route 0.688ns (83.002%)) - Logic Levels: 0 - Clock Path Skew: 0.327ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.588ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.674 -0.588 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X33Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X33Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.447 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.688 0.241 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/D[0] - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/sys_clk - SLICE_X30Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X30Y74 FDCE (Hold_fdce_C_D) 0.046 -0.019 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.019 - arrival time 0.241 - ------------------------------------------------------------------- - slack 0.260 - -Slack (MET) : 0.261ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.776ns (logic 0.128ns (16.502%) route 0.648ns (83.498%)) - Logic Levels: 0 - Clock Path Skew: 0.326ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.388ns - Source Clock Delay (SCD): -0.615ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.647 -0.615 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/mlkem_clk - SLICE_X114Y75 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X114Y75 FDCE (Prop_fdce_C_Q) 0.128 -0.487 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.648 0.160 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.920 -0.388 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/sys_clk - SLICE_X114Y76 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.289 - clock uncertainty 0.197 -0.093 - SLICE_X114Y76 FDCE (Hold_fdce_C_D) -0.008 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.101 - arrival time 0.160 - ------------------------------------------------------------------- - slack 0.261 - -Slack (MET) : 0.266ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.785ns (logic 0.128ns (16.296%) route 0.657ns (83.704%)) - Logic Levels: 0 - Clock Path Skew: 0.329ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.571ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.691 -0.571 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/mlkem_clk - SLICE_X15Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y86 FDCE (Prop_fdce_C_Q) 0.128 -0.443 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 0.657 0.214 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/D[3] - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X15Y87 FDCE (Hold_fdce_C_D) -0.006 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.052 - arrival time 0.214 - ------------------------------------------------------------------- - slack 0.266 - -Slack (MET) : 0.268ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.823ns (logic 0.394ns (47.859%) route 0.429ns (52.141%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.227 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 0.429 0.202 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[8] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) -0.001 -0.066 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[8] - ------------------------------------------------------------------- - required time 0.066 - arrival time 0.202 - ------------------------------------------------------------------- - slack 0.268 - -Slack (MET) : 0.290ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.868ns (logic 0.478ns (55.096%) route 0.390ns (44.904%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.478 -0.149 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMA_D1/O - net (fo=1, routed) 0.390 0.240 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[19] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) 0.047 -0.050 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[19] - ------------------------------------------------------------------- - required time 0.050 - arrival time 0.240 - ------------------------------------------------------------------- - slack 0.290 - -Slack (MET) : 0.311ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.837ns (logic 0.394ns (47.100%) route 0.443ns (52.900%)) - Logic Levels: 0 - Clock Path Skew: 0.331ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.624ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.638 -0.624 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X64Y77 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.230 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.443 0.212 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[26] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.002 -0.099 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[26] - ------------------------------------------------------------------- - required time 0.099 - arrival time 0.212 - ------------------------------------------------------------------- - slack 0.311 - -Slack (MET) : 0.319ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.942ns (logic 0.388ns (41.191%) route 0.554ns (58.809%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 0.554 0.321 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[3] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.066 0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[3] - ------------------------------------------------------------------- - required time -0.001 - arrival time 0.321 - ------------------------------------------------------------------- - slack 0.319 - -Slack (MET) : 0.323ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.955ns (logic 0.388ns (40.612%) route 0.567ns (59.388%)) - Logic Levels: 0 - Clock Path Skew: 0.360ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 0.567 0.334 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[9] - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X31Y75 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9]/C - clock pessimism 0.099 -0.261 - clock uncertainty 0.197 -0.065 - SLICE_X31Y75 FDRE (Hold_fdre_C_D) 0.076 0.011 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[9] - ------------------------------------------------------------------- - required time -0.011 - arrival time 0.334 - ------------------------------------------------------------------- - slack 0.323 - -Slack (MET) : 0.346ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.883ns (logic 0.128ns (14.500%) route 0.755ns (85.500%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.128 -0.454 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.755 0.300 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X26Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X26Y73 FDCE (Hold_fdce_C_D) 0.016 -0.046 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.046 - arrival time 0.300 - ------------------------------------------------------------------- - slack 0.346 - -Slack (MET) : 0.347ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.851ns (logic 0.394ns (46.280%) route 0.457ns (53.720%)) - Logic Levels: 0 - Clock Path Skew: 0.334ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.392ns - Source Clock Delay (SCD): -0.627ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.635 -0.627 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X64Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X64Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.233 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 0.457 0.224 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[20] - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.916 -0.392 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X57Y78 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20]/C - clock pessimism 0.099 -0.293 - clock uncertainty 0.197 -0.097 - SLICE_X57Y78 FDRE (Hold_fdre_C_D) -0.026 -0.123 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[20] - ------------------------------------------------------------------- - required time 0.123 - arrival time 0.224 - ------------------------------------------------------------------- - slack 0.347 - -Slack (MET) : 0.402ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.983ns (logic 0.141ns (14.340%) route 0.842ns (85.660%)) - Logic Levels: 0 - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.357ns - Source Clock Delay (SCD): -0.582ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.680 -0.582 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/mlkem_clk - SLICE_X24Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X24Y72 FDCE (Prop_fdce_C_Q) 0.141 -0.441 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.842 0.401 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.951 -0.357 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X24Y73 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.099 -0.258 - clock uncertainty 0.197 -0.062 - SLICE_X24Y73 FDCE (Hold_fdce_C_D) 0.061 -0.001 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.001 - arrival time 0.401 - ------------------------------------------------------------------- - slack 0.402 - -Slack (MET) : 0.410ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.005ns (logic 0.388ns (38.609%) route 0.617ns (61.391%)) - Logic Levels: 0 - Clock Path Skew: 0.328ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.352ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X20Y76 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.388 -0.193 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_30_35/RAMB_D1/O - net (fo=1, routed) 0.617 0.424 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[33] - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.956 -0.352 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X19Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33]/C - clock pessimism 0.099 -0.253 - clock uncertainty 0.197 -0.057 - SLICE_X19Y76 FDRE (Hold_fdre_C_D) 0.070 0.013 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[33] - ------------------------------------------------------------------- - required time -0.013 - arrival time 0.424 - ------------------------------------------------------------------- - slack 0.410 - -Slack (MET) : 0.416ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.986ns (logic 0.492ns (49.918%) route 0.494ns (50.082%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X46Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X46Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.492 -0.129 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 0.494 0.364 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[6] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.012 -0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[6] - ------------------------------------------------------------------- - required time 0.052 - arrival time 0.364 - ------------------------------------------------------------------- - slack 0.416 - -Slack (MET) : 0.420ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: sys_clk - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 1.054ns (logic 0.386ns (36.630%) route 0.668ns (63.370%)) - Logic Levels: 0 - Clock Path Skew: 0.361ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.359ns - Source Clock Delay (SCD): -0.621ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.641 -0.621 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X52Y75 RAMD32 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X52Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.235 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 0.668 0.432 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port10__3[5] - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.949 -0.359 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X28Y76 FDRE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5]/C - clock pessimism 0.099 -0.260 - clock uncertainty 0.197 -0.064 - SLICE_X28Y76 FDRE (Hold_fdre_C_D) 0.076 0.012 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/_zz_ram_port1_reg[5] - ------------------------------------------------------------------- - required time -0.012 - arrival time 0.432 - ------------------------------------------------------------------- - slack 0.420 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: cpu_clk - To Clock: cpu_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.651ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.651ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.880%) route 0.593ns (76.120%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.194ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.307ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.372 0.314 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X6Y50 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.001 -0.307 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3]/C - clock pessimism 0.037 -0.270 - SLICE_X6Y50 FDCE (Remov_fdce_C_CLR) -0.067 -0.337 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.337 - arrival time 0.314 - ------------------------------------------------------------------- - slack 0.651 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.703ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.627ns (logic 0.186ns (29.656%) route 0.441ns (70.344%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.220 0.162 u_Axi_CDC/wFifo/popToPushGray_buffercc/p_0_in - SLICE_X0Y49 FDCE f u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X0Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.162 - ------------------------------------------------------------------- - slack 0.703 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.885ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.838ns (logic 0.227ns (27.080%) route 0.611ns (72.920%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.404 0.263 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X19Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.263 - ------------------------------------------------------------------- - slack 0.885 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 0.936ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.860ns (logic 0.186ns (21.621%) route 0.674ns (78.379%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.016ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.229ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): 0.220ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.453 0.395 u_Axi_CDC/wFifo/p_0_in - SLICE_X3Y49 FDCE f u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.079 -0.229 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2]/C - clock pessimism -0.220 -0.449 - SLICE_X3Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.541 u_Axi_CDC/wFifo/pushCC_pushPtr_reg[2] - ------------------------------------------------------------------- - required time 0.541 - arrival time 0.395 - ------------------------------------------------------------------- - slack 0.936 - -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.005ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.958ns (logic 0.227ns (23.685%) route 0.731ns (76.315%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.525 0.383 u_Axi_CDC/bFifo/buffers_1_reg - SLICE_X17Y58 FDCE f u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X17Y58 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.383 - ------------------------------------------------------------------- - slack 1.005 - -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X19Y59 FDCE f u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.012ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 0.965ns (logic 0.227ns (23.531%) route 0.738ns (76.469%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.045ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.531 0.389 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X19Y59 FDCE f u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.970 -0.338 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.530 - SLICE_X19Y59 FDCE (Remov_fdce_C_CLR) -0.092 -0.622 u_Axi_CDC/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.622 - arrival time 0.389 - ------------------------------------------------------------------- - slack 1.012 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.378ns (logic 0.186ns (13.499%) route 1.192ns (86.501%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.155ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.346ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.971 0.913 u_Axi_CDC/arFifo/popToPushGray_buffercc/p_0_in - SLICE_X14Y68 FDCE f u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.962 -0.346 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.309 - SLICE_X14Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.376 u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.376 - arrival time 0.913 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.290ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.356ns (logic 0.186ns (13.719%) route 1.170ns (86.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.157ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 0.949 0.891 u_Axi_CDC/arFifo/p_0_in - SLICE_X17Y66 FDCE f u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.964 -0.344 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1]/C - clock pessimism 0.037 -0.307 - SLICE_X17Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.399 u_Axi_CDC/arFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 0.399 - arrival time 0.891 - ------------------------------------------------------------------- - slack 1.290 - -Slack (MET) : 1.356ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0] - ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.356 - -Slack (MET) : 1.356ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1] - ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.356 - -Slack (MET) : 1.356ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2] - ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.356 - -Slack (MET) : 1.356ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[0] - ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.356 - -Slack (MET) : 1.356ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/p_0_in - SLICE_X14Y69 FDCE f u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X14Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.377 u_Axi_CDC/awFifo/pushCC_pushPtr_reg[1] - ------------------------------------------------------------------- - required time 0.377 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.356 - -Slack (MET) : 1.366ns (arrival time - required time) - Source: u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.358ns (logic 0.227ns (16.717%) route 1.131ns (83.283%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.059ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.324ns - Source Clock Delay (SCD): -0.575ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.687 -0.575 u_Axi_CDC/bFifo/bufferCC_12/cpu_clk - SLICE_X30Y58 FDCE r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X30Y58 FDCE (Prop_fdce_C_Q) 0.128 -0.447 r u_Axi_CDC/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.207 -0.241 u_Axi_CDC/bFifo/bufferCC_12/buffers_1 - SLICE_X28Y58 LUT1 (Prop_lut1_I0_O) 0.099 -0.142 f u_Axi_CDC/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__0/O - net (fo=30, routed) 0.924 0.783 u_Axi_CDC/rFifo/buffers_0_reg[3] - SLICE_X6Y74 FDCE f u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.984 -0.324 u_Axi_CDC/rFifo/cpu_clk - SLICE_X6Y74 FDCE r u_Axi_CDC/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.516 - SLICE_X6Y74 FDCE (Remov_fdce_C_CLR) -0.067 -0.583 u_Axi_CDC/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.583 - arrival time 0.783 - ------------------------------------------------------------------- - slack 1.366 - -Slack (MET) : 1.381ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.381 - -Slack (MET) : 1.381ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.381 - -Slack (MET) : 1.381ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.381 - -Slack (MET) : 1.381ns (arrival time - required time) - Source: pll_clk.u_rst_cpu/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (cpu_clk rise@0.000ns - cpu_clk rise@0.000ns) - Data Path Delay: 1.443ns (logic 0.186ns (12.888%) route 1.257ns (87.112%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.154ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.465ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.798 -0.465 pll_clk.u_rst_cpu/cpu_clk - SLICE_X0Y48 FDCE r pll_clk.u_rst_cpu/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y48 FDCE (Prop_fdce_C_Q) 0.141 -0.324 r pll_clk.u_rst_cpu/delay_reg[1]/Q - net (fo=1, routed) 0.221 -0.103 pll_clk.u_rst_cpu/cpu_resetn - SLICE_X0Y48 LUT1 (Prop_lut1_I0_O) 0.045 -0.058 f pll_clk.u_rst_cpu/reset_i_1/O - net (fo=40, routed) 1.036 0.978 u_Axi_CDC/awFifo/popToPushGray_buffercc/p_0_in - SLICE_X15Y69 FDCE f u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 0.961 -0.347 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.310 - SLICE_X15Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.402 u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.402 - arrival time 0.978 - ------------------------------------------------------------------- - slack 1.381 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.613ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.613ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.555ns (logic 0.227ns (40.925%) route 0.328ns (59.075%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.188 -0.027 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X28Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X28Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X28Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time -0.027 - ------------------------------------------------------------------- - slack 0.613 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.629ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.551ns (logic 0.227ns (41.209%) route 0.324ns (58.791%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.184 -0.031 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X27Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.214 -0.567 - SLICE_X27Y79 FDCE (Remov_fdce_C_CLR) -0.092 -0.659 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.659 - arrival time -0.031 - ------------------------------------------------------------------- - slack 0.629 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[14] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[22] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.728ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6]/C - clock pessimism -0.192 -0.573 - SLICE_X120Y68 FDCE (Remov_fdce_C_CLR) -0.067 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[6] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.728 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.741ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.682ns (logic 0.227ns (33.271%) route 0.455ns (66.729%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.356ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.316 0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/buffers_0_reg[2] - SLICE_X30Y78 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.952 -0.356 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/mlkem_clk - SLICE_X30Y78 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.548 - SLICE_X30Y78 FDCE (Remov_fdce_C_CLR) -0.092 -0.640 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/arFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.640 - arrival time 0.101 - ------------------------------------------------------------------- - slack 0.741 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.753ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.695ns (logic 0.186ns (26.771%) route 0.509ns (73.229%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.211 0.087 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9]/C - clock pessimism -0.192 -0.573 - SLICE_X121Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_byte_addr_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.087 - ------------------------------------------------------------------- - slack 0.753 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[12] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[16] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[20] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[24] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.772ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.692ns (logic 0.186ns (26.887%) route 0.506ns (73.113%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.208 0.084 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X119Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X119Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8]/C - clock pessimism -0.213 -0.595 - SLICE_X119Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[8] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.084 - ------------------------------------------------------------------- - slack 0.772 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0]/C - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[0] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.776ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.696ns (logic 0.186ns (26.719%) route 0.510ns (73.281%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.012ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.213 0.089 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4]/C - clock pessimism -0.213 -0.595 - SLICE_X118Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.687 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_byte_l_reg[4] - ------------------------------------------------------------------- - required time 0.687 - arrival time 0.089 - ------------------------------------------------------------------- - slack 0.776 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[10] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[11] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[8] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.741ns (logic 0.186ns (25.097%) route 0.555ns (74.903%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.034ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.381ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.258 0.134 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X123Y68 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.927 -0.381 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X123Y68 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9]/C - clock pessimism -0.192 -0.573 - SLICE_X123Y68 FDCE (Remov_fdce_C_CLR) -0.092 -0.665 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[9] - ------------------------------------------------------------------- - required time 0.665 - arrival time 0.134 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[11] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[19] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[27] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[28] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[30] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[3] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.799ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X120Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X120Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4]/C - clock pessimism -0.192 -0.574 - SLICE_X120Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.641 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wdata_reg[4] - ------------------------------------------------------------------- - required time 0.641 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.799 - -Slack (MET) : 0.824ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.765ns (logic 0.186ns (24.299%) route 0.579ns (75.701%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.282 0.158 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X121Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X121Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0]/C - clock pessimism -0.192 -0.574 - SLICE_X121Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_lane_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.158 - ------------------------------------------------------------------- - slack 0.824 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/buffers_1_reg - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.827ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.764ns (logic 0.227ns (29.725%) route 0.537ns (70.275%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.029ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.360ns - Source Clock Delay (SCD): -0.581ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.681 -0.581 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X25Y79 FDCE (Prop_fdce_C_Q) 0.128 -0.453 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.139 -0.314 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1 - SLICE_X25Y79 LUT1 (Prop_lut1_I0_O) 0.099 -0.215 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/popCC_popPtr[2]_i_2__1/O - net (fo=43, routed) 0.397 0.182 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X31Y74 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.948 -0.360 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/mlkem_clk - SLICE_X31Y74 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.552 - SLICE_X31Y74 FDCE (Remov_fdce_C_CLR) -0.092 -0.644 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.644 - arrival time 0.182 - ------------------------------------------------------------------- - slack 0.827 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0]/C - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_sync_reg[0] - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.860ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.779ns (logic 0.186ns (23.870%) route 0.593ns (76.130%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.011ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.383ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.213ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.296 0.172 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X118Y70 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.925 -0.383 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X118Y70 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg/C - clock pessimism -0.213 -0.596 - SLICE_X118Y70 FDCE (Remov_fdce_C_CLR) -0.092 -0.688 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/start_tg_reg - ------------------------------------------------------------------- - required time 0.688 - arrival time 0.172 - ------------------------------------------------------------------- - slack 0.860 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0]/C - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[0] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - -Slack (MET) : 0.868ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 0.809ns (logic 0.186ns (22.998%) route 0.623ns (77.002%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.033ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.382ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 0.325 0.201 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/pre_addr_l_reg[2]_rep__1_0 - SLICE_X122Y69 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.926 -0.382 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/mlkem_clk - SLICE_X122Y69 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1]/C - clock pessimism -0.192 -0.574 - SLICE_X122Y69 FDCE (Remov_fdce_C_CLR) -0.092 -0.666 u_fft_mlkem_axi_slave/u_mlkem_axi_slave/stream_wstrb_reg[1] - ------------------------------------------------------------------- - required time 0.666 - arrival time 0.201 - ------------------------------------------------------------------- - slack 0.868 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: mlkem_clk_clk_pll - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 2.861ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 2.861ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.351ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 0.216 - arrival time 2.645 - ------------------------------------------------------------------- - slack 2.861 - -Slack (MET) : 2.861ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 3.250ns (logic 0.187ns (5.753%) route 3.063ns (94.247%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.351ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.353ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 1.463 2.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/p_0_in - SLICE_X25Y79 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.955 -0.353 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/mlkem_clk - SLICE_X25Y79 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg/C - clock pessimism 0.099 -0.254 - clock uncertainty 0.197 -0.058 - SLICE_X25Y79 FDCE (Remov_fdce_C_CLR) -0.158 -0.216 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/awFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.216 - arrival time 2.645 - ------------------------------------------------------------------- - slack 2.861 - -Slack (MET) : 4.207ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[0]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.380ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[0]/C - clock pessimism 0.099 -0.281 - clock uncertainty 0.197 -0.085 - SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[0] - ------------------------------------------------------------------- - required time 0.243 - arrival time 3.964 - ------------------------------------------------------------------- - slack 4.207 - -Slack (MET) : 4.207ns (arrival time - required time) - Source: pll_clk.u_rst_sys/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_rst_mlkem/delay_reg[1]/CLR - (removal check against rising-edge clock mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (mlkem_clk_clk_pll rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 4.569ns (logic 0.187ns (4.093%) route 4.382ns (95.907%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.324ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.380ns - Source Clock Delay (SCD): -0.605ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r pll_clk.u_rst_sys/delay_reg[1]/Q - net (fo=115, routed) 1.600 1.136 pll_clk.u_rst_sys/Q[0] - SLICE_X14Y74 LUT1 (Prop_lut1_I0_O) 0.046 1.182 f pll_clk.u_rst_sys/bf2_do_en_i_1/O - net (fo=4130, routed) 2.782 3.964 pll_clk.u_rst_mlkem/p_0_in - SLICE_X118Y67 FDCE f pll_clk.u_rst_mlkem/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.928 -0.380 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - clock pessimism 0.099 -0.281 - clock uncertainty 0.197 -0.085 - SLICE_X118Y67 FDCE (Remov_fdce_C_CLR) -0.158 -0.243 pll_clk.u_rst_mlkem/delay_reg[1] - ------------------------------------------------------------------- - required time 0.243 - arrival time 3.964 - ------------------------------------------------------------------- - slack 4.207 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: mlkem_clk_clk_pll - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 2.991ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 2.991ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.365ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg - ------------------------------------------------------------------- - required time 0.138 - arrival time 2.853 - ------------------------------------------------------------------- - slack 2.991 - -Slack (MET) : 2.991ns (arrival time - required time) - Source: pll_clk.u_rst_mlkem/delay_reg[1]/C - (rising edge-triggered cell FDCE clocked by mlkem_clk_clk_pll {rise@0.000ns fall@20.000ns period=40.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - mlkem_clk_clk_pll rise@0.000ns) - Data Path Delay: 3.460ns (logic 0.186ns (5.375%) route 3.274ns (94.625%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.365ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.607ns - Clock Pessimism Removal (CPR): -0.099ns - Clock Uncertainty: 0.197ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.136ns - Phase Error (PE): 0.120ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock mlkem_clk_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT2) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/mlkem_clk_clk_pll - BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout3_buf/O - net (fo=26129, routed) 0.655 -0.607 pll_clk.u_rst_mlkem/mlkem_clk - SLICE_X118Y67 FDCE r pll_clk.u_rst_mlkem/delay_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X118Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.466 r pll_clk.u_rst_mlkem/delay_reg[1]/Q - net (fo=4, routed) 0.297 -0.169 pll_clk.u_rst_mlkem/Q[0] - SLICE_X118Y67 LUT1 (Prop_lut1_I0_O) 0.045 -0.124 f pll_clk.u_rst_mlkem/rdb_addr[11]_i_2/O - net (fo=1069, routed) 2.977 2.853 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_0_reg_0 - SLICE_X13Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - clock pessimism 0.099 -0.242 - clock uncertainty 0.197 -0.046 - SLICE_X13Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.138 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg - ------------------------------------------------------------------- - required time 0.138 - arrival time 2.853 - ------------------------------------------------------------------- - slack 2.991 - - - - - ---------------------------------------------------------------------------------------------------- -Path Group: **async_default** -From Clock: sys_clk - To Clock: sys_clk - -Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA -Hold : 0 Failing Endpoints, Worst Slack 0.479ns, Total Violation 0.000ns ---------------------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.479ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X14Y87 FDCE (Remov_fdce_C_CLR) -0.067 -0.622 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.622 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.479 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.504ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.427ns (logic 0.227ns (53.157%) route 0.200ns (46.843%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.341ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.147 -0.143 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y87 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.967 -0.341 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism -0.214 -0.555 - SLICE_X15Y87 FDCE (Remov_fdce_C_CLR) -0.092 -0.647 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.647 - arrival time -0.143 - ------------------------------------------------------------------- - slack 0.504 - -Slack (MET) : 0.524ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.468ns (logic 0.227ns (48.556%) route 0.241ns (51.444%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.036ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.187 -0.103 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X17Y86 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X17Y86 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3]/C - clock pessimism -0.192 -0.534 - SLICE_X17Y86 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.626 - arrival time -0.103 - ------------------------------------------------------------------- - slack 0.524 - -Slack (MET) : 0.548ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.470ns (logic 0.227ns (48.316%) route 0.243ns (51.684%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.014ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.189 -0.101 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X15Y85 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X15Y85 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.214 -0.556 - SLICE_X15Y85 FDCE (Remov_fdce_C_CLR) -0.092 -0.648 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.648 - arrival time -0.101 - ------------------------------------------------------------------- - slack 0.548 - -Slack (MET) : 0.558ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X14Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X14Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg/C - clock pessimism -0.214 -0.553 - SLICE_X14Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.620 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_addressGen_rValid_reg - ------------------------------------------------------------------- - required time 0.620 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.558 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.583ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.508ns (logic 0.227ns (44.714%) route 0.281ns (55.286%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.017ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.214ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.227 -0.063 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X15Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.214 -0.553 - SLICE_X15Y88 FDCE (Remov_fdce_C_CLR) -0.092 -0.645 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.645 - arrival time -0.063 - ------------------------------------------------------------------- - slack 0.583 - -Slack (MET) : 0.650ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.622ns (logic 0.227ns (36.501%) route 0.395ns (63.499%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.039ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.341 0.052 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X16Y88 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X16Y88 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3]/C - clock pessimism -0.192 -0.531 - SLICE_X16Y88 FDCE (Remov_fdce_C_CLR) -0.067 -0.598 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.598 - arrival time 0.052 - ------------------------------------------------------------------- - slack 0.650 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.800ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.055ns (logic 0.227ns (21.508%) route 0.828ns (78.492%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.546 0.514 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X5Y49 FDCE f u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X5Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.514 - ------------------------------------------------------------------- - slack 0.800 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.805ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.060ns (logic 0.227ns (21.419%) route 0.833ns (78.581%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.550 0.518 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X4Y49 FDCE f u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y49 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_1_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.518 - ------------------------------------------------------------------- - slack 0.805 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[0]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[1]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[2]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 0.859ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.114ns (logic 0.227ns (20.373%) route 0.887ns (79.627%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.347ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.231ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): -0.037ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.605 0.573 u_Axi_CDC/wFifo/buffers_0_reg[3] - SLICE_X4Y48 FDCE f u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.077 -0.231 u_Axi_CDC/wFifo/sys_clk - SLICE_X4Y48 FDCE r u_Axi_CDC/wFifo/popCC_popPtr_reg[3]/C - clock pessimism 0.037 -0.194 - SLICE_X4Y48 FDCE (Remov_fdce_C_CLR) -0.092 -0.286 u_Axi_CDC/wFifo/popCC_popPtr_reg[3] - ------------------------------------------------------------------- - required time 0.286 - arrival time 0.573 - ------------------------------------------------------------------- - slack 0.859 - -Slack (MET) : 1.001ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.546 - SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.638 - arrival time 0.363 - ------------------------------------------------------------------- - slack 1.001 - -Slack (MET) : 1.001ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 0.933ns (logic 0.227ns (24.323%) route 0.706ns (75.677%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.653 0.363 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/buffers_0_reg[3] - SLICE_X30Y80 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/sys_clk - SLICE_X30Y80 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.546 - SLICE_X30Y80 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/rFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.638 - arrival time 0.363 - ------------------------------------------------------------------- - slack 1.001 - -Slack (MET) : 1.086ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.001ns (logic 0.227ns (22.676%) route 0.774ns (77.324%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.007ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.342ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.491 0.460 u_Axi_CDC/awFifo/buffers_1_reg - SLICE_X15Y64 FDCE f u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.966 -0.342 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y64 FDCE r u_Axi_CDC/awFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.534 - SLICE_X15Y64 FDCE (Remov_fdce_C_CLR) -0.092 -0.626 u_Axi_CDC/awFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.626 - arrival time 0.460 - ------------------------------------------------------------------- - slack 1.086 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[0] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[1] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.139ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.070ns (logic 0.227ns (21.214%) route 0.843ns (78.786%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.023ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.355ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.790 0.500 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/buffers_1_reg - SLICE_X26Y72 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.953 -0.355 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/sys_clk - SLICE_X26Y72 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2]/C - clock pessimism -0.192 -0.547 - SLICE_X26Y72 FDCE (Remov_fdce_C_CLR) -0.092 -0.639 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/popCC_ptrToPush_reg[2] - ------------------------------------------------------------------- - required time 0.639 - arrival time 0.500 - ------------------------------------------------------------------- - slack 1.139 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[0] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.207ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.120ns (logic 0.227ns (20.264%) route 0.893ns (79.736%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.005ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.344ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.611 0.579 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X15Y66 FDCE f u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.964 -0.344 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2]/C - clock pessimism -0.192 -0.536 - SLICE_X15Y66 FDCE (Remov_fdce_C_CLR) -0.092 -0.628 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_1_reg[2] - ------------------------------------------------------------------- - required time 0.628 - arrival time 0.579 - ------------------------------------------------------------------- - slack 1.207 - -Slack (MET) : 1.256ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - clock pessimism -0.192 -0.546 - SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[1] - ------------------------------------------------------------------- - required time 0.638 - arrival time 0.618 - ------------------------------------------------------------------- - slack 1.256 - -Slack (MET) : 1.256ns (arrival time - required time) - Source: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.188ns (logic 0.227ns (19.107%) route 0.961ns (80.893%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.024ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.354ns - Source Clock Delay (SCD): -0.570ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.692 -0.570 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/sys_clk - SLICE_X13Y87 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y87 FDCE (Prop_fdce_C_Q) 0.128 -0.442 r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.053 -0.389 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/buffers_1 - SLICE_X13Y87 LUT1 (Prop_lut1_I0_O) 0.099 -0.290 f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/bufferCC_12/popCC_popPtr[2]_i_2__2/O - net (fo=30, routed) 0.908 0.618 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_1 - SLICE_X27Y71 FDCE f u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.954 -0.354 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/sys_clk - SLICE_X27Y71 FDCE r u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1]/C - clock pessimism -0.192 -0.546 - SLICE_X27Y71 FDCE (Remov_fdce_C_CLR) -0.092 -0.638 u_fft_mlkem_axi_slave/u_mlkem_axi_cdc/bFifo/pushToPopGray_buffercc/buffers_1_reg[1] - ------------------------------------------------------------------- - required time 0.638 - arrival time 0.618 - ------------------------------------------------------------------- - slack 1.256 - -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[0]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[0] - ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 - ------------------------------------------------------------------- - slack 1.359 - -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[1]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[1] - ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 - ------------------------------------------------------------------- - slack 1.359 - -Slack (MET) : 1.359ns (arrival time - required time) - Source: u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: **async_default** - Path Type: Removal (Min at Fast Process Corner) - Requirement: 0.000ns (sys_clk rise@0.000ns - sys_clk rise@0.000ns) - Data Path Delay: 1.294ns (logic 0.227ns (17.540%) route 1.067ns (82.460%)) - Logic Levels: 1 (LUT1=1) - Clock Path Skew: 0.002ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.347ns - Source Clock Delay (SCD): -0.541ns - Clock Pessimism Removal (CPR): 0.192ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_Axi_CDC/awFifo/bufferCC_12/sys_clk - SLICE_X7Y59 FDCE r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X7Y59 FDCE (Prop_fdce_C_Q) 0.128 -0.413 r u_Axi_CDC/awFifo/bufferCC_12/buffers_1_reg/Q - net (fo=1, routed) 0.283 -0.131 u_Axi_CDC/awFifo/bufferCC_12/buffers_1 - SLICE_X7Y59 LUT1 (Prop_lut1_I0_O) 0.099 -0.032 f u_Axi_CDC/awFifo/bufferCC_12/popCC_popPtr[2]_i_2/O - net (fo=43, routed) 0.785 0.753 u_Axi_CDC/arFifo/buffers_0_reg[2] - SLICE_X12Y69 FDCE f u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.961 -0.347 u_Axi_CDC/arFifo/sys_clk - SLICE_X12Y69 FDCE r u_Axi_CDC/arFifo/popCC_popPtr_reg[2]/C - clock pessimism -0.192 -0.539 - SLICE_X12Y69 FDCE (Remov_fdce_C_CLR) -0.067 -0.606 u_Axi_CDC/arFifo/popCC_popPtr_reg[2] - ------------------------------------------------------------------- - required time 0.606 - arrival time 0.753 - ------------------------------------------------------------------- - slack 1.359 - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: sys_clk - To Clock: cpu_clk - -Max Delay 0 Endpoints -Min Delay 59 Endpoints --------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.686ns (logic 0.418ns (60.951%) route 0.268ns (39.049%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.268 -1.332 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[0] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.622ns (logic 0.367ns (58.974%) route 0.255ns (41.026%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=2, routed) 0.255 -1.321 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[2] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.623ns (logic 0.367ns (58.905%) route 0.256ns (41.095%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.256 -1.320 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[0] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.720ns (logic 0.337ns (46.825%) route 0.383ns (53.175%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X15Y70 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.383 -1.299 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[2] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.743ns (logic 0.367ns (49.384%) route 0.376ns (50.616%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.376 -1.275 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[1] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.842ns (logic 0.418ns (49.650%) route 0.424ns (50.350%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/awFifo/sys_clk - SLICE_X16Y69 FDCE r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X16Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.424 -1.176 u_Axi_CDC/awFifo/popToPushGray_buffercc/D[1] - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.935 -2.407 u_Axi_CDC/awFifo/popToPushGray_buffercc/cpu_clk - SLICE_X15Y69 FDCE r u_Axi_CDC/awFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.843ns (logic 0.337ns (39.996%) route 0.506ns (60.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.337 -1.681 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.506 -1.176 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[2] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.782ns (logic 0.367ns (46.956%) route 0.415ns (53.044%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.335ns - Source Clock Delay (SCD): -1.943ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.367 -1.576 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.415 -1.162 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0[1] - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.007 -2.335 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y76 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.630ns (logic 0.367ns (58.287%) route 0.263ns (41.713%)) - Logic Levels: 0 - Clock Path Skew: -0.564ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.316ns - Source Clock Delay (SCD): -1.752ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.263 -1.122 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[3] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.632ns (logic 0.367ns (58.089%) route 0.265ns (41.911%)) - Logic Levels: 0 - Clock Path Skew: -0.377ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.129ns - Source Clock Delay (SCD): -1.752ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.265 -1.120 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[0] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.922ns (logic 0.367ns (39.803%) route 0.555ns (60.197%)) - Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.555 -1.095 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[0] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.888ns (logic 0.337ns (37.964%) route 0.551ns (62.036%)) - Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.943ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.885 -1.943 u_Axi_CDC/rFifo/sys_clk - SLICE_X5Y77 FDCE r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y77 FDCE (Prop_fdce_C_Q) 0.337 -1.606 r u_Axi_CDC/rFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=4, routed) 0.551 -1.056 u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]_0 - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.005 -2.337 u_Axi_CDC/rFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X5Y75 FDCE r u_Axi_CDC/rFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.075ns (logic 0.518ns (48.184%) route 0.557ns (51.816%)) - Logic Levels: 1 (LUT5=1) - Clock Path Skew: -0.382ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.498ns - Source Clock Delay (SCD): -2.115ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.713 -2.115 u_snix_axil_cdma_mux_8ch/sys_clk - SLICE_X56Y62 FDRE r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X56Y62 FDRE (Prop_fdre_C_Q) 0.418 -1.697 r u_snix_axil_cdma_mux_8ch/ch_done_reg[2]/Q - net (fo=3, routed) 0.557 -1.140 u_snix_axil_cdma_mux_8ch/ch_done_reg[2]_0 - SLICE_X57Y58 LUT5 (Prop_lut5_I3_O) 0.100 -1.040 r u_snix_axil_cdma_mux_8ch/csr_estat[3]_i_1/O - net (fo=1, routed) 0.000 -1.040 u_cpu/u_csr/interrupt[1] - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.844 -2.498 u_cpu/u_csr/cpu_clk - SLICE_X57Y58 FDRE r u_cpu/u_csr/csr_estat_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.742ns (logic 0.367ns (49.468%) route 0.375ns (50.532%)) - Logic Levels: 0 - Clock Path Skew: -0.377ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.129ns - Source Clock Delay (SCD): -1.752ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.385 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.375 -1.010 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[1] - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.213 -2.129 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X0Y49 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.025ns (logic 0.337ns (32.867%) route 0.688ns (67.133%)) - Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.337 -1.680 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.688 -0.992 u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.073ns (logic 0.367ns (34.191%) route 0.706ns (65.809%)) - Logic Levels: 0 - Clock Path Skew: -0.379ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.811 -2.017 u_Axi_CDC/bFifo/sys_clk - SLICE_X19Y68 FDCE r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y68 FDCE (Prop_fdce_C_Q) 0.367 -1.650 r u_Axi_CDC/bFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.706 -0.944 u_Axi_CDC/bFifo/pushToPopGray_buffercc/Q[1] - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.945 -2.397 u_Axi_CDC/bFifo/pushToPopGray_buffercc/cpu_clk - SLICE_X19Y59 FDCE r u_Axi_CDC/bFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.147ns (logic 0.367ns (31.992%) route 0.780ns (68.008%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.406ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.810 -2.018 u_Axi_CDC/arFifo/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X13Y69 FDCE (Prop_fdce_C_Q) 0.367 -1.651 r u_Axi_CDC/arFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.780 -0.871 u_Axi_CDC/arFifo/popToPushGray_buffercc/D[0] - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.936 -2.406 u_Axi_CDC/arFifo/popToPushGray_buffercc/cpu_clk - SLICE_X14Y68 FDCE r u_Axi_CDC/arFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.043ns (logic 0.337ns (32.302%) route 0.706ns (67.698%)) - Logic Levels: 0 - Clock Path Skew: -0.564ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.316ns - Source Clock Delay (SCD): -1.752ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.077 -1.752 u_Axi_CDC/wFifo/sys_clk - SLICE_X5Y49 FDCE r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.415 r u_Axi_CDC/wFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.706 -0.708 u_Axi_CDC/wFifo/popToPushGray_buffercc/Q[2] - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.026 -2.316 u_Axi_CDC/wFifo/popToPushGray_buffercc/cpu_clk - SLICE_X6Y50 FDCE r u_Axi_CDC/wFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_matmul_axi_slave/done_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.754ns (logic 0.418ns (23.829%) route 1.336ns (76.171%)) - Logic Levels: 0 - Clock Path Skew: -0.104ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.228ns - Source Clock Delay (SCD): -2.123ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.705 -2.123 u_matmul_axi_slave/sys_clk - SLICE_X46Y72 FDRE r u_matmul_axi_slave/done_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X46Y72 FDRE (Prop_fdre_C_Q) 0.418 -1.705 r u_matmul_axi_slave/done_reg/Q - net (fo=12, routed) 1.336 -0.369 u_cpu/u_csr/interrupt[2] - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.114 -2.228 u_cpu/u_csr/cpu_clk - SLICE_X41Y40 FDRE r u_cpu/u_csr/csr_estat_reg[4]/C - -Slack: inf - Source: u_confreg/int_out_or_q2_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_cpu/u_csr/csr_estat_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.063ns (logic 0.367ns (17.786%) route 1.696ns (82.214%)) - Logic Levels: 0 - Clock Path Skew: -0.223ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.231ns - Source Clock Delay (SCD): -2.007ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.821 -2.007 u_confreg/sys_clk - SLICE_X11Y58 FDRE r u_confreg/int_out_or_q2_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X11Y58 FDRE (Prop_fdre_C_Q) 0.367 -1.640 r u_confreg/int_out_or_q2_reg/Q - net (fo=1, routed) 1.696 0.056 u_cpu/u_csr/interrupt[0] - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.111 -2.231 u_cpu/u_csr/cpu_clk - SLICE_X30Y30 FDRE r u_cpu/u_csr/csr_estat_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.149ns (logic 1.078ns (50.163%) route 1.071ns (49.837%)) - Logic Levels: 0 - Clock Path Skew: -0.371ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC/O - net (fo=1, routed) 1.071 0.127 u_Axi_CDC/rFifo/_zz_ram_port10__2[4] - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y52 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[4]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.153ns (logic 1.062ns (49.332%) route 1.091ns (50.668%)) - Logic Levels: 0 - Clock Path Skew: -0.376ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.398ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_36_39/WCLK - SLICE_X16Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_36_39/RAMB_D1/O - net (fo=1, routed) 1.091 0.131 u_Axi_CDC/rFifo/_zz_ram_port10__2[39] - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.944 -2.398 u_Axi_CDC/rFifo/cpu_clk - SLICE_X13Y61 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[39]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.174ns (logic 1.056ns (48.570%) route 1.118ns (51.430%)) - Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA_D1/O - net (fo=1, routed) 1.118 0.150 u_Axi_CDC/rFifo/_zz_ram_port10__2[31] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.202ns (logic 1.078ns (48.964%) route 1.124ns (51.036%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.946 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC/O - net (fo=1, routed) 1.124 0.177 u_Axi_CDC/rFifo/_zz_ram_port10__2[16] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[16]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.203ns (logic 1.083ns (49.171%) route 1.120ns (50.829%)) - Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMB/O - net (fo=1, routed) 1.120 0.178 u_Axi_CDC/rFifo/_zz_ram_port10__2[32] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[32]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.208ns (logic 1.083ns (49.047%) route 1.125ns (50.953%)) - Logic Levels: 0 - Clock Path Skew: -0.370ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.395ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB/O - net (fo=1, routed) 1.125 0.184 u_Axi_CDC/rFifo/_zz_ram_port10__2[14] - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y53 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[14]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.216ns (logic 1.078ns (48.649%) route 1.138ns (51.351%)) - Logic Levels: 0 - Clock Path Skew: -0.372ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC/O - net (fo=1, routed) 1.138 0.195 u_Axi_CDC/rFifo/_zz_ram_port10__2[28] - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[28]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.231ns (logic 1.056ns (47.336%) route 1.175ns (52.664%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA_D1/O - net (fo=1, routed) 1.175 0.207 u_Axi_CDC/rFifo/_zz_ram_port10__2[13] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[13]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.300ns (logic 1.056ns (45.907%) route 1.244ns (54.093%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.966 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA_D1/O - net (fo=1, routed) 1.244 0.278 u_Axi_CDC/rFifo/_zz_ram_port10__2[1] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.329ns (logic 1.084ns (46.543%) route 1.245ns (53.457%)) - Logic Levels: 0 - Clock Path Skew: -0.369ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.394ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMA/O - net (fo=1, routed) 1.245 0.305 u_Axi_CDC/rFifo/_zz_ram_port10__2[12] - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.948 -2.394 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y50 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[12]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.337ns (logic 1.059ns (45.323%) route 1.278ns (54.677%)) - Logic Levels: 0 - Clock Path Skew: -0.373ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.395ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMC_D1/O - net (fo=1, routed) 1.278 0.315 u_Axi_CDC/rFifo/_zz_ram_port10__2[29] - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.947 -2.395 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y54 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[29]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.340ns (logic 1.059ns (45.262%) route 1.281ns (54.738%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.963 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMC_D1/O - net (fo=1, routed) 1.281 0.317 u_Axi_CDC/rFifo/_zz_ram_port10__2[5] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.340ns (logic 1.056ns (45.123%) route 1.284ns (54.877%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA_D1/O - net (fo=1, routed) 1.284 0.319 u_Axi_CDC/rFifo/_zz_ram_port10__2[7] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.349ns (logic 1.084ns (46.148%) route 1.265ns (53.852%)) - Logic Levels: 0 - Clock Path Skew: -0.183ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_30_35/WCLK - SLICE_X14Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/rFifo/ram_reg_0_7_30_35/RAMA/O - net (fo=1, routed) 1.265 0.325 u_Axi_CDC/rFifo/_zz_ram_port10__2[30] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[30]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.378ns (logic 1.083ns (45.550%) route 1.295ns (54.450%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB/O - net (fo=1, routed) 1.295 0.355 u_Axi_CDC/rFifo/_zz_ram_port10__2[2] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.380ns (logic 1.062ns (44.630%) route 1.318ns (55.370%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.960 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMB_D1/O - net (fo=1, routed) 1.318 0.357 u_Axi_CDC/rFifo/_zz_ram_port10__2[3] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.383ns (logic 1.062ns (44.564%) route 1.321ns (55.436%)) - Logic Levels: 0 - Clock Path Skew: -0.186ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.208ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB_D1/O - net (fo=1, routed) 1.321 0.362 u_Axi_CDC/rFifo/_zz_ram_port10__2[27] - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.134 -2.208 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y48 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[27]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.393ns (logic 1.062ns (44.383%) route 1.331ns (55.617%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB_D1/O - net (fo=1, routed) 1.331 0.372 u_Axi_CDC/rFifo/_zz_ram_port10__2[9] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[9]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.414ns (logic 1.083ns (44.858%) route 1.331ns (55.142%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.939 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMB/O - net (fo=1, routed) 1.331 0.392 u_Axi_CDC/rFifo/_zz_ram_port10__2[20] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[20]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.434ns (logic 1.062ns (43.637%) route 1.372ns (56.363%)) - Logic Levels: 0 - Clock Path Skew: -0.185ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.804 -2.024 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.962 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMB_D1/O - net (fo=1, routed) 1.372 0.409 u_Axi_CDC/rFifo/_zz_ram_port10__2[15] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[15]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.441ns (logic 1.078ns (44.167%) route 1.363ns (55.833%)) - Logic Levels: 0 - Clock Path Skew: -0.187ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.944 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC/O - net (fo=1, routed) 1.363 0.418 u_Axi_CDC/rFifo/_zz_ram_port10__2[22] - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y49 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[22]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.491ns (logic 1.083ns (43.479%) route 1.408ns (56.521%)) - Logic Levels: 0 - Clock Path Skew: -0.190ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMB/O - net (fo=1, routed) 1.408 0.470 u_Axi_CDC/rFifo/_zz_ram_port10__2[8] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.529ns (logic 1.056ns (41.755%) route 1.473ns (58.245%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMA_D1/O - net (fo=1, routed) 1.473 0.508 u_Axi_CDC/rFifo/_zz_ram_port10__2[25] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[25]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.538ns (logic 1.084ns (42.711%) route 1.454ns (57.289%)) - Logic Levels: 0 - Clock Path Skew: -0.188ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.210ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.937 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMA/O - net (fo=1, routed) 1.454 0.517 u_Axi_CDC/rFifo/_zz_ram_port10__2[6] - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.132 -2.210 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y47 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.565ns (logic 1.078ns (42.030%) route 1.487ns (57.970%)) - Logic Levels: 0 - Clock Path Skew: -0.190ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.807 -2.021 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC/O - net (fo=1, routed) 1.487 0.544 u_Axi_CDC/rFifo/_zz_ram_port10__2[10] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 2.570ns (logic 1.084ns (42.178%) route 1.486ns (57.822%)) - Logic Levels: 0 - Clock Path Skew: -0.189ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.212ns - Source Clock Delay (SCD): -2.022ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.806 -2.022 u_Axi_CDC/rFifo/ram_reg_0_7_0_5/WCLK - SLICE_X18Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y76 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.938 r u_Axi_CDC/rFifo/ram_reg_0_7_0_5/RAMA/O - net (fo=1, routed) 1.486 0.548 u_Axi_CDC/rFifo/_zz_ram_port10__2[0] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.130 -2.212 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.131ns (logic 0.386ns (34.129%) route 0.745ns (65.871%)) - Logic Levels: 0 - Clock Path Skew: 0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.579ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.683 -0.579 u_Axi_CDC/rFifo/ram_reg_0_7_18_23/WCLK - SLICE_X16Y76 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y76 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.193 r u_Axi_CDC/rFifo/ram_reg_0_7_18_23/RAMC_D1/O - net (fo=1, routed) 0.745 0.552 u_Axi_CDC/rFifo/_zz_ram_port10__2[23] - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk - SLICE_X17Y44 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[23]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.175ns (logic 0.386ns (32.837%) route 0.789ns (67.163%)) - Logic Levels: 0 - Clock Path Skew: 0.314ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.263ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_6_11/WCLK - SLICE_X18Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.191 r u_Axi_CDC/rFifo/ram_reg_0_7_6_11/RAMC_D1/O - net (fo=1, routed) 0.789 0.598 u_Axi_CDC/rFifo/_zz_ram_port10__2[11] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[11]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.178ns (logic 0.394ns (33.456%) route 0.784ns (66.544%)) - Logic Levels: 0 - Clock Path Skew: 0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.262ns - Source Clock Delay (SCD): -0.577ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.685 -0.577 u_Axi_CDC/rFifo/ram_reg_0_7_24_29/WCLK - SLICE_X14Y77 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X14Y77 RAMD32 (Prop_ramd32_CLK_O) - 0.394 -0.183 r u_Axi_CDC/rFifo/ram_reg_0_7_24_29/RAMB/O - net (fo=1, routed) 0.784 0.600 u_Axi_CDC/rFifo/_zz_ram_port10__2[26] - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.046 -0.262 u_Axi_CDC/rFifo/cpu_clk - SLICE_X15Y41 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[26]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - (rising edge-triggered cell FDRE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.182ns (logic 0.386ns (32.666%) route 0.796ns (67.334%)) - Logic Levels: 0 - Clock Path Skew: 0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.263ns - Source Clock Delay (SCD): -0.580ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.682 -0.580 u_Axi_CDC/rFifo/ram_reg_0_7_12_17/WCLK - SLICE_X18Y75 RAMD32 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y75 RAMD32 (Prop_ramd32_CLK_O) - 0.386 -0.194 r u_Axi_CDC/rFifo/ram_reg_0_7_12_17/RAMC_D1/O - net (fo=1, routed) 0.796 0.601 u_Axi_CDC/rFifo/_zz_ram_port10__2[17] - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.045 -0.263 u_Axi_CDC/rFifo/cpu_clk - SLICE_X19Y42 FDRE r u_Axi_CDC/rFifo/_zz_ram_port1_reg[17]/C - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: cpu_clk - To Clock: sys_clk - -Max Delay 0 Endpoints -Min Delay 162 Endpoints --------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.597ns (logic 0.337ns (56.456%) route 0.260ns (43.544%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.337 -1.671 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[2]/Q - net (fo=2, routed) 0.260 -1.411 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[2] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.617ns (logic 0.337ns (54.608%) route 0.280ns (45.392%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.337 -1.677 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.280 -1.397 u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.634ns (logic 0.367ns (57.910%) route 0.267ns (42.090%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.267 -1.381 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[0] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.654ns (logic 0.385ns (58.892%) route 0.269ns (41.108%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.385 -1.633 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=4, routed) 0.269 -1.365 u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]_0 - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.621ns (logic 0.337ns (54.306%) route 0.284ns (45.694%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.946ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.337 -1.609 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[2]/Q - net (fo=1, routed) 0.284 -1.326 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[2] - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.736ns (logic 0.367ns (49.854%) route 0.369ns (50.146%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X19Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X19Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[0]/Q - net (fo=2, routed) 0.369 -1.272 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[0] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.740ns (logic 0.367ns (49.584%) route 0.373ns (50.416%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/bFifo/cpu_clk - SLICE_X17Y58 FDCE r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y58 FDCE (Prop_fdce_C_Q) 0.367 -1.641 r u_Axi_CDC/bFifo/popCC_ptrToPush_reg[1]/Q - net (fo=2, routed) 0.373 -1.268 u_Axi_CDC/bFifo/popToPushGray_buffercc/D[1] - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/bFifo/popToPushGray_buffercc/sys_clk - SLICE_X17Y59 FDCE r u_Axi_CDC/bFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.792ns (logic 0.367ns (46.311%) route 0.425ns (53.689%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.014ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.814 -2.014 u_Axi_CDC/arFifo/cpu_clk - SLICE_X17Y66 FDCE r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X17Y66 FDCE (Prop_fdce_C_Q) 0.367 -1.647 r u_Axi_CDC/arFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.425 -1.222 u_Axi_CDC/arFifo/pushToPopGray_buffercc/Q[1] - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/arFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y66 FDCE r u_Axi_CDC/arFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.817ns (logic 0.418ns (51.164%) route 0.399ns (48.836%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.399 -1.201 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[0] - SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X13Y69 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.833ns (logic 0.418ns (50.157%) route 0.415ns (49.843%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/cpu_clk - SLICE_X14Y69 FDCE r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X14Y69 FDCE (Prop_fdce_C_Q) 0.418 -1.600 r u_Axi_CDC/awFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.415 -1.185 u_Axi_CDC/awFifo/pushToPopGray_buffercc/Q[1] - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/awFifo/pushToPopGray_buffercc/sys_clk - SLICE_X15Y70 FDCE r u_Axi_CDC/awFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.793ns (logic 0.367ns (46.283%) route 0.426ns (53.717%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.337ns - Source Clock Delay (SCD): -1.946ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[3]/Q - net (fo=1, routed) 0.426 -1.153 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[3] - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.005 -2.337 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y75 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.632ns (logic 0.337ns (53.354%) route 0.295ns (46.646%)) - Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.337 -1.413 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[3]/Q - net (fo=5, routed) 0.295 -1.118 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[3] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.641ns (logic 0.367ns (57.215%) route 0.274ns (42.785%)) - Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[1]/Q - net (fo=2, routed) 0.274 -1.108 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[1] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.928ns (logic 0.367ns (39.555%) route 0.561ns (60.445%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.334ns - Source Clock Delay (SCD): -1.946ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[1]/Q - net (fo=1, routed) 0.561 -1.018 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[1] - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.770ns (logic 0.367ns (47.632%) route 0.403ns (52.368%)) - Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[2]/Q - net (fo=3, routed) 0.403 -0.979 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[2] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.000ns (logic 0.367ns (36.693%) route 0.633ns (63.307%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.334ns - Source Clock Delay (SCD): -1.946ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.882 -1.946 u_Axi_CDC/rFifo/cpu_clk - SLICE_X5Y74 FDCE r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X5Y74 FDCE (Prop_fdce_C_Q) 0.367 -1.579 r u_Axi_CDC/rFifo/popCC_ptrToPush_reg[0]/Q - net (fo=1, routed) 0.633 -0.946 u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[3]_0[0] - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.008 -2.334 u_Axi_CDC/rFifo/popToPushGray_buffercc/sys_clk - SLICE_X4Y77 FDCE r u_Axi_CDC/rFifo/popToPushGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C - (rising edge-triggered cell FDCE clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 0.892ns (logic 0.367ns (41.149%) route 0.525ns (58.851%)) - Logic Levels: 0 - Clock Path Skew: -0.381ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.131ns - Source Clock Delay (SCD): -1.750ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 2.079 -1.750 u_Axi_CDC/wFifo/cpu_clk - SLICE_X3Y49 FDCE r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y49 FDCE (Prop_fdce_C_Q) 0.367 -1.383 r u_Axi_CDC/wFifo/pushCC_pushPtrGray_reg[0]/Q - net (fo=2, routed) 0.525 -0.858 u_Axi_CDC/wFifo/pushToPopGray_buffercc/D[0] - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 2.211 -2.131 u_Axi_CDC/wFifo/pushToPopGray_buffercc/sys_clk - SLICE_X4Y49 FDCE r u_Axi_CDC/wFifo/pushToPopGray_buffercc/buffers_0_reg[0]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.215ns (logic 1.056ns (86.901%) route 0.159ns (13.099%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.953 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMA_D1/O - net (fo=1, routed) 0.159 -0.794 u_Axi_CDC/awFifo/_zz_ram_port10[1] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[1]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.218ns (logic 1.059ns (86.968%) route 0.159ns (13.032%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.950 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMC_D1/O - net (fo=1, routed) 0.159 -0.792 u_Axi_CDC/awFifo/_zz_ram_port10[5] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[5]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.399ns - Source Clock Delay (SCD): -2.011ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.949 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMB_D1/O - net (fo=1, routed) 0.159 -0.791 u_Axi_CDC/awFifo/_zz_ram_port10[45] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[45]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.221ns (logic 1.062ns (86.996%) route 0.159ns (13.004%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.397ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.947 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 0.159 -0.789 u_Axi_CDC/awFifo/_zz_ram_port10[3] - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.945 -2.397 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.940 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA/O - net (fo=1, routed) 0.162 -0.778 u_Axi_CDC/arFifo/_zz_ram_port10__1[6] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[6]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.934 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA/O - net (fo=1, routed) 0.162 -0.772 u_Axi_CDC/arFifo/_zz_ram_port10__1[48] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[48]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.245ns (logic 1.083ns (86.954%) route 0.162ns (13.046%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.015ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.932 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMB/O - net (fo=1, routed) 0.162 -0.770 u_Axi_CDC/arFifo/_zz_ram_port10__1[44] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[44]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.246ns (logic 1.084ns (86.999%) route 0.162ns (13.001%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.015ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.813 -2.015 u_Axi_CDC/arFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y67 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.084 -0.931 r u_Axi_CDC/arFifo/ram_reg_0_3_42_47/RAMA/O - net (fo=1, routed) 0.162 -0.769 u_Axi_CDC/arFifo/_zz_ram_port10__1[42] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[42]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.329ns (logic 1.078ns (81.137%) route 0.251ns (18.863%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.946 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMC/O - net (fo=1, routed) 0.251 -0.696 u_Axi_CDC/arFifo/_zz_ram_port10__1[10] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[10]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.340ns (logic 1.062ns (79.263%) route 0.278ns (20.737%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB_D1/O - net (fo=1, routed) 0.278 -0.684 u_Axi_CDC/arFifo/_zz_ram_port10__1[3] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[3]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.338ns (logic 1.059ns (79.147%) route 0.279ns (20.853%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.962 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC_D1/O - net (fo=1, routed) 0.279 -0.683 u_Axi_CDC/awFifo/_zz_ram_port10[53] - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[53]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.334ns (logic 1.056ns (79.142%) route 0.278ns (20.858%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.404ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.278 -0.683 u_Axi_CDC/arFifo/_zz_ram_port10__1[37] - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.938 -2.404 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y67 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[37]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.340ns (logic 1.062ns (79.249%) route 0.278ns (20.751%)) - Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.412ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.956 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMB_D1/O - net (fo=1, routed) 0.278 -0.678 u_Axi_CDC/arFifo/_zz_ram_port10__1[51] - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[51]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.337ns (logic 1.056ns (79.009%) route 0.281ns (20.991%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.403ns - Source Clock Delay (SCD): -2.013ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.957 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMA_D1/O - net (fo=1, routed) 0.281 -0.677 u_Axi_CDC/awFifo/_zz_ram_port10[37] - SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.939 -2.403 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y66 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[37]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.360ns (logic 1.078ns (79.282%) route 0.282ns (20.718%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.943 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMC/O - net (fo=1, routed) 0.282 -0.662 u_Axi_CDC/awFifo/_zz_ram_port10[52] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[52]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.364ns (logic 1.083ns (79.398%) route 0.281ns (20.602%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.398ns - Source Clock Delay (SCD): -2.009ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.819 -2.009 u_Axi_CDC/awFifo/ram_reg_0_3_0_5/WCLK - SLICE_X20Y58 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X20Y58 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.926 r u_Axi_CDC/awFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.281 -0.645 u_Axi_CDC/awFifo/_zz_ram_port10[2] - SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.944 -2.398 u_Axi_CDC/awFifo/sys_clk - SLICE_X21Y59 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.411ns (logic 1.062ns (75.266%) route 0.349ns (24.734%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.402ns - Source Clock Delay (SCD): -2.013ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.951 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMB_D1/O - net (fo=1, routed) 0.349 -0.602 u_Axi_CDC/awFifo/_zz_ram_port10[39] - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[39]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.432ns (logic 1.083ns (75.645%) route 0.349ns (24.355%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.396ns - Source Clock Delay (SCD): -2.008ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.820 -2.008 u_Axi_CDC/awFifo/ram_reg_0_3_6_11/WCLK - SLICE_X16Y57 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y57 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.925 r u_Axi_CDC/awFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 0.349 -0.577 u_Axi_CDC/awFifo/_zz_ram_port10[8] - SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.946 -2.396 u_Axi_CDC/awFifo/sys_clk - SLICE_X15Y58 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.451ns (logic 1.056ns (72.768%) route 0.395ns (27.232%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.965 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.395 -0.570 u_Axi_CDC/awFifo/_zz_ram_port10[49] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[49]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.454ns (logic 1.062ns (73.041%) route 0.392ns (26.959%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.410ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB_D1/O - net (fo=1, routed) 0.392 -0.567 u_Axi_CDC/awFifo/_zz_ram_port10[51] - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.932 -2.410 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y70 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[51]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.454ns (logic 1.059ns (72.851%) route 0.395ns (27.149%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.959 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMC_D1/O - net (fo=1, routed) 0.395 -0.565 u_Axi_CDC/awFifo/_zz_ram_port10[35] - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[35]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.453ns (logic 1.056ns (72.668%) route 0.397ns (27.332%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.961 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMA_D1/O - net (fo=1, routed) 0.397 -0.564 u_Axi_CDC/arFifo/_zz_ram_port10__1[31] - SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X16Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[31]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.457ns (logic 1.062ns (72.904%) route 0.395ns (27.096%)) - Logic Levels: 0 - Clock Path Skew: -0.390ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/awFifo/ram_reg_0_3_30_35/WCLK - SLICE_X22Y67 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y67 RAMD32 (Prop_ramd32_CLK_O) - 1.062 -0.956 r u_Axi_CDC/awFifo/ram_reg_0_3_30_35/RAMB_D1/O - net (fo=1, routed) 0.395 -0.562 u_Axi_CDC/awFifo/_zz_ram_port10[33] - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y69 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[33]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.482ns (logic 1.083ns (73.069%) route 0.399ns (26.931%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMB/O - net (fo=1, routed) 0.399 -0.542 u_Axi_CDC/arFifo/_zz_ram_port10__1[8] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[8]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.482ns (logic 1.083ns (73.083%) route 0.399ns (26.917%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.021ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.807 -2.021 u_Axi_CDC/awFifo/ram_reg_0_3_48_53/WCLK - SLICE_X22Y69 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X22Y69 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.938 r u_Axi_CDC/awFifo/ram_reg_0_3_48_53/RAMB/O - net (fo=1, routed) 0.399 -0.539 u_Axi_CDC/awFifo/_zz_ram_port10[50] - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/awFifo/sys_clk - SLICE_X23Y71 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[50]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.479ns (logic 1.078ns (72.907%) route 0.401ns (27.093%)) - Logic Levels: 0 - Clock Path Skew: -0.391ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.409ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_30_35/WCLK - SLICE_X16Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.078 -0.939 r u_Axi_CDC/arFifo/ram_reg_0_3_30_35/RAMC/O - net (fo=1, routed) 0.401 -0.539 u_Axi_CDC/arFifo/_zz_ram_port10__1[34] - SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.933 -2.409 u_Axi_CDC/arFifo/sys_clk - SLICE_X17Y71 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[34]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%)) - Logic Levels: 0 - Clock Path Skew: -0.386ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.411ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_6_11/WCLK - SLICE_X36Y60 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y60 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.968 r u_Axi_CDC/arFifo/ram_reg_0_3_6_11/RAMA_D1/O - net (fo=1, routed) 0.437 -0.532 u_Axi_CDC/arFifo/_zz_ram_port10__1[7] - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.931 -2.411 u_Axi_CDC/arFifo/sys_clk - SLICE_X37Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[7]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.056ns (70.750%) route 0.437ns (29.250%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.408ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.056 -0.962 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMA_D1/O - net (fo=1, routed) 0.437 -0.526 u_Axi_CDC/arFifo/_zz_ram_port10__1[49] - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.934 -2.408 u_Axi_CDC/arFifo/sys_clk - SLICE_X19Y70 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[49]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.496ns (logic 1.059ns (70.775%) route 0.437ns (29.225%)) - Logic Levels: 0 - Clock Path Skew: -0.393ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.412ns - Source Clock Delay (SCD): -2.018ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.810 -2.018 u_Axi_CDC/arFifo/ram_reg_0_3_48_53/WCLK - SLICE_X18Y70 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y70 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.959 r u_Axi_CDC/arFifo/ram_reg_0_3_48_53/RAMC_D1/O - net (fo=1, routed) 0.437 -0.522 u_Axi_CDC/arFifo/_zz_ram_port10__1[53] - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.930 -2.412 u_Axi_CDC/arFifo/sys_clk - SLICE_X18Y72 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[53]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.497ns (logic 1.059ns (70.746%) route 0.438ns (29.254%)) - Logic Levels: 0 - Clock Path Skew: -0.389ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.017ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.811 -2.017 u_Axi_CDC/arFifo/ram_reg_0_3_36_41/WCLK - SLICE_X18Y68 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y68 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.958 r u_Axi_CDC/arFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.438 -0.520 u_Axi_CDC/arFifo/_zz_ram_port10__1[41] - SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk - SLICE_X20Y68 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[41]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.493ns (logic 1.059ns (70.929%) route 0.434ns (29.071%)) - Logic Levels: 0 - Clock Path Skew: -0.387ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.399ns - Source Clock Delay (SCD): -2.011ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.817 -2.011 u_Axi_CDC/awFifo/ram_reg_0_3_42_47/WCLK - SLICE_X18Y62 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X18Y62 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.952 r u_Axi_CDC/awFifo/ram_reg_0_3_42_47/RAMC_D1/O - net (fo=1, routed) 0.434 -0.518 u_Axi_CDC/awFifo/_zz_ram_port10[47] - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.943 -2.399 u_Axi_CDC/awFifo/sys_clk - SLICE_X19Y62 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[47]/C - -Slack: inf - Source: u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.511ns (logic 1.083ns (71.691%) route 0.428ns (28.309%)) - Logic Levels: 0 - Clock Path Skew: -0.382ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.407ns - Source Clock Delay (SCD): -2.024ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.804 -2.024 u_Axi_CDC/arFifo/ram_reg_0_3_0_5/WCLK - SLICE_X36Y59 RAMD32 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X36Y59 RAMD32 (Prop_ramd32_CLK_O) - 1.083 -0.941 r u_Axi_CDC/arFifo/ram_reg_0_3_0_5/RAMB/O - net (fo=1, routed) 0.428 -0.514 u_Axi_CDC/arFifo/_zz_ram_port10__1[2] - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.935 -2.407 u_Axi_CDC/arFifo/sys_clk - SLICE_X32Y60 FDRE r u_Axi_CDC/arFifo/_zz_ram_port1_reg[2]/C - -Slack: inf - Source: u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - (rising edge-triggered cell RAMD32 clocked by cpu_clk {rise@0.000ns fall@15.161ns period=30.323ns}) - Destination: u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Slow Process Corner) - Data Path Delay: 1.504ns (logic 1.059ns (70.415%) route 0.445ns (29.585%)) - Logic Levels: 0 - Clock Path Skew: -0.388ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -2.402ns - Source Clock Delay (SCD): -2.013ns - Clock Pessimism Removal (CPR): -0.000ns - Clock Uncertainty: 0.194ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Discrete Jitter (DJ): 0.130ns - Phase Error (PE): 0.120ns - Timing Exception: Asynchronous Clock Groups - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock cpu_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0 - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/cpu_clk_clk_pll - BUFGCTRL_X0Y18 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkout1_buf/O - net (fo=6484, routed) 1.815 -2.013 u_Axi_CDC/awFifo/ram_reg_0_3_36_41/WCLK - SLICE_X16Y65 RAMD32 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X16Y65 RAMD32 (Prop_ramd32_CLK_O) - 1.059 -0.954 r u_Axi_CDC/awFifo/ram_reg_0_3_36_41/RAMC_D1/O - net (fo=1, routed) 0.445 -0.509 u_Axi_CDC/awFifo/_zz_ram_port10[41] - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.463 1.463 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.253 2.716 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -8.991 -6.275 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 1.837 -4.438 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -4.342 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.940 -2.402 u_Axi_CDC/awFifo/sys_clk - SLICE_X18Y65 FDRE r u_Axi_CDC/awFifo/_zz_ram_port1_reg[41]/C - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: clkfbout_clk_pll - To Clock: - -Max Delay 0 Endpoints -Min Delay 1 Endpoint --------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT - (clock source 'clkfbout_clk_pll' {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN - Path Group: (none) - Path Type: Min at Slow Process Corner - Data Path Delay: 3.498ns (logic 0.091ns (2.602%) route 3.407ns (97.398%)) - Logic Levels: 1 (BUFG=1) - Clock Uncertainty: 0.169ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.075ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock clkfbout_clk_pll rise edge) - 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 1.393 1.393 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 1.181 2.573 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) - -8.248 -5.674 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBOUT - net (fo=1, routed) 1.755 -3.919 pll_clk.u_clk_pll/inst/clkfbout_clk_pll - BUFGCTRL_X0Y19 BUFG (Prop_bufg_I_O) 0.091 -3.828 r pll_clk.u_clk_pll/inst/clkf_buf/O - net (fo=1, routed) 1.652 -2.177 pll_clk.u_clk_pll/inst/clkfbout_buf_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKFBIN - ------------------------------------------------------------------- ------------------- - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: sys_clk - To Clock: - -Max Delay 0 Endpoints -Min Delay 41 Endpoints --------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - (clock source 'sys_clk' {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_clk - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.614ns (logic 1.260ns (48.196%) route 1.354ns (51.804%)) - Logic Levels: 2 (BUFG=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.794 -0.468 video_clk_OBUF - H22 OBUF (Prop_obuf_I_O) 1.234 0.766 r video_clk_OBUF_inst/O - net (fo=0) 0.000 0.766 video_clk - H22 r video_clk (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[0]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.665ns (logic 1.416ns (53.147%) route 1.249ns (46.853%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[0]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[0]_lopt_replica/Q - net (fo=1, routed) 1.249 0.852 lopt - B24 OBUF (Prop_obuf_I_O) 1.275 2.128 r leds_OBUF[0]_inst/O - net (fo=0) 0.000 2.128 leds[0] - B24 r leds[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[1]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.771ns (logic 1.383ns (49.914%) route 1.388ns (50.086%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[1]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[1]_lopt_replica/Q - net (fo=1, routed) 1.388 0.992 lopt_7 - E21 OBUF (Prop_obuf_I_O) 1.242 2.234 r leds_OBUF[1]_inst/O - net (fo=0) 0.000 2.234 leds[1] - E21 r leds[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[7]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[7] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.806ns (logic 1.454ns (51.806%) route 1.352ns (48.194%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[7]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[7]_lopt_replica/Q - net (fo=1, routed) 1.352 0.943 lopt_13 - B22 OBUF (Prop_obuf_I_O) 1.326 2.268 r leds_OBUF[7]_inst/O - net (fo=0) 0.000 2.268 leds[7] - B22 r leds[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[7] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.807ns (logic 1.362ns (48.520%) route 1.445ns (51.480%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[7]/Q - net (fo=1, routed) 1.445 1.050 dpy1_OBUF[7] - G17 OBUF (Prop_obuf_I_O) 1.221 2.271 r dpy1_OBUF[7]_inst/O - net (fo=0) 0.000 2.271 dpy1[7] - G17 r dpy1[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[13]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[13] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.809ns (logic 1.412ns (50.266%) route 1.397ns (49.734%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X1Y98 FDRE r u_confreg/led_data_reg[13]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[13]_lopt_replica/Q - net (fo=1, routed) 1.397 1.002 lopt_4 - A22 OBUF (Prop_obuf_I_O) 1.271 2.273 r leds_OBUF[13]_inst/O - net (fo=0) 0.000 2.273 leds[13] - A22 r leds[13] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[10]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[10] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.819ns (logic 1.389ns (49.262%) route 1.430ns (50.738%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[10]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[10]_lopt_replica/Q - net (fo=1, routed) 1.430 1.030 lopt_1 - D21 OBUF (Prop_obuf_I_O) 1.248 2.278 r leds_OBUF[10]_inst/O - net (fo=0) 0.000 2.278 leds[10] - D21 r leds[10] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[14]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[14] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.815ns (logic 1.404ns (49.886%) route 1.411ns (50.114%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[14]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[14]_lopt_replica/Q - net (fo=1, routed) 1.411 1.014 lopt_5 - A20 OBUF (Prop_obuf_I_O) 1.263 2.278 r leds_OBUF[14]_inst/O - net (fo=0) 0.000 2.278 leds[14] - A20 r leds[14] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_TX - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.818ns (logic 1.033ns (36.656%) route 1.785ns (63.344%)) - Logic Levels: 2 (LUT3=1 OBUFT=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y60 FDRE (Prop_fdre_C_Q) 0.164 -0.375 r u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en_reg/Q - net (fo=2, routed) 0.232 -0.143 u_axi_uart_controller/uart0/regs/transmitter/tx2rx_en - SLICE_X3Y60 LUT3 (Prop_lut3_I0_O) 0.045 -0.098 r u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IOBUF_inst_i_3/O - net (fo=1, routed) 1.553 1.455 UART_TX_IOBUF_inst/T - H18 OBUFT (TriStatD_obuft_T_O) - 0.824 2.279 r UART_TX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 2.279 UART_TX - H18 r UART_TX (INOUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: UART_RX - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.902ns (logic 0.965ns (33.253%) route 1.937ns (66.747%)) - Logic Levels: 1 (OBUFT=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.689 -0.573 u_axi_uart_controller/uart0/regs/sys_clk - SLICE_X9Y67 FDSE r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X9Y67 FDSE (Prop_fdse_C_Q) 0.141 -0.432 r u_axi_uart_controller/uart0/regs/mode_reg_reg[1]/Q - net (fo=28, routed) 1.937 1.505 UART_RX_IOBUF_inst/T - J20 OBUFT (TriStatD_obuft_T_O) - 0.824 2.329 r UART_RX_IOBUF_inst/OBUFT/O - net (fo=1, unset) 0.000 2.329 UART_RX - J20 r UART_RX (INOUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.872ns (logic 1.407ns (48.983%) route 1.465ns (51.017%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[0]/Q - net (fo=1, routed) 1.465 1.070 dpy1_OBUF[0] - A17 OBUF (Prop_obuf_I_O) 1.266 2.336 r dpy1_OBUF[0]_inst/O - net (fo=0) 0.000 2.336 dpy1[0] - A17 r dpy1[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.877ns (logic 1.376ns (47.814%) route 1.502ns (52.186%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[5]/Q - net (fo=1, routed) 1.502 1.106 dpy1_OBUF[5] - G16 OBUF (Prop_obuf_I_O) 1.235 2.341 r dpy1_OBUF[5]_inst/O - net (fo=0) 0.000 2.341 dpy1[5] - G16 r dpy1[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[7] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.946ns (logic 1.386ns (47.054%) route 1.560ns (52.946%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[7]/Q - net (fo=1, routed) 1.560 1.096 dpy0_OBUF[7] - C17 OBUF (Prop_obuf_I_O) 1.245 2.341 r dpy0_OBUF[7]_inst/O - net (fo=0) 0.000 2.341 dpy0[7] - C17 r dpy0[7] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[6] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.958ns (logic 1.398ns (47.262%) route 1.560ns (52.738%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[6]/Q - net (fo=1, routed) 1.560 1.096 dpy0_OBUF[6] - B17 OBUF (Prop_obuf_I_O) 1.257 2.353 r dpy0_OBUF[6]_inst/O - net (fo=0) 0.000 2.353 dpy0[6] - B17 r dpy0[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.927ns (logic 1.391ns (47.509%) route 1.537ns (52.491%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[1]/Q - net (fo=1, routed) 1.537 1.141 dpy1_OBUF[1] - D16 OBUF (Prop_obuf_I_O) 1.250 2.391 r dpy1_OBUF[1]_inst/O - net (fo=0) 0.000 2.391 dpy1[1] - D16 r dpy1[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 2.966ns (logic 1.383ns (46.637%) route 1.583ns (53.363%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[4]/Q - net (fo=1, routed) 1.583 1.188 dpy1_OBUF[4] - E16 OBUF (Prop_obuf_I_O) 1.242 2.430 r dpy1_OBUF[4]_inst/O - net (fo=0) 0.000 2.430 dpy1[4] - E16 r dpy1[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[3] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.046ns (logic 1.415ns (46.436%) route 1.632ns (53.564%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[3]/Q - net (fo=1, routed) 1.632 1.168 dpy0_OBUF[3] - A19 OBUF (Prop_obuf_I_O) 1.274 2.441 r dpy0_OBUF[3]_inst/O - net (fo=0) 0.000 2.441 dpy0[3] - A19 r dpy0[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[12]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[12] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.006ns (logic 1.384ns (46.047%) route 1.622ns (53.953%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[12]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[12]_lopt_replica/Q - net (fo=1, routed) 1.622 1.223 lopt_3 - D20 OBUF (Prop_obuf_I_O) 1.243 2.467 r leds_OBUF[12]_inst/O - net (fo=0) 0.000 2.467 leds[12] - D20 r leds[12] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.083ns (logic 1.402ns (45.458%) route 1.682ns (54.542%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[0]/Q - net (fo=1, routed) 1.682 1.218 dpy0_OBUF[0] - B19 OBUF (Prop_obuf_I_O) 1.261 2.478 r dpy0_OBUF[0]_inst/O - net (fo=0) 0.000 2.478 dpy0[0] - B19 r dpy0[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[6] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.165ns (logic 1.379ns (43.565%) route 1.786ns (56.435%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X1Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/C - ------------------------------------------------------------------- ------------------- - SLICE_X1Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[6]/Q - net (fo=1, routed) 1.786 1.391 dpy1_OBUF[6] - F15 OBUF (Prop_obuf_I_O) 1.238 2.629 r dpy1_OBUF[6]_inst/O - net (fo=0) 0.000 2.629 dpy1[6] - F15 r dpy1[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.248ns (logic 1.387ns (42.702%) route 1.861ns (57.298%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[1]/Q - net (fo=1, routed) 1.861 1.397 dpy0_OBUF[1] - D19 OBUF (Prop_obuf_I_O) 1.246 2.643 r dpy0_OBUF[1]_inst/O - net (fo=0) 0.000 2.643 dpy0[1] - D19 r dpy0[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.258ns (logic 1.388ns (42.591%) route 1.870ns (57.409%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[5]/Q - net (fo=1, routed) 1.870 1.406 dpy0_OBUF[5] - C19 OBUF (Prop_obuf_I_O) 1.247 2.653 r dpy0_OBUF[5]_inst/O - net (fo=0) 0.000 2.653 dpy0[5] - C19 r dpy0[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.236ns (logic 1.383ns (42.747%) route 1.853ns (57.253%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[2]/Q - net (fo=1, routed) 1.853 1.457 dpy1_OBUF[2] - E17 OBUF (Prop_obuf_I_O) 1.242 2.700 r dpy1_OBUF[2]_inst/O - net (fo=0) 0.000 2.700 dpy1[2] - E17 r dpy1[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[6]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[6] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.273ns (logic 1.423ns (43.486%) route 1.850ns (56.514%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[6]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[6]_lopt_replica/Q - net (fo=1, routed) 1.850 1.440 lopt_12 - E20 OBUF (Prop_obuf_I_O) 1.295 2.736 r leds_OBUF[6]_inst/O - net (fo=0) 0.000 2.736 leds[6] - E20 r leds[6] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[11]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[11] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.362ns (logic 1.408ns (41.889%) route 1.954ns (58.111%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y96 FDRE r u_confreg/led_data_reg[11]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y96 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[11]_lopt_replica/Q - net (fo=1, routed) 1.954 1.557 lopt_2 - A18 OBUF (Prop_obuf_I_O) 1.267 2.825 r leds_OBUF[11]_inst/O - net (fo=0) 0.000 2.825 leds[11] - A18 r leds[11] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_de - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.419ns (logic 1.470ns (42.999%) route 1.949ns (57.001%)) - Logic Levels: 2 (LUT6=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.247 -0.161 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X14Y86 LUT6 (Prop_lut6_I3_O) 0.045 -0.116 r u_axi_dvi/video_de_OBUF_inst_i_1/O - net (fo=1, routed) 1.702 1.586 video_de_OBUF - G24 OBUF (Prop_obuf_I_O) 1.261 2.847 r video_de_OBUF_inst/O - net (fo=0) 0.000 2.847 video_de - G24 r video_de (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_hsync - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.614ns (logic 1.455ns (40.253%) route 2.159ns (59.747%)) - Logic Levels: 2 (LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 f u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.447 0.038 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X9Y86 LUT5 (Prop_lut5_I1_O) 0.045 0.083 r u_axi_dvi/video_hsync_OBUF_inst_i_1/O - net (fo=1, routed) 1.713 1.796 video_hsync_OBUF - J24 OBUF (Prop_obuf_I_O) 1.246 3.041 r video_hsync_OBUF_inst/O - net (fo=0) 0.000 3.041 video_hsync - J24 r video_hsync (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/vdata_reg[8]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_vsync - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.713ns (logic 1.505ns (40.539%) route 2.208ns (59.461%)) - Logic Levels: 3 (LUT4=2 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.687 -0.575 u_axi_dvi/sys_clk - SLICE_X18Y80 FDRE r u_axi_dvi/vdata_reg[8]/C - ------------------------------------------------------------------- ------------------- - SLICE_X18Y80 FDRE (Prop_fdre_C_Q) 0.164 -0.411 f u_axi_dvi/vdata_reg[8]/Q - net (fo=11, routed) 0.333 -0.079 u_axi_dvi/vdata_reg_n_0_[8] - SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 -0.034 f u_axi_dvi/video_vsync_OBUF_inst_i_4/O - net (fo=2, routed) 0.093 0.059 u_axi_dvi/video_vsync_OBUF_inst_i_4_n_0 - SLICE_X17Y86 LUT4 (Prop_lut4_I3_O) 0.045 0.104 r u_axi_dvi/video_vsync_OBUF_inst_i_1/O - net (fo=1, routed) 1.782 1.886 video_vsync_OBUF - H24 OBUF (Prop_obuf_I_O) 1.251 3.138 r video_vsync_OBUF_inst/O - net (fo=0) 0.000 3.138 video_vsync - H24 r video_vsync (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.728ns (logic 1.648ns (44.198%) route 2.081ns (55.802%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.568 1.869 video_red_OBUF[0] - E26 OBUF (Prop_obuf_I_O) 1.287 3.156 r video_red_OBUF[2]_inst/O - net (fo=0) 0.000 3.156 video_red[2] - E26 r video_red[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy1[3] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.728ns (logic 1.356ns (36.384%) route 2.371ns (63.616%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y97 FDCE r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y97 FDCE (Prop_fdce_C_Q) 0.141 -0.395 r u_confreg/u_digitaltube_controller/dpy1_reg_reg[3]/Q - net (fo=1, routed) 2.371 1.976 dpy1_OBUF[3] - F17 OBUF (Prop_obuf_I_O) 1.215 3.191 r dpy1_OBUF[3]_inst/O - net (fo=0) 0.000 3.191 dpy1[3] - F17 r dpy1[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[1] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.827ns (logic 1.622ns (42.374%) route 2.206ns (57.626%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.693 1.994 video_red_OBUF[0] - F24 OBUF (Prop_obuf_I_O) 1.261 3.255 r video_red_OBUF[1]_inst/O - net (fo=0) 0.000 3.255 video_red[1] - F24 r video_red[1] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_axi_dvi/hdata_reg[11]/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: video_red[0] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.859ns (logic 1.594ns (41.315%) route 2.265ns (58.685%)) - Logic Levels: 4 (CARRY4=2 LUT5=1 OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.690 -0.572 u_axi_dvi/sys_clk - SLICE_X12Y83 FDRE r u_axi_dvi/hdata_reg[11]/C - ------------------------------------------------------------------- ------------------- - SLICE_X12Y83 FDRE (Prop_fdre_C_Q) 0.164 -0.408 r u_axi_dvi/hdata_reg[11]/Q - net (fo=12, routed) 0.257 -0.152 u_axi_dvi/hdata_reg_n_0_[11] - SLICE_X15Y84 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.113 -0.039 r u_axi_dvi/video_red_OBUF[2]_inst_i_26/CO[3] - net (fo=1, routed) 0.000 -0.039 u_axi_dvi/video_red_OBUF[2]_inst_i_26_n_0 - SLICE_X15Y85 CARRY4 (Prop_carry4_CI_CO[3]) - 0.039 0.000 f u_axi_dvi/video_red_OBUF[2]_inst_i_5/CO[3] - net (fo=1, routed) 0.257 0.257 u_axi_dvi/video_red_OBUF[2]_inst_i_5_n_0 - SLICE_X16Y85 LUT5 (Prop_lut5_I3_O) 0.045 0.302 r u_axi_dvi/video_red_OBUF[2]_inst_i_1/O - net (fo=3, routed) 1.752 2.053 video_red_OBUF[0] - K23 OBUF (Prop_obuf_I_O) 1.233 3.287 r video_red_OBUF[0]_inst/O - net (fo=0) 0.000 3.287 video_red[0] - K23 r video_red[0] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.903ns (logic 1.400ns (35.872%) route 2.503ns (64.128%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y101 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y101 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[2]/Q - net (fo=1, routed) 2.503 2.039 dpy0_OBUF[2] - B21 OBUF (Prop_obuf_I_O) 1.259 3.298 r dpy0_OBUF[2]_inst/O - net (fo=0) 0.000 3.298 dpy0[2] - B21 r dpy0[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[2]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[2] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.877ns (logic 1.428ns (36.839%) route 2.448ns (63.161%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[2]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[2]_lopt_replica/Q - net (fo=1, routed) 2.448 2.053 lopt_8 - A24 OBUF (Prop_obuf_I_O) 1.287 3.340 r leds_OBUF[2]_inst/O - net (fo=0) 0.000 3.340 leds[2] - A24 r leds[2] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[3]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[3] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 3.896ns (logic 1.404ns (36.025%) route 2.493ns (63.975%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.726 -0.536 u_confreg/sys_clk - SLICE_X0Y98 FDRE r u_confreg/led_data_reg[3]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y98 FDRE (Prop_fdre_C_Q) 0.141 -0.395 r u_confreg/led_data_reg[3]_lopt_replica/Q - net (fo=1, routed) 2.493 2.097 lopt_9 - D23 OBUF (Prop_obuf_I_O) 1.263 3.360 r leds_OBUF[3]_inst/O - net (fo=0) 0.000 3.360 leds[3] - D23 r leds[3] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[9]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[9] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.250ns (logic 1.424ns (33.494%) route 2.827ns (66.506%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.721 -0.541 u_confreg/sys_clk - SLICE_X0Y86 FDRE r u_confreg/led_data_reg[9]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y86 FDRE (Prop_fdre_C_Q) 0.141 -0.400 r u_confreg/led_data_reg[9]_lopt_replica/Q - net (fo=1, routed) 2.827 2.426 lopt_15 - A23 OBUF (Prop_obuf_I_O) 1.283 3.709 r leds_OBUF[9]_inst/O - net (fo=0) 0.000 3.709 leds[9] - A23 r leds[9] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[5]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[5] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.428ns (logic 1.436ns (32.434%) route 2.992ns (67.566%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[5]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.128 -0.409 r u_confreg/led_data_reg[5]_lopt_replica/Q - net (fo=1, routed) 2.992 2.582 lopt_11 - C21 OBUF (Prop_obuf_I_O) 1.308 3.890 r leds_OBUF[5]_inst/O - net (fo=0) 0.000 3.890 leds[5] - C21 r leds[5] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: dpy0[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.536ns (logic 1.381ns (30.449%) route 3.155ns (69.551%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.658 -0.605 u_confreg/u_digitaltube_controller/sys_clk - SLICE_X0Y100 FDCE r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y100 FDCE (Prop_fdce_C_Q) 0.141 -0.464 r u_confreg/u_digitaltube_controller/dpy0_reg_reg[4]/Q - net (fo=1, routed) 3.155 2.691 dpy0_OBUF[4] - E18 OBUF (Prop_obuf_I_O) 1.240 3.931 r dpy0_OBUF[4]_inst/O - net (fo=0) 0.000 3.931 dpy0[4] - E18 r dpy0[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[4]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[4] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.540ns (logic 1.404ns (30.920%) route 3.136ns (69.080%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.723 -0.539 u_confreg/sys_clk - SLICE_X3Y89 FDRE r u_confreg/led_data_reg[4]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y89 FDRE (Prop_fdre_C_Q) 0.141 -0.398 r u_confreg/led_data_reg[4]_lopt_replica/Q - net (fo=1, routed) 3.136 2.738 lopt_10 - C22 OBUF (Prop_obuf_I_O) 1.263 4.001 r leds_OBUF[4]_inst/O - net (fo=0) 0.000 4.001 leds[4] - C22 r leds[4] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[8]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[8] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.629ns (logic 1.426ns (30.799%) route 3.203ns (69.201%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.718 -0.544 u_confreg/sys_clk - SLICE_X2Y81 FDRE r u_confreg/led_data_reg[8]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X2Y81 FDRE (Prop_fdre_C_Q) 0.164 -0.380 r u_confreg/led_data_reg[8]_lopt_replica/Q - net (fo=1, routed) 3.203 2.823 lopt_14 - C23 OBUF (Prop_obuf_I_O) 1.262 4.084 r leds_OBUF[8]_inst/O - net (fo=0) 0.000 4.084 leds[8] - C23 r leds[8] (OUT) - ------------------------------------------------------------------- ------------------- - -Slack: inf - Source: u_confreg/led_data_reg[15]_lopt_replica/C - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Destination: leds[15] - (output port) - Path Group: (none) - Path Type: Min at Fast Process Corner - Data Path Delay: 4.721ns (logic 1.404ns (29.752%) route 3.316ns (70.248%)) - Logic Levels: 1 (OBUF=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.231 0.231 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.440 0.671 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.520 -1.848 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.560 -1.289 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.263 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.725 -0.537 u_confreg/sys_clk - SLICE_X0Y95 FDRE r u_confreg/led_data_reg[15]_lopt_replica/C - ------------------------------------------------------------------- ------------------- - SLICE_X0Y95 FDRE (Prop_fdre_C_Q) 0.141 -0.396 r u_confreg/led_data_reg[15]_lopt_replica/Q - net (fo=1, routed) 3.316 2.920 lopt_6 - B20 OBUF (Prop_obuf_I_O) 1.263 4.183 r leds_OBUF[15]_inst/O - net (fo=0) 0.000 4.183 leds[15] - B20 r leds[15] (OUT) - ------------------------------------------------------------------- ------------------- - - - - - --------------------------------------------------------------------------------------- -Path Group: (none) -From Clock: - To Clock: sys_clk - -Max Delay 0 Endpoints -Min Delay 43 Endpoints --------------------------------------------------------------------------------------- - - -Min Delay Paths --------------------------------------------------------------------------------------- -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.811ns (logic 0.287ns (15.865%) route 1.523ns (84.135%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.523 1.766 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/UART_TX_IBUF - SLICE_X4Y61 LUT5 (Prop_lut5_I2_O) 0.045 1.811 r u_axi_uart_controller/uart0/regs/transmitter/fifo_tx/tx_error_i_1/O - net (fo=1, routed) 0.000 1.811 u_axi_uart_controller/uart0/regs/transmitter/fifo_tx_n_21 - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X4Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/tx_error_reg/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D - (rising edge-triggered cell FDSE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 1.893ns (logic 0.287ns (15.179%) route 1.605ns (84.821%)) - Logic Levels: 2 (IBUF=1 LUT4=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 r UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.605 1.848 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/UART_TX_IBUF - SLICE_X1Y61 LUT4 (Prop_lut4_I2_O) 0.045 1.893 r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0[0]_i_1/O - net (fo=1, routed) 0.000 1.893 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/rcv_pad_i - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/i_uart_sync_flops/sys_clk - SLICE_X1Y61 FDSE r u_axi_uart_controller/uart0/regs/i_uart_sync_flops/flop_0_reg[0]/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[0]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Removal (Min at Fast Process Corner) - Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[0]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[0]/C - -Slack: inf - Source: pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - (internal pin) - Destination: pll_clk.u_rst_sys/delay_reg[1]/CLR - (removal check against rising-edge clock sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Removal (Min at Fast Process Corner) - Data Path Delay: 1.899ns (logic 0.045ns (2.370%) route 1.854ns (97.630%)) - Logic Levels: 1 (LUT1=1) - Clock Uncertainty: 0.190ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE - Total System Jitter (TSJ): 0.050ns - Discrete Jitter (DJ): 0.122ns - Phase Error (PE): 0.124ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - PLLE2_ADV_X0Y3 PLLE2_ADV 0.000 0.000 r pll_clk.u_clk_pll/inst/plle2_adv_inst/LOCKED - net (fo=1, routed) 1.417 1.417 pll_clk.u_rst_sys/locked - SLICE_X0Y121 LUT1 (Prop_lut1_I0_O) 0.045 1.462 f pll_clk.u_rst_sys/delay[1]_i_1/O - net (fo=2, routed) 0.437 1.899 pll_clk.u_rst_sys/delay[1]_i_1_n_0 - SLICE_X1Y101 FDCE f pll_clk.u_rst_sys/delay_reg[1]/CLR - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.932 -0.376 pll_clk.u_rst_sys/sys_clk - SLICE_X1Y101 FDCE r pll_clk.u_rst_sys/delay_reg[1]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.058ns (logic 0.287ns (13.959%) route 1.771ns (86.041%)) - Logic Levels: 2 (IBUF=1 LUT5=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 r UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 r UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT5 (Prop_lut5_I0_O) 0.045 1.838 r u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1/O - net (fo=1, routed) 0.220 2.058 u_axi_uart_controller/uart0/regs/transmitter/error_time[0]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[0]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.089ns (logic 0.408ns (19.545%) route 1.681ns (80.455%)) - Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.130 1.971 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y61 LUT6 (Prop_lut6_I2_O) 0.118 2.089 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1/O - net (fo=1, routed) 0.000 2.089 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_1_n_0 - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y61 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[2]/C - -Slack: inf - Source: touch_btn[0] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.121ns (logic 0.267ns (12.568%) route 1.855ns (87.432%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.339ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T2 0.000 0.000 r touch_btn[0] (IN) - net (fo=0) 0.000 0.000 touch_btn[0] - T2 IBUF (Prop_ibuf_I_O) 0.267 0.267 r touch_btn_IBUF[0]_inst/O - net (fo=1, routed) 1.855 2.121 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[0] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[0]/C - -Slack: inf - Source: UART_TX - (input port) - Destination: u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.315ns (logic 0.406ns (17.548%) route 1.909ns (82.452%)) - Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - H18 0.000 0.000 f UART_TX (INOUT) - net (fo=1, unset) 0.000 0.000 UART_TX_IOBUF_inst/IO - H18 IBUF (Prop_ibuf_I_O) 0.242 0.242 f UART_TX_IOBUF_inst/IBUF/O - net (fo=4, routed) 1.550 1.793 u_axi_uart_controller/uart0/regs/transmitter/UART_TX_IBUF - SLICE_X2Y60 LUT2 (Prop_lut2_I1_O) 0.048 1.841 r u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2/O - net (fo=2, routed) 0.239 2.080 u_axi_uart_controller/uart0/regs/transmitter/error_time[2]_i_2_n_0 - SLICE_X2Y60 LUT5 (Prop_lut5_I1_O) 0.116 2.196 r u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1/O - net (fo=1, routed) 0.119 2.315 u_axi_uart_controller/uart0/regs/transmitter/error_time[1]_i_1_n_0 - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_axi_uart_controller/uart0/regs/transmitter/sys_clk - SLICE_X2Y60 FDRE r u_axi_uart_controller/uart0/regs/transmitter/error_time_reg[1]/C - -Slack: inf - Source: dip_sw[31] - (input port) - Destination: u_confreg/s_rdata_reg[31]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.513ns (logic 0.351ns (13.984%) route 2.162ns (86.016%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R2 0.000 0.000 r dip_sw[31] (IN) - net (fo=0) 0.000 0.000 dip_sw[31] - R2 IBUF (Prop_ibuf_I_O) 0.261 0.261 r dip_sw_IBUF[31]_inst/O - net (fo=1, routed) 1.988 2.249 u_confreg/dip_sw_IBUF[31] - SLICE_X2Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.294 r u_confreg/s_rdata[31]_i_6/O - net (fo=1, routed) 0.174 2.468 u_confreg/u_int_ctrl/s_rdata_reg[31]_2 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.513 r u_confreg/u_int_ctrl/s_rdata[31]_i_1/O - net (fo=1, routed) 0.000 2.513 u_confreg/u_int_ctrl_n_0 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[31]/C - -Slack: inf - Source: dip_sw[27] - (input port) - Destination: u_confreg/s_rdata_reg[27]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.522ns (logic 0.362ns (14.372%) route 2.159ns (85.628%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R1 0.000 0.000 r dip_sw[27] (IN) - net (fo=0) 0.000 0.000 dip_sw[27] - R1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[27]_inst/O - net (fo=1, routed) 1.804 2.076 u_confreg/dip_sw_IBUF[27] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.121 r u_confreg/s_rdata[27]_i_4/O - net (fo=1, routed) 0.356 2.477 u_confreg/u_int_ctrl/s_rdata_reg[27]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.522 r u_confreg/u_int_ctrl/s_rdata[27]_i_1/O - net (fo=1, routed) 0.000 2.522 u_confreg/u_int_ctrl_n_4 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[27]/C - -Slack: inf - Source: dip_sw[22] - (input port) - Destination: u_confreg/s_rdata_reg[22]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.618ns (logic 0.320ns (12.234%) route 2.298ns (87.766%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P6 0.000 0.000 r dip_sw[22] (IN) - net (fo=0) 0.000 0.000 dip_sw[22] - P6 IBUF (Prop_ibuf_I_O) 0.230 0.230 r dip_sw_IBUF[22]_inst/O - net (fo=1, routed) 1.991 2.221 u_confreg/dip_sw_IBUF[22] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.266 r u_confreg/s_rdata[22]_i_4/O - net (fo=1, routed) 0.307 2.573 u_confreg/u_int_ctrl/s_rdata_reg[22]_0 - SLICE_X4Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.618 r u_confreg/u_int_ctrl/s_rdata[22]_i_1/O - net (fo=1, routed) 0.000 2.618 u_confreg/u_int_ctrl_n_9 - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X4Y88 FDRE r u_confreg/s_rdata_reg[22]/C - -Slack: inf - Source: dip_sw[28] - (input port) - Destination: u_confreg/s_rdata_reg[28]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.622ns (logic 0.326ns (12.419%) route 2.296ns (87.581%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R5 0.000 0.000 r dip_sw[28] (IN) - net (fo=0) 0.000 0.000 dip_sw[28] - R5 IBUF (Prop_ibuf_I_O) 0.236 0.236 r dip_sw_IBUF[28]_inst/O - net (fo=1, routed) 2.141 2.376 u_confreg/dip_sw_IBUF[28] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.421 r u_confreg/s_rdata[28]_i_4/O - net (fo=1, routed) 0.155 2.577 u_confreg/u_int_ctrl/s_rdata_reg[28]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.622 r u_confreg/u_int_ctrl/s_rdata[28]_i_1/O - net (fo=1, routed) 0.000 2.622 u_confreg/u_int_ctrl_n_3 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[28]/C - -Slack: inf - Source: dip_sw[30] - (input port) - Destination: u_confreg/s_rdata_reg[30]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.648ns (logic 0.317ns (11.976%) route 2.331ns (88.024%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R6 0.000 0.000 r dip_sw[30] (IN) - net (fo=0) 0.000 0.000 dip_sw[30] - R6 IBUF (Prop_ibuf_I_O) 0.227 0.227 r dip_sw_IBUF[30]_inst/O - net (fo=1, routed) 1.934 2.162 u_confreg/dip_sw_IBUF[30] - SLICE_X2Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.207 r u_confreg/s_rdata[30]_i_4/O - net (fo=1, routed) 0.396 2.603 u_confreg/u_int_ctrl/s_rdata_reg[30]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.648 r u_confreg/u_int_ctrl/s_rdata[30]_i_1/O - net (fo=1, routed) 0.000 2.648 u_confreg/u_int_ctrl_n_1 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[30]/C - -Slack: inf - Source: dip_sw[18] - (input port) - Destination: u_confreg/s_rdata_reg[18]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.666ns (logic 0.347ns (13.011%) route 2.319ns (86.989%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.340ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N3 0.000 0.000 r dip_sw[18] (IN) - net (fo=0) 0.000 0.000 dip_sw[18] - N3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[18]_inst/O - net (fo=1, routed) 2.090 2.347 u_confreg/dip_sw_IBUF[18] - SLICE_X8Y87 LUT5 (Prop_lut5_I4_O) 0.045 2.392 r u_confreg/s_rdata[18]_i_4/O - net (fo=1, routed) 0.229 2.621 u_confreg/u_int_ctrl/s_rdata_reg[18]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 2.666 r u_confreg/u_int_ctrl/s_rdata[18]_i_1/O - net (fo=1, routed) 0.000 2.666 u_confreg/u_int_ctrl_n_13 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[18]/C - -Slack: inf - Source: dip_sw[29] - (input port) - Destination: u_confreg/s_rdata_reg[29]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.680ns (logic 0.336ns (12.535%) route 2.344ns (87.465%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.308ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.308ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T5 0.000 0.000 r dip_sw[29] (IN) - net (fo=0) 0.000 0.000 dip_sw[29] - T5 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[29]_inst/O - net (fo=1, routed) 1.991 2.237 u_confreg/dip_sw_IBUF[29] - SLICE_X1Y94 LUT5 (Prop_lut5_I4_O) 0.045 2.282 r u_confreg/s_rdata[29]_i_4/O - net (fo=1, routed) 0.353 2.635 u_confreg/u_int_ctrl/s_rdata_reg[29]_0 - SLICE_X2Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.680 r u_confreg/u_int_ctrl/s_rdata[29]_i_1/O - net (fo=1, routed) 0.000 2.680 u_confreg/u_int_ctrl_n_2 - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 1.000 -0.308 u_confreg/sys_clk - SLICE_X2Y88 FDRE r u_confreg/s_rdata_reg[29]/C - -Slack: inf - Source: dip_sw[12] - (input port) - Destination: u_confreg/s_rdata_reg[12]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.685ns (logic 0.327ns (12.182%) route 2.358ns (87.818%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M5 0.000 0.000 r dip_sw[12] (IN) - net (fo=0) 0.000 0.000 dip_sw[12] - M5 IBUF (Prop_ibuf_I_O) 0.237 0.237 r dip_sw_IBUF[12]_inst/O - net (fo=1, routed) 2.193 2.430 u_confreg/dip_sw_IBUF[12] - SLICE_X5Y86 LUT5 (Prop_lut5_I4_O) 0.045 2.475 r u_confreg/s_rdata[12]_i_4/O - net (fo=1, routed) 0.165 2.640 u_confreg/u_int_ctrl/s_rdata_reg[12]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 2.685 r u_confreg/u_int_ctrl/s_rdata[12]_i_1/O - net (fo=1, routed) 0.000 2.685 u_confreg/u_int_ctrl_n_19 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[12]/C - -Slack: inf - Source: dip_sw[7] - (input port) - Destination: u_confreg/s_rdata_reg[7]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.753ns (logic 0.329ns (11.958%) route 2.424ns (88.042%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.312ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.312ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N6 0.000 0.000 r dip_sw[7] (IN) - net (fo=0) 0.000 0.000 dip_sw[7] - N6 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[7]_inst/O - net (fo=1, routed) 2.373 2.612 u_confreg/dip_sw_IBUF[7] - SLICE_X1Y84 LUT5 (Prop_lut5_I4_O) 0.045 2.657 r u_confreg/s_rdata[7]_i_4/O - net (fo=1, routed) 0.051 2.708 u_confreg/u_int_ctrl/s_rdata_reg[7]_0 - SLICE_X1Y84 LUT6 (Prop_lut6_I4_O) 0.045 2.753 r u_confreg/u_int_ctrl/s_rdata[7]_i_1/O - net (fo=1, routed) 0.000 2.753 u_confreg/u_int_ctrl_n_24 - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.996 -0.312 u_confreg/sys_clk - SLICE_X1Y84 FDRE r u_confreg/s_rdata_reg[7]/C - -Slack: inf - Source: dip_sw[24] - (input port) - Destination: u_confreg/s_rdata_reg[24]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.843ns (logic 0.324ns (11.413%) route 2.518ns (88.587%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P5 0.000 0.000 r dip_sw[24] (IN) - net (fo=0) 0.000 0.000 dip_sw[24] - P5 IBUF (Prop_ibuf_I_O) 0.234 0.234 r dip_sw_IBUF[24]_inst/O - net (fo=1, routed) 2.106 2.340 u_confreg/dip_sw_IBUF[24] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.385 r u_confreg/s_rdata[24]_i_4/O - net (fo=1, routed) 0.412 2.798 u_confreg/u_int_ctrl/s_rdata_reg[24]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.843 r u_confreg/u_int_ctrl/s_rdata[24]_i_1/O - net (fo=1, routed) 0.000 2.843 u_confreg/u_int_ctrl_n_7 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[24]/C - -Slack: inf - Source: touch_btn[1] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.881ns (logic 0.283ns (9.807%) route 2.599ns (90.193%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.339ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.339ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M1 0.000 0.000 r touch_btn[1] (IN) - net (fo=0) 0.000 0.000 touch_btn[1] - M1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r touch_btn_IBUF[1]_inst/O - net (fo=1, routed) 2.599 2.881 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[1] - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.969 -0.339 u_confreg/u_int_ctrl/sys_clk - SLICE_X13Y89 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[1]/C - -Slack: inf - Source: dip_sw[3] - (input port) - Destination: u_confreg/s_rdata_reg[3]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.900ns (logic 0.362ns (12.483%) route 2.538ns (87.517%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.319ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P1 0.000 0.000 r dip_sw[3] (IN) - net (fo=0) 0.000 0.000 dip_sw[3] - P1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[3]_inst/O - net (fo=1, routed) 2.197 2.469 u_confreg/dip_sw_IBUF[3] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.514 r u_confreg/s_rdata[3]_i_4/O - net (fo=1, routed) 0.340 2.855 u_confreg/u_int_ctrl/s_rdata_reg[3]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 2.900 r u_confreg/u_int_ctrl/s_rdata[3]_i_1/O - net (fo=1, routed) 0.000 2.900 u_confreg/u_int_ctrl_n_28 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[3]/C - -Slack: inf - Source: dip_sw[16] - (input port) - Destination: u_confreg/s_rdata_reg[16]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.965ns (logic 0.358ns (12.066%) route 2.607ns (87.934%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K2 0.000 0.000 r dip_sw[16] (IN) - net (fo=0) 0.000 0.000 dip_sw[16] - K2 IBUF (Prop_ibuf_I_O) 0.268 0.268 r dip_sw_IBUF[16]_inst/O - net (fo=1, routed) 2.496 2.764 u_confreg/dip_sw_IBUF[16] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.809 r u_confreg/s_rdata[16]_i_4/O - net (fo=1, routed) 0.111 2.920 u_confreg/u_int_ctrl/s_rdata_reg[16]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.965 r u_confreg/u_int_ctrl/s_rdata[16]_i_1/O - net (fo=1, routed) 0.000 2.965 u_confreg/u_int_ctrl_n_15 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[16]/C - -Slack: inf - Source: dip_sw[0] - (input port) - Destination: u_confreg/s_rdata_reg[0]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.973ns (logic 0.353ns (11.866%) route 2.620ns (88.134%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T3 0.000 0.000 r dip_sw[0] (IN) - net (fo=0) 0.000 0.000 dip_sw[0] - T3 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[0]_inst/O - net (fo=1, routed) 2.278 2.541 u_confreg/dip_sw_IBUF[0] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.586 r u_confreg/s_rdata[0]_i_4/O - net (fo=1, routed) 0.342 2.928 u_confreg/u_int_ctrl/s_rdata_reg[0]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 2.973 r u_confreg/u_int_ctrl/s_rdata[0]_i_1/O - net (fo=1, routed) 0.000 2.973 u_confreg/u_int_ctrl_n_31 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[0]/C - -Slack: inf - Source: touch_btn[3] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.974ns (logic 0.280ns (9.424%) route 2.694ns (90.576%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.317ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.317ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - U2 0.000 0.000 r touch_btn[3] (IN) - net (fo=0) 0.000 0.000 touch_btn[3] - U2 IBUF (Prop_ibuf_I_O) 0.280 0.280 r touch_btn_IBUF[3]_inst/O - net (fo=1, routed) 2.694 2.974 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[3] - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.991 -0.317 u_confreg/u_int_ctrl/sys_clk - SLICE_X1Y79 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[3]/C - -Slack: inf - Source: dip_sw[14] - (input port) - Destination: u_confreg/s_rdata_reg[14]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.984ns (logic 0.373ns (12.482%) route 2.612ns (87.518%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J1 0.000 0.000 r dip_sw[14] (IN) - net (fo=0) 0.000 0.000 dip_sw[14] - J1 IBUF (Prop_ibuf_I_O) 0.283 0.283 r dip_sw_IBUF[14]_inst/O - net (fo=1, routed) 2.273 2.555 u_confreg/dip_sw_IBUF[14] - SLICE_X5Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.600 r u_confreg/s_rdata[14]_i_4/O - net (fo=1, routed) 0.339 2.939 u_confreg/u_int_ctrl/s_rdata_reg[14]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 2.984 r u_confreg/u_int_ctrl/s_rdata[14]_i_1/O - net (fo=1, routed) 0.000 2.984 u_confreg/u_int_ctrl_n_17 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[14]/C - -Slack: inf - Source: dip_sw[21] - (input port) - Destination: u_confreg/s_rdata_reg[21]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 2.997ns (logic 0.346ns (11.544%) route 2.651ns (88.456%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N2 0.000 0.000 r dip_sw[21] (IN) - net (fo=0) 0.000 0.000 dip_sw[21] - N2 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[21]_inst/O - net (fo=1, routed) 2.278 2.534 u_confreg/dip_sw_IBUF[21] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.579 r u_confreg/s_rdata[21]_i_4/O - net (fo=1, routed) 0.373 2.952 u_confreg/u_int_ctrl/s_rdata_reg[21]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 2.997 r u_confreg/u_int_ctrl/s_rdata[21]_i_1/O - net (fo=1, routed) 0.000 2.997 u_confreg/u_int_ctrl_n_10 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[21]/C - -Slack: inf - Source: dip_sw[6] - (input port) - Destination: u_confreg/s_rdata_reg[6]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.000ns (logic 0.346ns (11.523%) route 2.655ns (88.477%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L3 0.000 0.000 r dip_sw[6] (IN) - net (fo=0) 0.000 0.000 dip_sw[6] - L3 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[6]_inst/O - net (fo=1, routed) 2.297 2.553 u_confreg/dip_sw_IBUF[6] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.598 r u_confreg/s_rdata[6]_i_4/O - net (fo=1, routed) 0.358 2.955 u_confreg/u_int_ctrl/s_rdata_reg[6]_0 - SLICE_X5Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.000 r u_confreg/u_int_ctrl/s_rdata[6]_i_1/O - net (fo=1, routed) 0.000 3.000 u_confreg/u_int_ctrl_n_25 - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/sys_clk - SLICE_X5Y83 FDRE r u_confreg/s_rdata_reg[6]/C - -Slack: inf - Source: dip_sw[26] - (input port) - Destination: u_confreg/s_rdata_reg[26]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.025ns (logic 0.367ns (12.128%) route 2.658ns (87.872%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.340ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.340ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - T4 0.000 0.000 r dip_sw[26] (IN) - net (fo=0) 0.000 0.000 dip_sw[26] - T4 IBUF (Prop_ibuf_I_O) 0.277 0.277 r dip_sw_IBUF[26]_inst/O - net (fo=1, routed) 2.208 2.485 u_confreg/dip_sw_IBUF[26] - SLICE_X6Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.530 r u_confreg/s_rdata[26]_i_4/O - net (fo=1, routed) 0.450 2.980 u_confreg/u_int_ctrl/s_rdata_reg[26]_0 - SLICE_X8Y87 LUT6 (Prop_lut6_I4_O) 0.045 3.025 r u_confreg/u_int_ctrl/s_rdata[26]_i_1/O - net (fo=1, routed) 0.000 3.025 u_confreg/u_int_ctrl_n_5 - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.968 -0.340 u_confreg/sys_clk - SLICE_X8Y87 FDRE r u_confreg/s_rdata_reg[26]/C - -Slack: inf - Source: dip_sw[10] - (input port) - Destination: u_confreg/s_rdata_reg[10]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.067ns (logic 0.330ns (10.763%) route 2.737ns (89.237%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M7 0.000 0.000 r dip_sw[10] (IN) - net (fo=0) 0.000 0.000 dip_sw[10] - M7 IBUF (Prop_ibuf_I_O) 0.240 0.240 r dip_sw_IBUF[10]_inst/O - net (fo=1, routed) 2.590 2.830 u_confreg/dip_sw_IBUF[10] - SLICE_X8Y80 LUT5 (Prop_lut5_I4_O) 0.045 2.875 r u_confreg/s_rdata[10]_i_4/O - net (fo=1, routed) 0.147 3.022 u_confreg/u_int_ctrl/s_rdata_reg[10]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.067 r u_confreg/u_int_ctrl/s_rdata[10]_i_1/O - net (fo=1, routed) 0.000 3.067 u_confreg/u_int_ctrl_n_21 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[10]/C - -Slack: inf - Source: dip_sw[15] - (input port) - Destination: u_confreg/s_rdata_reg[15]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.091ns (logic 0.352ns (11.385%) route 2.739ns (88.615%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L2 0.000 0.000 r dip_sw[15] (IN) - net (fo=0) 0.000 0.000 dip_sw[15] - L2 IBUF (Prop_ibuf_I_O) 0.262 0.262 r dip_sw_IBUF[15]_inst/O - net (fo=1, routed) 2.453 2.715 u_confreg/dip_sw_IBUF[15] - SLICE_X1Y95 LUT5 (Prop_lut5_I4_O) 0.045 2.760 r u_confreg/s_rdata[15]_i_4/O - net (fo=1, routed) 0.285 3.046 u_confreg/u_int_ctrl/s_rdata_reg[15]_0 - SLICE_X5Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.091 r u_confreg/u_int_ctrl/s_rdata[15]_i_1/O - net (fo=1, routed) 0.000 3.091 u_confreg/u_int_ctrl_n_16 - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y89 FDRE r u_confreg/s_rdata_reg[15]/C - -Slack: inf - Source: dip_sw[5] - (input port) - Destination: u_confreg/s_rdata_reg[5]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.122ns (logic 0.328ns (10.518%) route 2.794ns (89.482%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L5 0.000 0.000 r dip_sw[5] (IN) - net (fo=0) 0.000 0.000 dip_sw[5] - L5 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[5]_inst/O - net (fo=1, routed) 2.365 2.604 u_confreg/dip_sw_IBUF[5] - SLICE_X7Y91 LUT5 (Prop_lut5_I4_O) 0.045 2.649 r u_confreg/s_rdata[5]_i_4/O - net (fo=1, routed) 0.428 3.077 u_confreg/u_int_ctrl/s_rdata_reg[5]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.122 r u_confreg/u_int_ctrl/s_rdata[5]_i_1/O - net (fo=1, routed) 0.000 3.122 u_confreg/u_int_ctrl_n_26 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[5]/C - -Slack: inf - Source: dip_sw[2] - (input port) - Destination: u_confreg/s_rdata_reg[2]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.123ns (logic 0.353ns (11.299%) route 2.770ns (88.701%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M2 0.000 0.000 r dip_sw[2] (IN) - net (fo=0) 0.000 0.000 dip_sw[2] - M2 IBUF (Prop_ibuf_I_O) 0.263 0.263 r dip_sw_IBUF[2]_inst/O - net (fo=1, routed) 2.335 2.598 u_confreg/dip_sw_IBUF[2] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.643 r u_confreg/s_rdata[2]_i_4/O - net (fo=1, routed) 0.435 3.078 u_confreg/u_int_ctrl/s_rdata_reg[2]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 3.123 r u_confreg/u_int_ctrl/s_rdata[2]_i_1/O - net (fo=1, routed) 0.000 3.123 u_confreg/u_int_ctrl_n_29 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[2]/C - -Slack: inf - Source: dip_sw[17] - (input port) - Destination: u_confreg/s_rdata_reg[17]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.171ns (logic 0.362ns (11.408%) route 2.809ns (88.593%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K1 0.000 0.000 r dip_sw[17] (IN) - net (fo=0) 0.000 0.000 dip_sw[17] - K1 IBUF (Prop_ibuf_I_O) 0.272 0.272 r dip_sw_IBUF[17]_inst/O - net (fo=1, routed) 2.515 2.787 u_confreg/dip_sw_IBUF[17] - SLICE_X5Y92 LUT5 (Prop_lut5_I4_O) 0.045 2.832 r u_confreg/s_rdata[17]_i_4/O - net (fo=1, routed) 0.294 3.126 u_confreg/u_int_ctrl/s_rdata_reg[17]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 3.171 r u_confreg/u_int_ctrl/s_rdata[17]_i_1/O - net (fo=1, routed) 0.000 3.171 u_confreg/u_int_ctrl_n_14 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[17]/C - -Slack: inf - Source: dip_sw[23] - (input port) - Destination: u_confreg/s_rdata_reg[23]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.218ns (logic 0.376ns (11.683%) route 2.842ns (88.317%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N1 0.000 0.000 r dip_sw[23] (IN) - net (fo=0) 0.000 0.000 dip_sw[23] - N1 IBUF (Prop_ibuf_I_O) 0.286 0.286 r dip_sw_IBUF[23]_inst/O - net (fo=1, routed) 2.402 2.688 u_confreg/dip_sw_IBUF[23] - SLICE_X7Y93 LUT5 (Prop_lut5_I4_O) 0.045 2.733 r u_confreg/s_rdata[23]_i_4/O - net (fo=1, routed) 0.440 3.173 u_confreg/u_int_ctrl/s_rdata_reg[23]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 3.218 r u_confreg/u_int_ctrl/s_rdata[23]_i_1/O - net (fo=1, routed) 0.000 3.218 u_confreg/u_int_ctrl_n_8 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[23]/C - -Slack: inf - Source: dip_sw[4] - (input port) - Destination: u_confreg/s_rdata_reg[4]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.278ns (logic 0.346ns (10.553%) route 2.932ns (89.447%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.313ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.313ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P4 0.000 0.000 r dip_sw[4] (IN) - net (fo=0) 0.000 0.000 dip_sw[4] - P4 IBUF (Prop_ibuf_I_O) 0.256 0.256 r dip_sw_IBUF[4]_inst/O - net (fo=1, routed) 2.708 2.964 u_confreg/dip_sw_IBUF[4] - SLICE_X2Y85 LUT5 (Prop_lut5_I4_O) 0.045 3.009 r u_confreg/s_rdata[4]_i_4/O - net (fo=1, routed) 0.224 3.233 u_confreg/u_int_ctrl/s_rdata_reg[4]_0 - SLICE_X2Y83 LUT6 (Prop_lut6_I4_O) 0.045 3.278 r u_confreg/u_int_ctrl/s_rdata[4]_i_1/O - net (fo=1, routed) 0.000 3.278 u_confreg/u_int_ctrl_n_27 - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk - SLICE_X2Y83 FDRE r u_confreg/s_rdata_reg[4]/C - -Slack: inf - Source: dip_sw[9] - (input port) - Destination: u_confreg/s_rdata_reg[9]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 3.293ns (logic 0.328ns (9.951%) route 2.965ns (90.049%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - N7 0.000 0.000 r dip_sw[9] (IN) - net (fo=0) 0.000 0.000 dip_sw[9] - N7 IBUF (Prop_ibuf_I_O) 0.238 0.238 r dip_sw_IBUF[9]_inst/O - net (fo=1, routed) 2.752 2.990 u_confreg/dip_sw_IBUF[9] - SLICE_X1Y80 LUT5 (Prop_lut5_I4_O) 0.045 3.035 r u_confreg/s_rdata[9]_i_4/O - net (fo=1, routed) 0.213 3.248 u_confreg/u_int_ctrl/s_rdata_reg[9]_0 - SLICE_X1Y80 LUT6 (Prop_lut6_I4_O) 0.045 3.293 r u_confreg/u_int_ctrl/s_rdata[9]_i_1/O - net (fo=1, routed) 0.000 3.293 u_confreg/u_int_ctrl_n_22 - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X1Y80 FDRE r u_confreg/s_rdata_reg[9]/C - -Slack: inf - Source: touch_btn[2] - (input port) - Destination: u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - (rising edge-triggered cell FDCE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.287ns (logic 0.255ns (5.940%) route 4.032ns (94.060%)) - Logic Levels: 1 (IBUF=1) - Clock Path Skew: -0.315ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.315ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - P3 0.000 0.000 r touch_btn[2] (IN) - net (fo=0) 0.000 0.000 touch_btn[2] - P3 IBUF (Prop_ibuf_I_O) 0.255 0.255 r touch_btn_IBUF[2]_inst/O - net (fo=1, routed) 4.032 4.287 u_confreg/u_int_ctrl/int_in_sync_d1_reg[6]_0[2] - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.993 -0.315 u_confreg/u_int_ctrl/sys_clk - SLICE_X7Y83 FDCE r u_confreg/u_int_ctrl/int_in_sync_d1_reg[2]/C - -Slack: inf - Source: dip_sw[19] - (input port) - Destination: u_confreg/s_rdata_reg[19]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.396ns (logic 0.336ns (7.645%) route 4.060ns (92.355%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.313ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.313ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L4 0.000 0.000 r dip_sw[19] (IN) - net (fo=0) 0.000 0.000 dip_sw[19] - L4 IBUF (Prop_ibuf_I_O) 0.246 0.246 r dip_sw_IBUF[19]_inst/O - net (fo=1, routed) 4.009 4.255 u_confreg/dip_sw_IBUF[19] - SLICE_X7Y86 LUT5 (Prop_lut5_I4_O) 0.045 4.300 r u_confreg/s_rdata[19]_i_4/O - net (fo=1, routed) 0.051 4.351 u_confreg/u_int_ctrl/s_rdata_reg[19]_0 - SLICE_X7Y86 LUT6 (Prop_lut6_I4_O) 0.045 4.396 r u_confreg/u_int_ctrl/s_rdata[19]_i_1/O - net (fo=1, routed) 0.000 4.396 u_confreg/u_int_ctrl_n_12 - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.995 -0.313 u_confreg/sys_clk - SLICE_X7Y86 FDRE r u_confreg/s_rdata_reg[19]/C - -Slack: inf - Source: dip_sw[25] - (input port) - Destination: u_confreg/s_rdata_reg[25]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.440ns (logic 0.347ns (7.817%) route 4.093ns (92.183%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.338ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.338ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - R3 0.000 0.000 r dip_sw[25] (IN) - net (fo=0) 0.000 0.000 dip_sw[25] - R3 IBUF (Prop_ibuf_I_O) 0.257 0.257 r dip_sw_IBUF[25]_inst/O - net (fo=1, routed) 3.854 4.111 u_confreg/dip_sw_IBUF[25] - SLICE_X9Y88 LUT5 (Prop_lut5_I4_O) 0.045 4.156 r u_confreg/s_rdata[25]_i_4/O - net (fo=1, routed) 0.239 4.395 u_confreg/u_int_ctrl/s_rdata_reg[25]_0 - SLICE_X8Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.440 r u_confreg/u_int_ctrl/s_rdata[25]_i_1/O - net (fo=1, routed) 0.000 4.440 u_confreg/u_int_ctrl_n_6 - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.970 -0.338 u_confreg/sys_clk - SLICE_X8Y88 FDRE r u_confreg/s_rdata_reg[25]/C - -Slack: inf - Source: dip_sw[11] - (input port) - Destination: u_confreg/s_rdata_reg[11]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.518ns (logic 0.329ns (7.286%) route 4.189ns (92.714%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.316ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.316ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - L7 0.000 0.000 r dip_sw[11] (IN) - net (fo=0) 0.000 0.000 dip_sw[11] - L7 IBUF (Prop_ibuf_I_O) 0.239 0.239 r dip_sw_IBUF[11]_inst/O - net (fo=1, routed) 3.969 4.208 u_confreg/dip_sw_IBUF[11] - SLICE_X4Y82 LUT5 (Prop_lut5_I4_O) 0.045 4.253 r u_confreg/s_rdata[11]_i_4/O - net (fo=1, routed) 0.220 4.473 u_confreg/u_int_ctrl/s_rdata_reg[11]_0 - SLICE_X5Y82 LUT6 (Prop_lut6_I4_O) 0.045 4.518 r u_confreg/u_int_ctrl/s_rdata[11]_i_1/O - net (fo=1, routed) 0.000 4.518 u_confreg/u_int_ctrl_n_20 - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.992 -0.316 u_confreg/sys_clk - SLICE_X5Y82 FDRE r u_confreg/s_rdata_reg[11]/C - -Slack: inf - Source: dip_sw[13] - (input port) - Destination: u_confreg/s_rdata_reg[13]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.727ns (logic 0.344ns (7.270%) route 4.383ns (92.730%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - K3 0.000 0.000 r dip_sw[13] (IN) - net (fo=0) 0.000 0.000 dip_sw[13] - K3 IBUF (Prop_ibuf_I_O) 0.254 0.254 r dip_sw_IBUF[13]_inst/O - net (fo=1, routed) 4.162 4.416 u_confreg/dip_sw_IBUF[13] - SLICE_X4Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.461 r u_confreg/s_rdata[13]_i_4/O - net (fo=1, routed) 0.221 4.682 u_confreg/u_int_ctrl/s_rdata_reg[13]_0 - SLICE_X5Y88 LUT6 (Prop_lut6_I4_O) 0.045 4.727 r u_confreg/u_int_ctrl/s_rdata[13]_i_1/O - net (fo=1, routed) 0.000 4.727 u_confreg/u_int_ctrl_n_18 - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X5Y88 FDRE r u_confreg/s_rdata_reg[13]/C - -Slack: inf - Source: dip_sw[1] - (input port) - Destination: u_confreg/s_rdata_reg[1]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.729ns (logic 0.355ns (7.516%) route 4.374ns (92.484%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.345ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.345ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - J3 0.000 0.000 r dip_sw[1] (IN) - net (fo=0) 0.000 0.000 dip_sw[1] - J3 IBUF (Prop_ibuf_I_O) 0.265 0.265 r dip_sw_IBUF[1]_inst/O - net (fo=1, routed) 3.965 4.231 u_confreg/dip_sw_IBUF[1] - SLICE_X6Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.276 r u_confreg/s_rdata[1]_i_4/O - net (fo=1, routed) 0.409 4.684 u_confreg/u_int_ctrl/s_rdata_reg[1]_0 - SLICE_X8Y81 LUT6 (Prop_lut6_I4_O) 0.045 4.729 r u_confreg/u_int_ctrl/s_rdata[1]_i_1/O - net (fo=1, routed) 0.000 4.729 u_confreg/u_int_ctrl_n_30 - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.963 -0.345 u_confreg/sys_clk - SLICE_X8Y81 FDRE r u_confreg/s_rdata_reg[1]/C - -Slack: inf - Source: dip_sw[20] - (input port) - Destination: u_confreg/s_rdata_reg[20]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 4.977ns (logic 0.333ns (6.690%) route 4.644ns (93.310%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.310ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.310ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M4 0.000 0.000 r dip_sw[20] (IN) - net (fo=0) 0.000 0.000 dip_sw[20] - M4 IBUF (Prop_ibuf_I_O) 0.243 0.243 r dip_sw_IBUF[20]_inst/O - net (fo=1, routed) 4.258 4.501 u_confreg/dip_sw_IBUF[20] - SLICE_X7Y92 LUT5 (Prop_lut5_I4_O) 0.045 4.546 r u_confreg/s_rdata[20]_i_4/O - net (fo=1, routed) 0.386 4.932 u_confreg/u_int_ctrl/s_rdata_reg[20]_0 - SLICE_X7Y89 LUT6 (Prop_lut6_I4_O) 0.045 4.977 r u_confreg/u_int_ctrl/s_rdata[20]_i_1/O - net (fo=1, routed) 0.000 4.977 u_confreg/u_int_ctrl_n_11 - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.998 -0.310 u_confreg/sys_clk - SLICE_X7Y89 FDRE r u_confreg/s_rdata_reg[20]/C - -Slack: inf - Source: dip_sw[8] - (input port) - Destination: u_confreg/s_rdata_reg[8]/D - (rising edge-triggered cell FDRE clocked by sys_clk {rise@0.000ns fall@10.000ns period=20.000ns}) - Path Group: (none) - Path Type: Hold (Min at Fast Process Corner) - Data Path Delay: 5.044ns (logic 0.334ns (6.614%) route 4.711ns (93.386%)) - Logic Levels: 3 (IBUF=1 LUT5=1 LUT6=1) - Clock Path Skew: -0.319ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): -0.319ns - Source Clock Delay (SCD): 0.000ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - M6 0.000 0.000 r dip_sw[8] (IN) - net (fo=0) 0.000 0.000 dip_sw[8] - M6 IBUF (Prop_ibuf_I_O) 0.244 0.244 r dip_sw_IBUF[8]_inst/O - net (fo=1, routed) 4.491 4.735 u_confreg/dip_sw_IBUF[8] - SLICE_X5Y79 LUT5 (Prop_lut5_I4_O) 0.045 4.780 r u_confreg/s_rdata[8]_i_4/O - net (fo=1, routed) 0.220 4.999 u_confreg/u_int_ctrl/s_rdata_reg[8]_0 - SLICE_X5Y79 LUT6 (Prop_lut6_I4_O) 0.045 5.044 r u_confreg/u_int_ctrl/s_rdata[8]_i_1/O - net (fo=1, routed) 0.000 5.044 u_confreg/u_int_ctrl_n_23 - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/D - ------------------------------------------------------------------- ------------------- - - (clock sys_clk rise edge) 0.000 0.000 r - K21 0.000 0.000 r clk (IN) - net (fo=0) 0.000 0.000 pll_clk.u_clk_pll/inst/clk_in1 - K21 IBUF (Prop_ibuf_I_O) 0.419 0.419 r pll_clk.u_clk_pll/inst/clkin1_ibufg/O - net (fo=1, routed) 0.481 0.900 pll_clk.u_clk_pll/inst/clk_in1_clk_pll - PLLE2_ADV_X0Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) - -2.847 -1.947 r pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1 - net (fo=1, routed) 0.611 -1.337 pll_clk.u_clk_pll/inst/sys_clk_clk_pll - BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.308 r pll_clk.u_clk_pll/inst/clkout2_buf/O - net (fo=10004, routed) 0.989 -0.319 u_confreg/sys_clk - SLICE_X5Y79 FDRE r u_confreg/s_rdata_reg[8]/C - - - - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt deleted file mode 100644 index ad58480..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization.rpt +++ /dev/null @@ -1,237 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:05 2026 -| Host : fedora running 64-bit unknown -| Command : report_utilization -file /home/fallensigh/vivado_reports_nodsp/utilization.rpt -| Design : soc_top -| Device : 7a200tfbg676-1 -| Design State : Routed ------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+----------------------------+-------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------------------+-------+-------+-----------+-------+ -| Slice LUTs | 60995 | 0 | 133800 | 45.59 | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | -| LUT as Shift Register | 1115 | 0 | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register as Flip Flop | 39931 | 0 | 267600 | 14.92 | -| Register as Latch | 0 | 0 | 267600 | 0.00 | -| F7 Muxes | 4480 | 0 | 66900 | 6.70 | -| F8 Muxes | 1556 | 0 | 33450 | 4.65 | -+----------------------------+-------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 24 | Yes | - | Set | -| 26637 | Yes | - | Reset | -| 139 | Yes | Set | - | -| 13131 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+--------------------------------------------+-------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+--------------------------------------------+-------+-------+-----------+-------+ -| Slice | 20066 | 0 | 33450 | 59.99 | -| SLICEL | 13210 | 0 | | | -| SLICEM | 6856 | 0 | | | -| LUT as Logic | 59140 | 0 | 133800 | 44.20 | -| using O5 output only | 2 | | | | -| using O6 output only | 49931 | | | | -| using O5 and O6 | 9207 | | | | -| LUT as Memory | 1855 | 0 | 46200 | 4.02 | -| LUT as Distributed RAM | 740 | 0 | | | -| using O5 output only | 0 | | | | -| using O6 output only | 60 | | | | -| using O5 and O6 | 680 | | | | -| LUT as Shift Register | 1115 | 0 | | | -| using O5 output only | 47 | | | | -| using O6 output only | 1008 | | | | -| using O5 and O6 | 60 | | | | -| Slice Registers | 39931 | 0 | 267600 | 14.92 | -| Register driven from within the Slice | 20433 | | | | -| Register driven from outside the Slice | 19498 | | | | -| LUT in front of the register is unused | 10788 | | | | -| LUT in front of the register is used | 8710 | | | | -| Unique Control Sets | 1304 | | 33450 | 3.90 | -+--------------------------------------------+-------+-------+-----------+-------+ -* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 23.5 | 0 | 365 | 6.44 | -| RAMB36/FIFO* | 8 | 0 | 365 | 2.19 | -| RAMB36E1 only | 8 | | | | -| RAMB18 | 31 | 0 | 730 | 4.25 | -| RAMB18E1 only | 31 | | | | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+----------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+----------------+------+-------+-----------+-------+ -| DSPs | 16 | 0 | 740 | 2.16 | -| DSP48E1 only | 16 | | | | -+----------------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 202 | 202 | 400 | 50.50 | -| IOB Master Pads | 97 | | | | -| IOB Slave Pads | 102 | | | | -| Bonded IPADs | 0 | 0 | 26 | 0.00 | -| Bonded OPADs | 0 | 0 | 16 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 384 | 0.00 | -| GTPE2_CHANNEL | 0 | 0 | 8 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 4 | 0.00 | -| ILOGIC | 0 | 0 | 400 | 0.00 | -| OLOGIC | 0 | 0 | 400 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 4 | 0 | 32 | 12.50 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 1 | 0 | 10 | 10.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | -| BUFHCE | 0 | 0 | 120 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+-----------+-------+---------------------+ -| Ref Name | Used | Functional Category | -+-----------+-------+---------------------+ -| LUT6 | 35413 | LUT | -| FDCE | 26637 | Flop & Latch | -| FDRE | 13131 | Flop & Latch | -| LUT3 | 9384 | LUT | -| LUT5 | 8477 | LUT | -| LUT4 | 7294 | LUT | -| LUT2 | 6978 | LUT | -| MUXF7 | 4480 | MuxFx | -| CARRY4 | 2859 | CarryLogic | -| MUXF8 | 1556 | MuxFx | -| RAMD32 | 1060 | Distributed Memory | -| SRLC32E | 992 | Distributed Memory | -| LUT1 | 801 | LUT | -| RAMS32 | 328 | Distributed Memory | -| SRL16E | 183 | Distributed Memory | -| FDSE | 139 | Flop & Latch | -| IBUF | 104 | IO | -| OBUF | 98 | IO | -| OBUFT | 66 | IO | -| RAMD64E | 32 | Distributed Memory | -| RAMB18E1 | 31 | Block Memory | -| FDPE | 24 | Flop & Latch | -| DSP48E1 | 16 | Block Arithmetic | -| RAMB36E1 | 8 | Block Memory | -| BUFG | 4 | Clock | -| PLLE2_ADV | 1 | Clock | -+-----------+-------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ -| clk_pll | 1 | -+----------+------+ - - diff --git a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt b/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt deleted file mode 100644 index 9abba2a..0000000 --- a/fpga/vivado_reports_nodsp/vivado_reports_nodsp/utilization_hier.rpt +++ /dev/null @@ -1,276 +0,0 @@ -Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 -| Date : Wed Jul 8 03:34:06 2026 -| Host : fedora running 64-bit unknown -| Command : report_utilization -hierarchical -file /home/fallensigh/vivado_reports_nodsp/utilization_hier.rpt -| Design : soc_top -| Device : 7a200tfbg676-1 -| Design State : Routed -------------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Utilization by Hierarchy - -1. Utilization by Hierarchy ---------------------------- - -+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP48 Blocks | -+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -| soc_top | (top) | 60995 | 59140 | 740 | 1115 | 39931 | 8 | 31 | 16 | -| (soc_top) | (top) | 878 | 822 | 56 | 0 | 4 | 0 | 0 | 0 | -| pll_clk.u_clk_pll | clk_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| inst | clk_pll__clk_pll_clk_wiz | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| pll_clk.u_rst_cpu | rst_sync | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| pll_clk.u_rst_mlkem | rst_sync_0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| pll_clk.u_rst_sys | rst_sync_1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_AxiCrossbar_2x8 | AxiCrossbar_2x8 | 459 | 459 | 0 | 0 | 151 | 0 | 0 | 0 | -| (u_AxiCrossbar_2x8) | AxiCrossbar_2x8 | 6 | 6 | 0 | 0 | 24 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_4 | Axi4ReadOnlyArbiter | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_82 | 18 | 18 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_5 | Axi4ReadOnlyArbiter_65 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_81 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_6 | Axi4ReadOnlyArbiter_66 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_80 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4ReadOnlyArbiter_7 | Axi4ReadOnlyArbiter_67 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_79 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_4 | Axi4WriteOnlyArbiter | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 | -| (axi4WriteOnlyArbiter_4) | Axi4WriteOnlyArbiter | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_76 | 27 | 27 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_77 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_78 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_5 | Axi4WriteOnlyArbiter_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_73 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_74 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_75 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_6 | Axi4WriteOnlyArbiter_2 | 29 | 29 | 0 | 0 | 11 | 0 | 0 | 0 | -| (axi4WriteOnlyArbiter_6) | Axi4WriteOnlyArbiter_2 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7_70 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3_71 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3_72 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | -| axi4WriteOnlyArbiter_7 | Axi4WriteOnlyArbiter_3 | 23 | 23 | 0 | 0 | 11 | 0 | 0 | 0 | -| (axi4WriteOnlyArbiter_7) | Axi4WriteOnlyArbiter_3 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | -| cmdArbiter | StreamArbiter_7 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | -| cmdRouteFork_translated_fifo | StreamFifoLowLatency_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| fifo | StreamFifo_3 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | -| axiIn_0_readOnly_decoder | Axi4ReadOnlyDecoder | 96 | 96 | 0 | 0 | 25 | 0 | 0 | 0 | -| (axiIn_0_readOnly_decoder) | Axi4ReadOnlyDecoder | 75 | 75 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4ReadOnlyErrorSlave_1_69 | 21 | 21 | 0 | 0 | 13 | 0 | 0 | 0 | -| axiIn_0_writeOnly_decoder | Axi4WriteOnlyDecoder | 40 | 40 | 0 | 0 | 18 | 0 | 0 | 0 | -| (axiIn_0_writeOnly_decoder) | Axi4WriteOnlyDecoder | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1_68 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 | -| axiIn_1_readOnly_decoder | Axi4ReadOnlyDecoder_1 | 133 | 133 | 0 | 0 | 17 | 0 | 0 | 0 | -| (axiIn_1_readOnly_decoder) | Axi4ReadOnlyDecoder_1 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 | -| errorSlave | Axi4ReadOnlyErrorSlave_1 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | -| axiIn_1_writeOnly_decoder | Axi4WriteOnlyDecoder_1 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 | -| (axiIn_1_writeOnly_decoder) | Axi4WriteOnlyDecoder_1 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 | -| errorSlave | Axi4WriteOnlyErrorSlave_1 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | -| u_Axi_CDC | Axi_CDC | 410 | 282 | 128 | 0 | 317 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3_48 | 181 | 145 | 36 | 0 | 77 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3_48 | 176 | 140 | 36 | 0 | 65 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_63 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_64 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC_49 | 103 | 67 | 36 | 0 | 79 | 0 | 0 | 0 | -| (awFifo) | StreamFifoCC_49 | 99 | 63 | 36 | 0 | 65 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_10_60 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_61 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_62 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| bFifo | StreamFifoCC_2_50 | 15 | 15 | 0 | 0 | 26 | 0 | 0 | 0 | -| (bFifo) | StreamFifoCC_2_50 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_5_57 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_4_58 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_6_59 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4_51 | 45 | 17 | 28 | 0 | 66 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4_51 | 41 | 13 | 28 | 0 | 50 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_55 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_1_56 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1_52 | 66 | 38 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1_52 | 62 | 34 | 28 | 0 | 53 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_7_53 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_8_54 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_axi_axil_adapter | axi_axil_adapter | 1073 | 1073 | 0 | 0 | 173 | 0 | 0 | 0 | -| axi_axil_adapter_rd_inst | axi_axil_adapter_rd | 498 | 498 | 0 | 0 | 85 | 0 | 0 | 0 | -| axi_axil_adapter_wr_inst | axi_axil_adapter_wr | 575 | 575 | 0 | 0 | 88 | 0 | 0 | 0 | -| u_axi_dvi | axi_dvi | 283 | 283 | 0 | 0 | 211 | 0 | 0 | 0 | -| u_axi_ram | axi_wrap_ram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | -| u_axi_sram_sp | axi2sram_sp_external | 350 | 350 | 0 | 0 | 78 | 0 | 0 | 0 | -| u_axi_uart_controller | axi_uart_controller | 683 | 667 | 16 | 0 | 457 | 0 | 0 | 0 | -| AA_axi2apb_bridge_cpu | axi2apb_bridge | 251 | 251 | 0 | 0 | 120 | 0 | 0 | 0 | -| uart0 | UART_TOP | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | -| regs | uart_regs | 432 | 416 | 16 | 0 | 337 | 0 | 0 | 0 | -| (regs) | uart_regs | 119 | 119 | 0 | 0 | 155 | 0 | 0 | 0 | -| i_uart_sync_flops | uart_sync_flops | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | -| receiver | uart_receiver | 229 | 221 | 8 | 0 | 124 | 0 | 0 | 0 | -| (receiver) | uart_receiver | 68 | 68 | 0 | 0 | 54 | 0 | 0 | 0 | -| fifo_rx | uart_rfifo | 161 | 153 | 8 | 0 | 70 | 0 | 0 | 0 | -| (fifo_rx) | uart_rfifo | 143 | 143 | 0 | 0 | 62 | 0 | 0 | 0 | -| rfifo | raminfr_47 | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | -| transmitter | uart_transmitter | 83 | 75 | 8 | 0 | 56 | 0 | 0 | 0 | -| (transmitter) | uart_transmitter | 41 | 41 | 0 | 0 | 35 | 0 | 0 | 0 | -| fifo_tx | uart_tfifo | 43 | 35 | 8 | 0 | 21 | 0 | 0 | 0 | -| (fifo_tx) | uart_tfifo | 24 | 24 | 0 | 0 | 13 | 0 | 0 | 0 | -| tfifo | raminfr | 19 | 11 | 8 | 0 | 8 | 0 | 0 | 0 | -| u_cdma_matmul_bridge | cdma_matmul_bridge | 251 | 251 | 0 | 0 | 578 | 0 | 0 | 0 | -| u_confreg | confreg | 390 | 390 | 0 | 0 | 476 | 0 | 0 | 0 | -| (u_confreg) | confreg | 230 | 230 | 0 | 0 | 399 | 0 | 0 | 0 | -| u_digitaltube_controller | digitaltube_controller | 16 | 16 | 0 | 0 | 24 | 0 | 0 | 0 | -| u_int_ctrl | int_ctrl | 144 | 144 | 0 | 0 | 53 | 0 | 0 | 0 | -| u_cpu | core_top | 8551 | 8299 | 252 | 0 | 5591 | 0 | 20 | 0 | -| (u_cpu) | core_top | 519 | 519 | 0 | 0 | 1 | 0 | 0 | 0 | -| addr_trans | addr_trans | 2247 | 2107 | 140 | 0 | 1244 | 0 | 0 | 0 | -| (addr_trans) | addr_trans | 0 | 0 | 0 | 0 | 40 | 0 | 0 | 0 | -| tlb_entry | tlb_entry | 2247 | 2107 | 140 | 0 | 1204 | 0 | 0 | 0 | -| axi_bridge | axi_bridge | 40 | 40 | 0 | 0 | 214 | 0 | 0 | 0 | -| btb | btb | 1046 | 966 | 80 | 0 | 1611 | 0 | 0 | 0 | -| (btb) | btb | 1044 | 964 | 80 | 0 | 1611 | 0 | 0 | 0 | -| dec_btb_add_entry | decoder_5_32 | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | -| dcache | dcache | 552 | 520 | 32 | 0 | 146 | 0 | 10 | 0 | -| (dcache) | dcache | 87 | 55 | 32 | 0 | 138 | 0 | 0 | 0 | -| data_ram_way[0].data_ram_bank[0].u | data_bank_sram_36 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_37 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_38 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_39 | 51 | 51 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_40 | 17 | 17 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_41 | 49 | 49 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_42 | 81 | 81 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_43 | 54 | 54 | 0 | 0 | 0 | 0 | 1 | 0 | -| lfsr | lfsr_44 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| tagv_ram_way[0].u | tagv_sram_45 | 62 | 62 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_46 | 41 | 41 | 0 | 0 | 0 | 0 | 1 | 0 | -| exe_stage | exe_stage | 663 | 663 | 0 | 0 | 233 | 0 | 0 | 0 | -| (exe_stage) | exe_stage | 632 | 632 | 0 | 0 | 233 | 0 | 0 | 0 | -| u_alu | alu | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | -| icache | icache | 235 | 235 | 0 | 0 | 55 | 0 | 10 | 0 | -| (icache) | icache | 12 | 12 | 0 | 0 | 47 | 0 | 0 | 0 | -| data_ram_way[0].data_ram_bank[0].u | data_bank_sram | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[1].u | data_bank_sram_28 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[2].u | data_bank_sram_29 | 67 | 67 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[0].data_ram_bank[3].u | data_bank_sram_30 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[0].u | data_bank_sram_31 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[1].u | data_bank_sram_32 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[2].u | data_bank_sram_33 | 35 | 35 | 0 | 0 | 0 | 0 | 1 | 0 | -| data_ram_way[1].data_ram_bank[3].u | data_bank_sram_34 | 4 | 4 | 0 | 0 | 0 | 0 | 1 | 0 | -| lfsr | lfsr | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | -| tagv_ram_way[0].u | tagv_sram | 15 | 15 | 0 | 0 | 0 | 0 | 1 | 0 | -| tagv_ram_way[1].u | tagv_sram_35 | 87 | 87 | 0 | 0 | 0 | 0 | 1 | 0 | -| id_stage | id_stage | 1054 | 1054 | 0 | 0 | 108 | 0 | 0 | 0 | -| if_stage | if_stage | 135 | 135 | 0 | 0 | 173 | 0 | 0 | 0 | -| mem_stage | mem_stage | 116 | 116 | 0 | 0 | 211 | 0 | 0 | 0 | -| u_csr | csr | 200 | 200 | 0 | 0 | 663 | 0 | 0 | 0 | -| u_div | div | 142 | 142 | 0 | 0 | 107 | 0 | 0 | 0 | -| u_mul | mul | 936 | 936 | 0 | 0 | 592 | 0 | 0 | 0 | -| wb_stage | wb_stage | 680 | 680 | 0 | 0 | 233 | 0 | 0 | 0 | -| u_fft_mlkem_axi_slave | fft_mlkem_axi_slave | 36148 | 34927 | 112 | 1109 | 27165 | 8 | 10 | 16 | -| (u_fft_mlkem_axi_slave) | fft_mlkem_axi_slave | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| u_fft_controller | fft_controller | 2646 | 1606 | 0 | 1040 | 1083 | 6 | 4 | 16 | -| (u_fft_controller) | fft_controller | 123 | 123 | 0 | 0 | 100 | 0 | 0 | 0 | -| u_FFT | FFT | 2496 | 1456 | 0 | 1040 | 983 | 6 | 0 | 16 | -| SU1 | SdfUnit | 1071 | 303 | 0 | 768 | 197 | 2 | 0 | 4 | -| (SU1) | SdfUnit | 205 | 205 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_24 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_25 | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer | 562 | 50 | 0 | 512 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized0 | 256 | 0 | 0 | 256 | 32 | 0 | 0 | 0 | -| MU | Multiply_26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_27 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU2 | SdfUnit__parameterized0 | 492 | 300 | 0 | 192 | 197 | 2 | 0 | 4 | -| (SU2) | SdfUnit__parameterized0 | 73 | 73 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_20 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized1 | 240 | 112 | 0 | 128 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized2 | 128 | 64 | 0 | 64 | 32 | 0 | 0 | 0 | -| MU | Multiply_22 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle_23 | 3 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU3 | SdfUnit__parameterized1 | 346 | 298 | 0 | 48 | 197 | 0 | 0 | 4 | -| (SU3) | SdfUnit__parameterized1 | 74 | 74 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_17 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized3 | 144 | 112 | 0 | 32 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized4 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply_19 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| SU4 | SdfUnit__parameterized2 | 327 | 295 | 0 | 32 | 197 | 2 | 0 | 4 | -| (SU4) | SdfUnit__parameterized2 | 69 | 69 | 0 | 0 | 133 | 0 | 0 | 0 | -| BF1 | Butterfly_15 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0_16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized5 | 128 | 112 | 0 | 16 | 32 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized6 | 80 | 64 | 0 | 16 | 32 | 0 | 0 | 0 | -| MU | Multiply | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 4 | -| TW | Twiddle | 2 | 2 | 0 | 0 | 0 | 2 | 0 | 0 | -| SU5 | SdfUnit__parameterized3 | 260 | 260 | 0 | 0 | 195 | 0 | 0 | 0 | -| (SU5) | SdfUnit__parameterized3 | 68 | 68 | 0 | 0 | 99 | 0 | 0 | 0 | -| BF1 | Butterfly | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | -| BF2 | Butterfly__parameterized0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| DB1 | DelayBuffer__parameterized7 | 112 | 112 | 0 | 0 | 64 | 0 | 0 | 0 | -| DB2 | DelayBuffer__parameterized8 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | -| u_in0 | my_bram0 | 3 | 3 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_in1 | my_bram0_12 | 2 | 2 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out0 | my_bram0_13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_out1 | my_bram0_14 | 25 | 25 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_mlkem_axi_cdc | Axi_CDC_5 | 421 | 309 | 112 | 0 | 272 | 0 | 0 | 0 | -| arFifo | StreamFifoCC_3 | 53 | 25 | 28 | 0 | 55 | 0 | 0 | 0 | -| (arFifo) | StreamFifoCC_3 | 44 | 16 | 28 | 0 | 43 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9_10 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| awFifo | StreamFifoCC | 40 | 16 | 24 | 0 | 49 | 0 | 0 | 0 | -| (awFifo) | StreamFifoCC | 31 | 7 | 24 | 0 | 35 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_10 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_9 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_11 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | -| bFifo | StreamFifoCC_2 | 18 | 14 | 4 | 0 | 27 | 0 | 0 | 0 | -| (bFifo) | StreamFifoCC_2 | 11 | 7 | 4 | 0 | 13 | 0 | 0 | 0 | -| bufferCC_12 | BufferCC_5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_4 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_6 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | -| rFifo | StreamFifoCC_4 | 57 | 29 | 28 | 0 | 72 | 0 | 0 | 0 | -| (rFifo) | StreamFifoCC_4 | 49 | 21 | 28 | 0 | 56 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_1 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | -| wFifo | StreamFifoCC_1 | 253 | 225 | 28 | 0 | 69 | 0 | 0 | 0 | -| (wFifo) | StreamFifoCC_1 | 248 | 220 | 28 | 0 | 53 | 0 | 0 | 0 | -| popToPushGray_buffercc | BufferCC_7 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| pushToPopGray_buffercc | BufferCC_8 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | -| u_mlkem_axi_slave | mlkem_axi_slave | 33082 | 33013 | 0 | 69 | 25804 | 2 | 6 | 0 | -| (u_mlkem_axi_slave) | mlkem_axi_slave | 1202 | 1202 | 0 | 0 | 1068 | 0 | 0 | 0 | -| u_mlkem | mlkem_top | 31884 | 31815 | 0 | 69 | 24736 | 2 | 6 | 0 | -| (u_mlkem) | mlkem_top | 2738 | 2738 | 0 | 0 | 4960 | 0 | 0 | 0 | -| u_bank_a | sd_bram__parameterized0 | 50 | 50 | 0 | 0 | 0 | 1 | 1 | 0 | -| u_bank_se | sd_bram__parameterized1 | 70 | 70 | 0 | 0 | 0 | 1 | 0 | 0 | -| u_bank_t | sd_bram__parameterized2 | 654 | 654 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_c_in_bram | sd_bram | 1312 | 1312 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_cbd | sample_cbd_sync_shared | 2741 | 2741 | 0 | 0 | 3186 | 0 | 0 | 0 | -| u_comp | comp_decomp_sync | 467 | 466 | 0 | 1 | 323 | 0 | 0 | 0 | -| u_ct_bram | sd_bram_6 | 13 | 13 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_dkp_bram | sd_bram_7 | 82 | 82 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_ek_bram | sd_bram_8 | 2121 | 2121 | 0 | 0 | 0 | 0 | 1 | 0 | -| u_keccak | keccak_core | 5274 | 5274 | 0 | 0 | 1606 | 0 | 0 | 0 | -| u_ntt | ntt_core | 8625 | 8582 | 0 | 43 | 3861 | 0 | 0 | 0 | -| (u_ntt) | ntt_core | 6101 | 6085 | 0 | 16 | 3358 | 0 | 0 | 0 | -| u_bf | butterfly_unit_pipe | 2260 | 2234 | 0 | 26 | 286 | 0 | 0 | 0 | -| (u_bf) | butterfly_unit_pipe | 69 | 44 | 0 | 25 | 75 | 0 | 0 | 0 | -| u_barrett | barrett_mul_pipe_9 | 2192 | 2191 | 0 | 1 | 211 | 0 | 0 | 0 | -| u_scl | barrett_mul_pipe | 265 | 264 | 0 | 1 | 217 | 0 | 0 | 0 | -| u_pmul | poly_mul_sync | 3881 | 3856 | 0 | 25 | 6743 | 0 | 0 | 0 | -| (u_pmul) | poly_mul_sync | 2434 | 2434 | 0 | 0 | 6280 | 0 | 0 | 0 | -| u_bc | basecase_mul_pipe | 1447 | 1422 | 0 | 25 | 463 | 0 | 0 | 0 | -| u_sha3 | sha3_top_shared | 1766 | 1766 | 0 | 0 | 2388 | 0 | 0 | 0 | -| u_snt | sample_ntt_sync_shared | 2109 | 2109 | 0 | 0 | 1669 | 0 | 0 | 0 | -| u_matmul_axi_slave | matmul_axi_slave | 9758 | 9576 | 176 | 6 | 3248 | 0 | 0 | 0 | -| (u_matmul_axi_slave) | matmul_axi_slave | 5637 | 5455 | 176 | 6 | 2480 | 0 | 0 | 0 | -| mult_inst[0].u_mult | pipelined_mult_32x32 | 1063 | 1063 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[1].u_mult | pipelined_mult_32x32_2 | 999 | 999 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[2].u_mult | pipelined_mult_32x32_3 | 1062 | 1062 | 0 | 0 | 192 | 0 | 0 | 0 | -| mult_inst[3].u_mult | pipelined_mult_32x32_4 | 997 | 997 | 0 | 0 | 192 | 0 | 0 | 0 | -| u_snix_axil_cdma_mux_8ch | snix_axil_cdma_mux | 1788 | 1788 | 0 | 0 | 1476 | 0 | 1 | 0 | -| (u_snix_axil_cdma_mux_8ch) | snix_axil_cdma_mux | 751 | 751 | 0 | 0 | 1180 | 0 | 0 | 0 | -| u_core_engine | snix_axi_mm2mm | 1038 | 1038 | 0 | 0 | 296 | 0 | 1 | 0 | -| (u_core_engine) | snix_axi_mm2mm | 762 | 762 | 0 | 0 | 243 | 0 | 0 | 0 | -| axis_fifo_u0 | snix_axis_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | -| u_fifo | snix_sync_fifo | 276 | 276 | 0 | 0 | 53 | 0 | 1 | 0 | -+------------------------------------------+------------------------------+------------+------------+---------+------+-------+--------+--------+--------------+ -* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining - -